1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
21 * DaVinci family NAND controller support for OpenOCD.
23 * This driver uses hardware ECC (1-bit or 4-bit) unless
24 * the chip is accessed in "raw" mode.
31 #include <flash/arm_nandio.h>
35 HWECC1, /* all controllers support 1-bit ECC */
36 HWECC4, /* newer chips also have 4-bit ECC hardware */
37 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
41 struct target *target;
43 uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
46 /* Async EMIF controller base */
49 /* NAND chip addresses */
50 uint32_t data; /* without CLE or ALE */
51 uint32_t cmd; /* with CLE */
52 uint32_t addr; /* with ALE */
54 /* write acceleration */
55 struct arm_nand_data io;
57 /* page i/o for the relevant flavor of hardware ECC */
58 int (*read_page)(struct nand_device *nand, uint32_t page,
59 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
60 int (*write_page)(struct nand_device *nand, uint32_t page,
61 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
64 #define NANDFCR 0x60 /* flash control register */
65 #define NANDFSR 0x64 /* flash status register */
66 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
67 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
68 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
69 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
70 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
72 static int halted(struct target *target, const char *label)
74 if (target->state == TARGET_HALTED)
77 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
81 static int davinci_init(struct nand_device *nand)
83 struct davinci_nand *info = nand->controller_priv;
84 struct target *target = info->target;
87 if (!halted(target, "init"))
88 return ERROR_NAND_OPERATION_FAILED;
90 /* We require something else to have configured AEMIF to talk
91 * to NAND chip in this range (including timings and width).
93 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
94 if (!(nandfcr & (1 << info->chipsel))) {
95 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
96 return ERROR_NAND_OPERATION_FAILED;
99 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
100 * tested. 16 bit support should work too; but not with 4-bit ECC.
106 static int davinci_reset(struct nand_device *nand)
111 static int davinci_nand_ready(struct nand_device *nand, int timeout)
113 struct davinci_nand *info = nand->controller_priv;
114 struct target *target = info->target;
117 /* NOTE: return code is zero/error, else success; not ERROR_* */
119 if (!halted(target, "ready"))
123 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
129 } while (timeout-- > 0);
134 static int davinci_command(struct nand_device *nand, uint8_t command)
136 struct davinci_nand *info = nand->controller_priv;
137 struct target *target = info->target;
139 if (!halted(target, "command"))
140 return ERROR_NAND_OPERATION_FAILED;
142 target_write_u8(target, info->cmd, command);
146 static int davinci_address(struct nand_device *nand, uint8_t address)
148 struct davinci_nand *info = nand->controller_priv;
149 struct target *target = info->target;
151 if (!halted(target, "address"))
152 return ERROR_NAND_OPERATION_FAILED;
154 target_write_u8(target, info->addr, address);
158 static int davinci_write_data(struct nand_device *nand, uint16_t data)
160 struct davinci_nand *info = nand->controller_priv;
161 struct target *target = info->target;
163 if (!halted(target, "write_data"))
164 return ERROR_NAND_OPERATION_FAILED;
166 target_write_u8(target, info->data, data);
170 static int davinci_read_data(struct nand_device *nand, void *data)
172 struct davinci_nand *info = nand->controller_priv;
173 struct target *target = info->target;
175 if (!halted(target, "read_data"))
176 return ERROR_NAND_OPERATION_FAILED;
178 target_read_u8(target, info->data, data);
182 /* REVISIT a bit of native code should let block reads be MUCH faster */
184 static int davinci_read_block_data(struct nand_device *nand,
185 uint8_t *data, int data_size)
187 struct davinci_nand *info = nand->controller_priv;
188 struct target *target = info->target;
189 uint32_t nfdata = info->data;
192 if (!halted(target, "read_block"))
193 return ERROR_NAND_OPERATION_FAILED;
195 while (data_size >= 4) {
196 target_read_u32(target, nfdata, &tmp);
207 while (data_size > 0) {
208 target_read_u8(target, nfdata, data);
217 static int davinci_write_block_data(struct nand_device *nand,
218 uint8_t *data, int data_size)
220 struct davinci_nand *info = nand->controller_priv;
221 struct target *target = info->target;
222 uint32_t nfdata = info->data;
226 if (!halted(target, "write_block"))
227 return ERROR_NAND_OPERATION_FAILED;
229 /* try the fast way first */
230 status = arm_nandwrite(&info->io, data, data_size);
231 if (status != ERROR_NAND_NO_BUFFER)
234 /* else do it slowly */
235 while (data_size >= 4) {
236 tmp = le_to_h_u32(data);
237 target_write_u32(target, nfdata, tmp);
243 while (data_size > 0) {
244 target_write_u8(target, nfdata, *data);
253 static int davinci_write_page(struct nand_device *nand, uint32_t page,
254 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
256 struct davinci_nand *info = nand->controller_priv;
257 uint8_t *ooballoc = NULL;
261 return ERROR_NAND_DEVICE_NOT_PROBED;
262 if (!halted(info->target, "write_page"))
263 return ERROR_NAND_OPERATION_FAILED;
265 /* Always write both data and OOB ... we are not "raw" I/O! */
267 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
268 return ERROR_NAND_OPERATION_FAILED;
271 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
272 switch (nand->page_size) {
283 return ERROR_NAND_OPERATION_FAILED;
286 ooballoc = malloc(oob_size);
288 return ERROR_NAND_OPERATION_FAILED;
290 memset(oob, 0x0ff, oob_size);
293 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
294 * use 512 byte chunks. Read side support will often want
295 * to include oob_size ...
297 info->io.chunk_size = nand->page_size;
299 status = info->write_page(nand, page, data, data_size, oob, oob_size);
304 static int davinci_read_page(struct nand_device *nand, uint32_t page,
305 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
307 struct davinci_nand *info = nand->controller_priv;
310 return ERROR_NAND_DEVICE_NOT_PROBED;
311 if (!halted(info->target, "read_page"))
312 return ERROR_NAND_OPERATION_FAILED;
314 return info->read_page(nand, page, data, data_size, oob, oob_size);
317 static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page)
319 struct davinci_nand *info = nand->controller_priv;
320 struct target *target = info->target;
321 int page3 = nand->address_cycles - (nand->page_size == 512);
323 /* write command ({page,otp}x{read,program} */
324 target_write_u8(target, info->cmd, cmd);
326 /* column address (beginning-of-page) */
327 target_write_u8(target, info->addr, 0);
328 if (nand->page_size > 512)
329 target_write_u8(target, info->addr, 0);
332 target_write_u8(target, info->addr, page);
333 target_write_u8(target, info->addr, page >> 8);
335 target_write_u8(target, info->addr, page >> 16);
337 target_write_u8(target, info->addr, page >> 24);
340 static int davinci_writepage_tail(struct nand_device *nand,
341 uint8_t *oob, uint32_t oob_size)
343 struct davinci_nand *info = nand->controller_priv;
344 struct target *target = info->target;
348 davinci_write_block_data(nand, oob, oob_size);
350 /* non-cachemode page program */
351 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
353 if (!davinci_nand_ready(nand, 100))
354 return ERROR_NAND_OPERATION_TIMEOUT;
356 if (nand_read_status(nand, &status) != ERROR_OK) {
357 LOG_ERROR("couldn't read status");
358 return ERROR_NAND_OPERATION_FAILED;
361 if (status & NAND_STATUS_FAIL) {
362 LOG_ERROR("write operation failed, status: 0x%02x", status);
363 return ERROR_NAND_OPERATION_FAILED;
370 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
372 static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page,
373 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
376 struct davinci_nand *info = nand->controller_priv;
377 struct target *target = info->target;
378 const uint32_t fcr_addr = info->aemif + NANDFCR;
379 const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
382 /* Write contiguous ECC bytes starting at specified offset.
383 * NOTE: Linux reserves twice as many bytes as we need; and
384 * for 16-bit OOB, those extra bytes are discontiguous.
386 switch (nand->page_size) {
398 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
400 /* scrub any old ECC state */
401 target_read_u32(target, ecc1_addr, &ecc1);
403 target_read_u32(target, fcr_addr, &fcr);
404 fcr |= 1 << (8 + info->chipsel);
407 /* set "start csX 1bit ecc" bit */
408 target_write_u32(target, fcr_addr, fcr);
410 /* write 512 bytes */
411 davinci_write_block_data(nand, data, 512);
415 /* read the ecc, pack to 3 bytes, and invert so the ecc
416 * in an erased block is correct
418 target_read_u32(target, ecc1_addr, &ecc1);
419 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
422 /* save correct ECC code into oob data */
423 oob[oob_offset++] = (uint8_t)(ecc1);
424 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
425 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
429 /* write OOB into spare area */
430 return davinci_writepage_tail(nand, oob, oob_size);
434 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
435 * slows down large page reads done with error correction (since the OOB
436 * is read first, so its ECC data can be used incrementally), but the
437 * manufacturer bad block markers are safe. Contrast: old "infix" style.
439 static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page,
440 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
442 static const uint8_t ecc512[] = {
443 0, 1, 2, 3, 4, /* 5== mfr badblock */
444 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
446 static const uint8_t ecc2048[] = {
447 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
448 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
449 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
450 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
452 static const uint8_t ecc4096[] = {
453 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
454 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
455 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
456 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
457 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
458 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
459 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
460 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
463 struct davinci_nand *info = nand->controller_priv;
465 struct target *target = info->target;
466 const uint32_t fcr_addr = info->aemif + NANDFCR;
467 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
470 /* Use the same ECC layout Linux uses. For small page chips
471 * it's a bit cramped.
473 * NOTE: at this writing, 4KB pages have issues in Linux
474 * because they need more than 64 bytes of ECC data, which
475 * the standard ECC logic can't handle.
477 switch (nand->page_size) {
489 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
491 /* scrub any old ECC state */
492 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
494 target_read_u32(target, fcr_addr, &fcr);
496 fcr |= (1 << 12) | (info->chipsel << 4);
499 uint32_t raw_ecc[4], *p;
502 /* start 4bit ecc on csX */
503 target_write_u32(target, fcr_addr, fcr);
505 /* write 512 bytes */
506 davinci_write_block_data(nand, data, 512);
510 /* read the ecc, then save it into 10 bytes in the oob */
511 for (i = 0; i < 4; i++) {
512 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
513 raw_ecc[i] &= 0x03ff03ff;
515 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
516 oob[*l++] = p[0] & 0xff;
517 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
518 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
519 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
520 oob[*l++] = (p[1] >> 18) & 0xff;
525 /* write OOB into spare area */
526 return davinci_writepage_tail(nand, oob, oob_size);
530 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
531 * manufacturer bad block markers, except on small page chips. Once you
532 * write to a page using this scheme, you need specialized code to update
533 * it (code which ignores now-invalid bad block markers).
535 * This is needed *only* to support older firmware. Older ROM Boot Loaders
536 * need it to read their second stage loader (UBL) into SRAM, but from then
537 * on the whole system can use the cleaner non-infix layouts. Systems with
538 * older second stage loaders (ABL/U-Boot, etc) or other system software
539 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
541 static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page,
542 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
544 struct davinci_nand *info = nand->controller_priv;
545 struct target *target = info->target;
546 const uint32_t fcr_addr = info->aemif + NANDFCR;
547 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
550 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
552 /* scrub any old ECC state */
553 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
555 target_read_u32(target, fcr_addr, &fcr);
557 fcr |= (1 << 12) | (info->chipsel << 4);
560 uint32_t raw_ecc[4], *p;
564 /* start 4bit ecc on csX */
565 target_write_u32(target, fcr_addr, fcr);
567 /* write 512 bytes */
568 davinci_write_block_data(nand, data, 512);
573 for (i = 0; i < 4; i++) {
574 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
575 raw_ecc[i] &= 0x03ff03ff;
578 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
579 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
581 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
582 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
583 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
584 *l++ = (p[1] >> 18) & 0xff;
587 /* write this "out-of-band" data -- infix */
588 davinci_write_block_data(nand, oob, 16);
594 /* the last data and OOB writes included the spare area */
595 return davinci_writepage_tail(nand, NULL, 0);
598 static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page,
599 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
601 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
603 /* large page devices need a start command */
604 if (nand->page_size > 512)
605 davinci_command(nand, NAND_CMD_READSTART);
607 if (!davinci_nand_ready(nand, 100))
608 return ERROR_NAND_OPERATION_TIMEOUT;
610 /* NOTE: not bothering to compute and use ECC data for now */
613 /* write 512 bytes */
614 davinci_read_block_data(nand, data, 512);
618 /* read this "out-of-band" data -- infix */
619 davinci_read_block_data(nand, oob, 16);
627 NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
629 struct davinci_nand *info;
630 struct target *target;
631 unsigned long chip, aemif;
638 * - nand chip address
641 * Plus someday, optionally, ALE and CLE masks.
644 LOG_ERROR("parameters: %s target "
645 "chip_addr hwecc_mode aemif_addr",
650 target = get_target(CMD_ARGV[1]);
652 LOG_ERROR("invalid target %s", CMD_ARGV[1]);
656 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
658 LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]);
662 if (strcmp(CMD_ARGV[3], "hwecc1") == 0)
664 else if (strcmp(CMD_ARGV[3], "hwecc4") == 0)
666 else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0)
667 eccmode = HWECC4_INFIX;
669 LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]);
673 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif);
675 LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]);
679 /* REVISIT what we'd *like* to do is look up valid ranges using
680 * target-specific declarations, and not even need to pass the
681 * AEMIF controller address.
683 if (aemif == 0x01e00000 /* dm6446, dm357 */
684 || aemif == 0x01e10000 /* dm335, dm355 */
685 || aemif == 0x01d10000 /* dm365 */
687 if (chip < 0x02000000 || chip >= 0x0a000000) {
688 LOG_ERROR("NAND address %08lx out of range?", chip);
691 chipsel = (chip - 0x02000000) >> 25;
693 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
697 info = calloc(1, sizeof *info);
701 info->target = target;
702 info->eccmode = eccmode;
703 info->chipsel = chipsel;
706 info->cmd = chip | 0x10;
707 info->addr = chip | 0x08;
709 nand->controller_priv = info;
711 info->io.target = target;
712 info->io.data = info->data;
713 info->io.op = ARM_NAND_NONE;
715 /* NOTE: for now we don't do any error correction on read.
716 * Nothing else in OpenOCD currently corrects read errors,
717 * and in any case it's *writing* that we care most about.
719 info->read_page = nand_read_page_raw;
723 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
724 info->write_page = davinci_write_page_ecc1;
727 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
728 info->write_page = davinci_write_page_ecc4;
731 /* Same 4-bit ECC HW, with problematic page/ecc layout */
732 info->read_page = davinci_read_page_ecc4infix;
733 info->write_page = davinci_write_page_ecc4infix;
740 return ERROR_NAND_OPERATION_FAILED;
743 struct nand_flash_controller davinci_nand_controller = {
745 .nand_device_command = davinci_nand_device_command,
746 .init = davinci_init,
747 .reset = davinci_reset,
748 .command = davinci_command,
749 .address = davinci_address,
750 .write_data = davinci_write_data,
751 .read_data = davinci_read_data,
752 .write_page = davinci_write_page,
753 .read_page = davinci_read_page,
754 .write_block_data = davinci_write_block_data,
755 .read_block_data = davinci_read_block_data,
756 .nand_ready = davinci_nand_ready,