1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
3 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
4 * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
6 * Partially based on drivers/mtd/nand_ids.c from Linux. *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 /* configured NAND devices and NAND Flash command handler */
30 struct nand_device *nand_devices = NULL;
32 void nand_device_add(struct nand_device *c)
35 struct nand_device *p = nand_devices;
36 while (p && p->next) p = p->next;
45 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
48 * Pagesize; 0, 256, 512
49 * 0 get this information from the extended chip ID
50 * 256 256 Byte page size
51 * 512 512 Byte page size
53 static struct nand_info nand_flash_ids[] =
55 /* start "museum" IDs */
56 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
57 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
58 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
59 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
60 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
61 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
62 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
63 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
64 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
65 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
67 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
68 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
69 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
70 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
71 /* end "museum" IDs */
73 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
74 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
75 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
76 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
78 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
79 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
80 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
81 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
83 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
84 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
85 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
86 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
88 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
89 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
90 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
91 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
92 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
93 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
94 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
96 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
98 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
99 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
100 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
101 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
103 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
104 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
105 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
106 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
108 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
109 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
110 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
111 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
113 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
114 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
115 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
116 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
118 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
119 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
120 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
121 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
123 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
124 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
125 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
126 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
128 {NULL, 0, 0, 0, 0, 0 }
131 /* Manufacturer ID list
133 static struct nand_manufacturer nand_manuf_ids[] =
136 {NAND_MFR_TOSHIBA, "Toshiba"},
137 {NAND_MFR_SAMSUNG, "Samsung"},
138 {NAND_MFR_FUJITSU, "Fujitsu"},
139 {NAND_MFR_NATIONAL, "National"},
140 {NAND_MFR_RENESAS, "Renesas"},
141 {NAND_MFR_STMICRO, "ST Micro"},
142 {NAND_MFR_HYNIX, "Hynix"},
143 {NAND_MFR_MICRON, "Micron"},
148 * Define default oob placement schemes for large and small page devices
152 static struct nand_ecclayout nand_oob_8 = {
164 * Returns the flash bank specified by @a name, which matches the
165 * driver name and a suffix (option) specify the driver-specific
166 * bank number. The suffix consists of the '.' and the driver-specific
167 * bank number: when two davinci banks are defined, then 'davinci.1' refers
168 * to the second (e.g. DM355EVM).
170 static struct nand_device *get_nand_device_by_name(const char *name)
172 unsigned requested = get_flash_name_index(name);
175 struct nand_device *nand;
176 for (nand = nand_devices; NULL != nand; nand = nand->next)
178 if (strcmp(nand->name, name) == 0)
180 if (!flash_driver_name_matches(nand->controller->name, name))
182 if (++found < requested)
189 struct nand_device *get_nand_device_by_num(int num)
191 struct nand_device *p;
194 for (p = nand_devices; p; p = p->next)
205 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
206 struct nand_device **nand)
208 const char *str = CMD_ARGV[name_index];
209 *nand = get_nand_device_by_name(str);
214 COMMAND_PARSE_NUMBER(uint, str, num);
215 *nand = get_nand_device_by_num(num);
217 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
218 return ERROR_INVALID_ARGUMENTS;
223 int nand_build_bbt(struct nand_device *nand, int first, int last)
227 int pages_per_block = (nand->erase_size / nand->page_size);
230 if ((first < 0) || (first >= nand->num_blocks))
233 if ((last >= nand->num_blocks) || (last == -1))
234 last = nand->num_blocks - 1;
236 page = first * pages_per_block;
237 for (i = first; i <= last; i++)
239 nand_read_page(nand, page, NULL, 0, oob, 6);
241 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
242 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
243 ((nand->page_size == 2048) && (oob[0] != 0xff))))
245 LOG_WARNING("bad block: %i", i);
246 nand->blocks[i].is_bad = 1;
250 nand->blocks[i].is_bad = 0;
253 page += pages_per_block;
259 int nand_read_status(struct nand_device *nand, uint8_t *status)
262 return ERROR_NAND_DEVICE_NOT_PROBED;
264 /* Send read status command */
265 nand->controller->command(nand, NAND_CMD_STATUS);
270 if (nand->device->options & NAND_BUSWIDTH_16)
273 nand->controller->read_data(nand, &data);
274 *status = data & 0xff;
278 nand->controller->read_data(nand, status);
284 static int nand_poll_ready(struct nand_device *nand, int timeout)
288 nand->controller->command(nand, NAND_CMD_STATUS);
290 if (nand->device->options & NAND_BUSWIDTH_16) {
292 nand->controller->read_data(nand, &data);
293 status = data & 0xff;
295 nand->controller->read_data(nand, &status);
297 if (status & NAND_STATUS_READY)
302 return (status & NAND_STATUS_READY) != 0;
305 int nand_probe(struct nand_device *nand)
307 uint8_t manufacturer_id, device_id;
312 /* clear device data */
314 nand->manufacturer = NULL;
316 /* clear device parameters */
318 nand->address_cycles = 0;
320 nand->erase_size = 0;
322 /* initialize controller (device parameters are zero, use controller default) */
323 if ((retval = nand->controller->init(nand) != ERROR_OK))
327 case ERROR_NAND_OPERATION_FAILED:
328 LOG_DEBUG("controller initialization failed");
329 return ERROR_NAND_OPERATION_FAILED;
330 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
331 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
332 return ERROR_NAND_OPERATION_FAILED;
334 LOG_ERROR("BUG: unknown controller initialization failure");
335 return ERROR_NAND_OPERATION_FAILED;
339 nand->controller->command(nand, NAND_CMD_RESET);
340 nand->controller->reset(nand);
342 nand->controller->command(nand, NAND_CMD_READID);
343 nand->controller->address(nand, 0x0);
345 if (nand->bus_width == 8)
347 nand->controller->read_data(nand, &manufacturer_id);
348 nand->controller->read_data(nand, &device_id);
353 nand->controller->read_data(nand, &data_buf);
354 manufacturer_id = data_buf & 0xff;
355 nand->controller->read_data(nand, &data_buf);
356 device_id = data_buf & 0xff;
359 for (i = 0; nand_flash_ids[i].name; i++)
361 if (nand_flash_ids[i].id == device_id)
363 nand->device = &nand_flash_ids[i];
368 for (i = 0; nand_manuf_ids[i].name; i++)
370 if (nand_manuf_ids[i].id == manufacturer_id)
372 nand->manufacturer = &nand_manuf_ids[i];
377 if (!nand->manufacturer)
379 nand->manufacturer = &nand_manuf_ids[0];
380 nand->manufacturer->id = manufacturer_id;
385 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
386 manufacturer_id, device_id);
387 return ERROR_NAND_OPERATION_FAILED;
390 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
392 /* initialize device parameters */
395 if (nand->device->options & NAND_BUSWIDTH_16)
396 nand->bus_width = 16;
400 /* Do we need extended device probe information? */
401 if (nand->device->page_size == 0 ||
402 nand->device->erase_size == 0)
404 if (nand->bus_width == 8)
406 nand->controller->read_data(nand, id_buff + 3);
407 nand->controller->read_data(nand, id_buff + 4);
408 nand->controller->read_data(nand, id_buff + 5);
414 nand->controller->read_data(nand, &data_buf);
415 id_buff[3] = data_buf;
417 nand->controller->read_data(nand, &data_buf);
418 id_buff[4] = data_buf;
420 nand->controller->read_data(nand, &data_buf);
421 id_buff[5] = data_buf >> 8;
426 if (nand->device->page_size == 0)
428 nand->page_size = 1 << (10 + (id_buff[4] & 3));
430 else if (nand->device->page_size == 256)
432 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
433 return ERROR_NAND_OPERATION_FAILED;
437 nand->page_size = nand->device->page_size;
440 /* number of address cycles */
441 if (nand->page_size <= 512)
443 /* small page devices */
444 if (nand->device->chip_size <= 32)
445 nand->address_cycles = 3;
446 else if (nand->device->chip_size <= 8*1024)
447 nand->address_cycles = 4;
450 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
451 nand->address_cycles = 5;
456 /* large page devices */
457 if (nand->device->chip_size <= 128)
458 nand->address_cycles = 4;
459 else if (nand->device->chip_size <= 32*1024)
460 nand->address_cycles = 5;
463 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
464 nand->address_cycles = 6;
469 if (nand->device->erase_size == 0)
471 switch ((id_buff[4] >> 4) & 3) {
473 nand->erase_size = 64 << 10;
476 nand->erase_size = 128 << 10;
479 nand->erase_size = 256 << 10;
482 nand->erase_size =512 << 10;
488 nand->erase_size = nand->device->erase_size;
491 /* initialize controller, but leave parameters at the controllers default */
492 if ((retval = nand->controller->init(nand) != ERROR_OK))
496 case ERROR_NAND_OPERATION_FAILED:
497 LOG_DEBUG("controller initialization failed");
498 return ERROR_NAND_OPERATION_FAILED;
499 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
500 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
501 nand->bus_width, nand->address_cycles, nand->page_size);
502 return ERROR_NAND_OPERATION_FAILED;
504 LOG_ERROR("BUG: unknown controller initialization failure");
505 return ERROR_NAND_OPERATION_FAILED;
509 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
510 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
512 for (i = 0; i < nand->num_blocks; i++)
514 nand->blocks[i].size = nand->erase_size;
515 nand->blocks[i].offset = i * nand->erase_size;
516 nand->blocks[i].is_erased = -1;
517 nand->blocks[i].is_bad = -1;
523 int nand_erase(struct nand_device *nand, int first_block, int last_block)
531 return ERROR_NAND_DEVICE_NOT_PROBED;
533 if ((first_block < 0) || (last_block >= nand->num_blocks))
534 return ERROR_INVALID_ARGUMENTS;
536 /* make sure we know if a block is bad before erasing it */
537 for (i = first_block; i <= last_block; i++)
539 if (nand->blocks[i].is_bad == -1)
541 nand_build_bbt(nand, i, last_block);
546 for (i = first_block; i <= last_block; i++)
548 /* Send erase setup command */
549 nand->controller->command(nand, NAND_CMD_ERASE1);
551 page = i * (nand->erase_size / nand->page_size);
553 /* Send page address */
554 if (nand->page_size <= 512)
557 nand->controller->address(nand, page & 0xff);
558 nand->controller->address(nand, (page >> 8) & 0xff);
560 /* 3rd cycle only on devices with more than 32 MiB */
561 if (nand->address_cycles >= 4)
562 nand->controller->address(nand, (page >> 16) & 0xff);
564 /* 4th cycle only on devices with more than 8 GiB */
565 if (nand->address_cycles >= 5)
566 nand->controller->address(nand, (page >> 24) & 0xff);
571 nand->controller->address(nand, page & 0xff);
572 nand->controller->address(nand, (page >> 8) & 0xff);
574 /* 3rd cycle only on devices with more than 128 MiB */
575 if (nand->address_cycles >= 5)
576 nand->controller->address(nand, (page >> 16) & 0xff);
579 /* Send erase confirm command */
580 nand->controller->command(nand, NAND_CMD_ERASE2);
582 retval = nand->controller->nand_ready ?
583 nand->controller->nand_ready(nand, 1000) :
584 nand_poll_ready(nand, 1000);
586 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
587 return ERROR_NAND_OPERATION_TIMEOUT;
590 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
592 LOG_ERROR("couldn't read status");
593 return ERROR_NAND_OPERATION_FAILED;
598 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
599 (nand->blocks[i].is_bad == 1)
602 /* continue; other blocks might still be erasable */
605 nand->blocks[i].is_erased = 1;
612 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
617 return ERROR_NAND_DEVICE_NOT_PROBED;
619 if (address % nand->page_size)
621 LOG_ERROR("reads need to be page aligned");
622 return ERROR_NAND_OPERATION_FAILED;
625 page = malloc(nand->page_size);
627 while (data_size > 0)
629 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
630 uint32_t page_address;
633 page_address = address / nand->page_size;
635 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
637 memcpy(data, page, thisrun_size);
639 address += thisrun_size;
640 data += thisrun_size;
641 data_size -= thisrun_size;
649 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
654 return ERROR_NAND_DEVICE_NOT_PROBED;
656 if (address % nand->page_size)
658 LOG_ERROR("writes need to be page aligned");
659 return ERROR_NAND_OPERATION_FAILED;
662 page = malloc(nand->page_size);
664 while (data_size > 0)
666 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
667 uint32_t page_address;
669 memset(page, 0xff, nand->page_size);
670 memcpy(page, data, thisrun_size);
672 page_address = address / nand->page_size;
674 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
676 address += thisrun_size;
677 data += thisrun_size;
678 data_size -= thisrun_size;
687 int nand_write_page(struct nand_device *nand, uint32_t page,
688 uint8_t *data, uint32_t data_size,
689 uint8_t *oob, uint32_t oob_size)
694 return ERROR_NAND_DEVICE_NOT_PROBED;
696 block = page / (nand->erase_size / nand->page_size);
697 if (nand->blocks[block].is_erased == 1)
698 nand->blocks[block].is_erased = 0;
700 if (nand->use_raw || nand->controller->write_page == NULL)
701 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
703 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
706 int nand_read_page(struct nand_device *nand, uint32_t page,
707 uint8_t *data, uint32_t data_size,
708 uint8_t *oob, uint32_t oob_size)
711 return ERROR_NAND_DEVICE_NOT_PROBED;
713 if (nand->use_raw || nand->controller->read_page == NULL)
714 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
716 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
719 int nand_page_command(struct nand_device *nand, uint32_t page,
720 uint8_t cmd, bool oob_only)
723 return ERROR_NAND_DEVICE_NOT_PROBED;
725 if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
726 cmd = NAND_CMD_READOOB;
728 nand->controller->command(nand, cmd);
730 if (nand->page_size <= 512) {
731 /* small page device */
733 /* column (always 0, we start at the beginning of a page/OOB area) */
734 nand->controller->address(nand, 0x0);
737 nand->controller->address(nand, page & 0xff);
738 nand->controller->address(nand, (page >> 8) & 0xff);
740 /* 4th cycle only on devices with more than 32 MiB */
741 if (nand->address_cycles >= 4)
742 nand->controller->address(nand, (page >> 16) & 0xff);
744 /* 5th cycle only on devices with more than 8 GiB */
745 if (nand->address_cycles >= 5)
746 nand->controller->address(nand, (page >> 24) & 0xff);
748 /* large page device */
750 /* column (0 when we start at the beginning of a page,
751 * or 2048 for the beginning of OOB area)
753 nand->controller->address(nand, 0x0);
755 nand->controller->address(nand, 0x8);
757 nand->controller->address(nand, 0x0);
760 nand->controller->address(nand, page & 0xff);
761 nand->controller->address(nand, (page >> 8) & 0xff);
763 /* 5th cycle only on devices with more than 128 MiB */
764 if (nand->address_cycles >= 5)
765 nand->controller->address(nand, (page >> 16) & 0xff);
767 /* large page devices need a start command if reading */
768 if (NAND_CMD_READ0 == cmd)
769 nand->controller->command(nand, NAND_CMD_READSTART);
772 if (nand->controller->nand_ready) {
773 if (!nand->controller->nand_ready(nand, 100))
774 return ERROR_NAND_OPERATION_TIMEOUT;
782 int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
784 int retval = ERROR_NAND_NO_BUFFER;
786 if (nand->controller->read_block_data != NULL)
787 retval = (nand->controller->read_block_data)(nand, data, size);
789 if (ERROR_NAND_NO_BUFFER == retval) {
791 int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
794 for (i = 0; retval == ERROR_OK && i < size; i += incr) {
795 retval = nand->controller->read_data(nand, data);
803 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
804 uint8_t *data, uint32_t data_size,
805 uint8_t *oob, uint32_t oob_size)
809 retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
810 if (ERROR_OK != retval)
814 nand_read_data_page(nand, data, data_size);
817 nand_read_data_page(nand, oob, oob_size);
822 int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
824 int retval = ERROR_NAND_NO_BUFFER;
826 if (nand->controller->write_block_data != NULL)
827 retval = (nand->controller->write_block_data)(nand, data, size);
829 if (ERROR_NAND_NO_BUFFER == retval) {
830 bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
831 uint32_t incr = is16bit ? 2 : 1;
835 for (i = 0; i < size; i += incr) {
837 write_data = le_to_h_u16(data);
841 retval = nand->controller->write_data(nand, write_data);
842 if (ERROR_OK != retval)
852 int nand_write_finish(struct nand_device *nand)
857 nand->controller->command(nand, NAND_CMD_PAGEPROG);
859 retval = nand->controller->nand_ready ?
860 nand->controller->nand_ready(nand, 100) :
861 nand_poll_ready(nand, 100);
863 return ERROR_NAND_OPERATION_TIMEOUT;
865 retval = nand_read_status(nand, &status);
866 if (ERROR_OK != retval) {
867 LOG_ERROR("couldn't read status");
868 return ERROR_NAND_OPERATION_FAILED;
871 if (status & NAND_STATUS_FAIL) {
872 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
874 return ERROR_NAND_OPERATION_FAILED;
880 int nand_write_page_raw(struct nand_device *nand, uint32_t page,
881 uint8_t *data, uint32_t data_size,
882 uint8_t *oob, uint32_t oob_size)
886 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
887 if (ERROR_OK != retval)
891 retval = nand_write_data_page(nand, data, data_size);
892 if (ERROR_OK != retval) {
893 LOG_ERROR("Unable to write data to NAND device");
899 retval = nand_write_data_page(nand, oob, oob_size);
900 if (ERROR_OK != retval) {
901 LOG_ERROR("Unable to write OOB data to NAND device");
906 return nand_write_finish(nand);