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   1 /*
   2  * Copyright (C) 2009 by Dean Glazeski
   3  * dnglaze@gmail.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include <target/arm.h>
  24 #include <helper/log.h>
  25 #include "imp.h"
  26 #include "arm_io.h"
  27
  28 #define AT91C_PIOx_SODR (0x30)  /**< Offset to PIO SODR. */
  29 #define AT91C_PIOx_CODR (0x34)  /**< Offset to PIO CODR. */
  30 #define AT91C_PIOx_PDSR (0x3C)  /**< Offset to PIO PDSR. */
  31 #define AT91C_ECCx_CR (0x00)    /**< Offset to ECC CR. */
  32 #define AT91C_ECCx_SR (0x08)    /**< Offset to ECC SR. */
  33 #define AT91C_ECCx_PR (0x0C)    /**< Offset to ECC PR. */
  34 #define AT91C_ECCx_NPR (0x10)   /**< Offset to ECC NPR. */
  35
  36 /**
  37  * Representation of a pin on an AT91SAM9 chip.
  38  */
  39 struct at91sam9_pin {
  40         /** Address of the PIO controller. */
  41         uint32_t pioc;
  42
  43         /** Pin number. */
  44         uint32_t num;
  45 };
  46
  47 /**
  48  * Private data for the controller that is stored in the NAND device structure.
  49  */
  50 struct at91sam9_nand {
  51         /** Address of the ECC controller for NAND. */
  52         uint32_t ecc;
  53
  54         /** Address data is written to. */
  55         uint32_t data;
  56
  57         /** Address commands are written to. */
  58         uint32_t cmd;
  59
  60         /** Address addresses are written to. */
  61         uint32_t addr;
  62
  63         /** I/O structure for hosted reads/writes. */
  64         struct arm_nand_data io;
  65
  66         /** Pin representing the ready/~busy line. */
  67         struct at91sam9_pin busy;
  68
  69         /** Pin representing the chip enable. */
  70         struct at91sam9_pin ce;
  71 };
  72
  73 /**
  74  * Checks if the target is halted and prints an error message if it isn't.
  75  *
  76  * @param target Target to be checked.
  77  * @param label String label for where function is called from.
  78  * @return True if the target is halted.
  79  */
  80 static int at91sam9_halted(struct target *target, const char *label)
  81 {
  82         if (target->state == TARGET_HALTED)
  83                 return true;
  84
  85         LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  86         return false;
  87 }
  88
  89 /**
  90  * Initialize the AT91SAM9 NAND controller.
  91  *
  92  * @param nand NAND device the controller is attached to.
  93  * @return Success or failure of initialization.
  94  */
  95 static int at91sam9_init(struct nand_device *nand)
  96 {
  97         struct target *target = nand->target;
  98
  99         if (!at91sam9_halted(target, "init"))
 100                 return ERROR_NAND_OPERATION_FAILED;
 101
 102         return ERROR_OK;
 103 }
 104
 105 /**
 106  * Enable NAND device attached to a controller.
 107  *
 108  * @param info NAND controller information for controlling NAND device.
 109  * @return Success or failure of the enabling.
 110  */
 111 static int at91sam9_enable(struct nand_device *nand)
 112 {
 113         struct at91sam9_nand *info = nand->controller_priv;
 114         struct target *target = nand->target;
 115
 116         return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
 117 }
 118
 119 /**
 120  * Disable NAND device attached to a controller.
 121  *
 122  * @param info NAND controller information for controlling NAND device.
 123  * @return Success or failure of the disabling.
 124  */
 125 static int at91sam9_disable(struct nand_device *nand)
 126 {
 127         struct at91sam9_nand *info = nand->controller_priv;
 128         struct target *target = nand->target;
 129
 130         return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
 131 }
 132
 133 /**
 134  * Send a command to the NAND device.
 135  *
 136  * @param nand NAND device to write the command to.
 137  * @param command Command to be written.
 138  * @return Success or failure of writing the command.
 139  */
 140 static int at91sam9_command(struct nand_device *nand, uint8_t command)
 141 {
 142         struct at91sam9_nand *info = nand->controller_priv;
 143         struct target *target = nand->target;
 144
 145         if (!at91sam9_halted(target, "command"))
 146                 return ERROR_NAND_OPERATION_FAILED;
 147
 148         at91sam9_enable(nand);
 149
 150         return target_write_u8(target, info->cmd, command);
 151 }
 152
 153 /**
 154  * Reset the AT91SAM9 NAND controller.
 155  *
 156  * @param nand NAND device to be reset.
 157  * @return Success or failure of reset.
 158  */
 159 static int at91sam9_reset(struct nand_device *nand)
 160 {
 161         if (!at91sam9_halted(nand->target, "reset"))
 162                 return ERROR_NAND_OPERATION_FAILED;
 163
 164         return at91sam9_disable(nand);
 165 }
 166
 167 /**
 168  * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
 169  *
 170  * @param nand NAND device to send the address to.
 171  * @param address Address to be sent.
 172  * @return Success or failure of sending the address.
 173  */
 174 static int at91sam9_address(struct nand_device *nand, uint8_t address)
 175 {
 176         struct at91sam9_nand *info = nand->controller_priv;
 177         struct target *target = nand->target;
 178
 179         if (!at91sam9_halted(nand->target, "address"))
 180                 return ERROR_NAND_OPERATION_FAILED;
 181
 182         return target_write_u8(target, info->addr, address);
 183 }
 184
 185 /**
 186  * Read data directly from the NAND device attached to an AT91SAM9 NAND
 187  * controller.
 188  *
 189  * @param nand NAND device to read from.
 190  * @param data Pointer to where the data should be put.
 191  * @return Success or failure of reading the data.
 192  */
 193 static int at91sam9_read_data(struct nand_device *nand, void *data)
 194 {
 195         struct at91sam9_nand *info = nand->controller_priv;
 196         struct target *target = nand->target;
 197
 198         if (!at91sam9_halted(nand->target, "read data"))
 199                 return ERROR_NAND_OPERATION_FAILED;
 200
 201         return target_read_u8(target, info->data, data);
 202 }
 203
 204 /**
 205  * Write data directly to the NAND device attached to an AT91SAM9 NAND
 206  * controller.
 207  *
 208  * @param nand NAND device to be written to.
 209  * @param data Data to be written.
 210  * @return Success or failure of the data write.
 211  */
 212 static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
 213 {
 214         struct at91sam9_nand *info = nand->controller_priv;
 215         struct target *target = nand->target;
 216
 217         if (!at91sam9_halted(target, "write data"))
 218                 return ERROR_NAND_OPERATION_FAILED;
 219
 220         return target_write_u8(target, info->data, data);
 221 }
 222
 223 /**
 224  * Determine if the NAND device is ready by looking at the ready/~busy pin.
 225  *
 226  * @param nand NAND device to check.
 227  * @param timeout Time in milliseconds to wait for NAND to be ready.
 228  * @return True if the NAND is ready in the timeout period.
 229  */
 230 static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
 231 {
 232         struct at91sam9_nand *info = nand->controller_priv;
 233         struct target *target = nand->target;
 234         uint32_t status;
 235
 236         if (!at91sam9_halted(target, "nand ready"))
 237                 return 0;
 238
 239         do {
 240                 target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
 241
 242                 if (status & (1 << info->busy.num))
 243                         return 1;
 244
 245                 alive_sleep(1);
 246         } while (timeout-- > 0);
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * Read a block of data from the NAND device attached to an AT91SAM9.  This
 253  * utilizes the ARM hosted NAND read function.
 254  *
 255  * @param nand NAND device to read from.
 256  * @param data Pointer to where the read data should be placed.
 257  * @param size Size of the data being read.
 258  * @return Success or failure of the hosted read.
 259  */
 260 static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
 261 {
 262         struct at91sam9_nand *info = nand->controller_priv;
 263         struct arm_nand_data *io = &info->io;
 264         int status;
 265
 266         if (!at91sam9_halted(nand->target, "read block"))
 267                 return ERROR_NAND_OPERATION_FAILED;
 268
 269         io->chunk_size = nand->page_size;
 270         status = arm_nandread(io, data, size);
 271
 272         return status;
 273 }
 274
 275 /**
 276  * Write a block of data to a NAND device attached to an AT91SAM9.  This uses
 277  * the ARM hosted write function to write the data.
 278  *
 279  * @param nand NAND device to write to.
 280  * @param data Data to be written to device.
 281  * @param size Size of the data being written.
 282  * @return Success or failure of the hosted write.
 283  */
 284 static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
 285 {
 286         struct at91sam9_nand *info = nand->controller_priv;
 287         struct arm_nand_data *io = &info->io;
 288         int status;
 289
 290         if (!at91sam9_halted(nand->target, "write block"))
 291                 return ERROR_NAND_OPERATION_FAILED;
 292
 293         io->chunk_size = nand->page_size;
 294         status = arm_nandwrite(io, data, size);
 295
 296         return status;
 297 }
 298
 299 /**
 300  * Initialize the ECC controller on the AT91SAM9.
 301  *
 302  * @param target Target to configure ECC on.
 303  * @param info NAND controller information for where the ECC is.
 304  * @return Success or failure of initialization.
 305  */
 306 static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
 307 {
 308         if (!info->ecc) {
 309                 LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
 310                 return ERROR_NAND_OPERATION_FAILED;
 311         }
 312
 313         /* reset ECC parity registers */
 314         return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
 315 }
 316
 317 /**
 318  * Initialize an area for the OOB based on whether a user is requesting the OOB
 319  * data.  This determines the size of the OOB and allocates the space in case
 320  * the user has not requested the OOB data.
 321  *
 322  * @param nand NAND device we are creating an OOB for.
 323  * @param oob Pointer to the user supplied OOB area.
 324  * @param size Size of the OOB.
 325  * @return Pointer to an area to store OOB data.
 326  */
 327 static uint8_t *at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
 328 {
 329         if (!oob) {
 330                 /* user doesn't want OOB, allocate it */
 331                 if (nand->page_size == 512)
 332                         *size = 16;
 333                 else if (nand->page_size == 2048)
 334                         *size = 64;
 335
 336                 oob = malloc(*size);
 337                 if (!oob) {
 338                         LOG_ERROR("Unable to allocate space for OOB");
 339                         return NULL;
 340                 }
 341
 342                 memset(oob, 0xFF, *size);
 343         }
 344
 345         return oob;
 346 }
 347
 348 /**
 349  * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
 350  * controller on chip.  This makes an attempt to correct any errors that are
 351  * encountered while reading the page of data.
 352  *
 353  * @param nand NAND device to read from
 354  * @param page Page to be read.
 355  * @param data Pointer to where data should be read to.
 356  * @param data_size Size of the data to be read.
 357  * @param oob Pointer to where OOB data should be read to.
 358  * @param oob_size Size of the OOB data to be read.
 359  * @return Success or failure of reading the NAND page.
 360  */
 361 static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
 362         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 363 {
 364         int retval;
 365         struct at91sam9_nand *info = nand->controller_priv;
 366         struct target *target = nand->target;
 367         uint8_t *oob_data;
 368         uint32_t status;
 369
 370         retval = at91sam9_ecc_init(target, info);
 371         if (ERROR_OK != retval)
 372                 return retval;
 373
 374         retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
 375         if (ERROR_OK != retval)
 376                 return retval;
 377
 378         if (data) {
 379                 retval = nand_read_data_page(nand, data, data_size);
 380                 if (ERROR_OK != retval)
 381                         return retval;
 382         }
 383
 384         oob_data = at91sam9_oob_init(nand, oob, &oob_size);
 385         retval = nand_read_data_page(nand, oob_data, oob_size);
 386         if (ERROR_OK == retval && data) {
 387                 target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
 388                 if (status & 1) {
 389                         LOG_ERROR("Error detected!");
 390                         if (status & 4)
 391                                 LOG_ERROR("Multiple errors encountered; unrecoverable!");
 392                         else {
 393                                 /* attempt recovery */
 394                                 uint32_t parity;
 395
 396                                 target_read_u32(target,
 397                                         info->ecc + AT91C_ECCx_PR,
 398                                         &parity);
 399                                 uint32_t word = (parity & 0x0000FFF0) >> 4;
 400                                 uint32_t bit = parity & 0x0F;
 401
 402                                 data[word] ^= (0x1) << bit;
 403                                 LOG_INFO("Data word %d, bit %d corrected.",
 404                                         (unsigned) word,
 405                                         (unsigned) bit);
 406                         }
 407                 }
 408
 409                 if (status & 2) {
 410                         /* we could write back correct ECC data */
 411                         LOG_ERROR("Error in ECC bytes detected");
 412                 }
 413         }
 414
 415         if (!oob) {
 416                 /* if it wasn't asked for, free it */
 417                 free(oob_data);
 418         }
 419
 420         return retval;
 421 }
 422
 423 /**
 424  * Write a page of data including 1-bit ECC information to a NAND device
 425  * attached to an AT91SAM9 controller.  If there is OOB data to be written,
 426  * this will ignore the computed ECC from the ECC controller.
 427  *
 428  * @param nand NAND device to write to.
 429  * @param page Page to write.
 430  * @param data Pointer to data being written.
 431  * @param data_size Size of the data being written.
 432  * @param oob Pointer to OOB data being written.
 433  * @param oob_size Size of the OOB data.
 434  * @return Success or failure of the page write.
 435  */
 436 static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
 437         uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 438 {
 439         struct at91sam9_nand *info = nand->controller_priv;
 440         struct target *target = nand->target;
 441         int retval;
 442         uint8_t *oob_data = oob;
 443         uint32_t parity, nparity;
 444
 445         retval = at91sam9_ecc_init(target, info);
 446         if (ERROR_OK != retval)
 447                 return retval;
 448
 449         retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
 450         if (ERROR_OK != retval)
 451                 return retval;
 452
 453         if (data) {
 454                 retval = nand_write_data_page(nand, data, data_size);
 455                 if (ERROR_OK != retval) {
 456                         LOG_ERROR("Unable to write data to NAND device");
 457                         return retval;
 458                 }
 459         }
 460
 461         oob_data = at91sam9_oob_init(nand, oob, &oob_size);
 462
 463         if (!oob) {
 464                 /* no OOB given, so read in the ECC parity from the ECC controller */
 465                 target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
 466                 target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
 467
 468                 oob_data[0] = (uint8_t) parity;
 469                 oob_data[1] = (uint8_t) (parity >> 8);
 470                 oob_data[2] = (uint8_t) nparity;
 471                 oob_data[3] = (uint8_t) (nparity >> 8);
 472         }
 473
 474         retval = nand_write_data_page(nand, oob_data, oob_size);
 475
 476         if (!oob)
 477                 free(oob_data);
 478
 479         if (ERROR_OK != retval) {
 480                 LOG_ERROR("Unable to write OOB data to NAND");
 481                 return retval;
 482         }
 483
 484         retval = nand_write_finish(nand);
 485
 486         return retval;
 487 }
 488
 489 /**
 490  * Handle the initial NAND device command for AT91SAM9 controllers.  This
 491  * initializes much of the controller information struct to be ready for future
 492  * reads and writes.
 493  */
 494 NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
 495 {
 496         unsigned long chip = 0, ecc = 0;
 497         struct at91sam9_nand *info = NULL;
 498
 499         LOG_DEBUG("AT91SAM9 NAND Device Command");
 500
 501         if (CMD_ARGC < 3 || CMD_ARGC > 4) {
 502                 LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
 503                 return ERROR_NAND_OPERATION_FAILED;
 504         }
 505
 506         COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
 507         if (chip == 0) {
 508                 LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
 509                 return ERROR_NAND_OPERATION_FAILED;
 510         }
 511
 512         if (CMD_ARGC == 4) {
 513                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
 514                 if (ecc == 0) {
 515                         LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
 516                         return ERROR_NAND_OPERATION_FAILED;
 517                 }
 518         }
 519
 520         info = calloc(1, sizeof(*info));
 521         if (!info) {
 522                 LOG_ERROR("unable to allocate space for controller private data");
 523                 return ERROR_NAND_OPERATION_FAILED;
 524         }
 525
 526         info->data = chip;
 527         info->cmd = chip | (1 << 22);
 528         info->addr = chip | (1 << 21);
 529         info->ecc = ecc;
 530
 531         nand->controller_priv = info;
 532         info->io.target = nand->target;
 533         info->io.data = info->data;
 534         info->io.op = ARM_NAND_NONE;
 535
 536         return ERROR_OK;
 537 }
 538
 539 /**
 540  * Handle the AT91SAM9 CLE command for specifying the address line to use for
 541  * writing commands to a NAND device.
 542  */
 543 COMMAND_HANDLER(handle_at91sam9_cle_command)
 544 {
 545         struct nand_device *nand = NULL;
 546         struct at91sam9_nand *info = NULL;
 547         unsigned num, address_line;
 548
 549         if (CMD_ARGC != 2) {
 550                 command_print(CMD_CTX, "incorrect number of arguments for 'at91sam9 cle' command");
 551                 return ERROR_OK;
 552         }
 553
 554         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
 555         nand = get_nand_device_by_num(num);
 556         if (!nand) {
 557                 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
 558                 return ERROR_OK;
 559         }
 560
 561         info = nand->controller_priv;
 562
 563         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
 564         info->cmd = info->data | (1 << address_line);
 565
 566         return ERROR_OK;
 567 }
 568
 569 /**
 570  * Handle the AT91SAM9 ALE command for specifying the address line to use for
 571  * writing addresses to the NAND device.
 572  */
 573 COMMAND_HANDLER(handle_at91sam9_ale_command)
 574 {
 575         struct nand_device *nand = NULL;
 576         struct at91sam9_nand *info = NULL;
 577         unsigned num, address_line;
 578
 579         if (CMD_ARGC != 2)
 580                 return ERROR_COMMAND_SYNTAX_ERROR;
 581
 582         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
 583         nand = get_nand_device_by_num(num);
 584         if (!nand) {
 585                 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
 586                 return ERROR_COMMAND_ARGUMENT_INVALID;
 587         }
 588
 589         info = nand->controller_priv;
 590
 591         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
 592         info->addr = info->data | (1 << address_line);
 593
 594         return ERROR_OK;
 595 }
 596
 597 /**
 598  * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
 599  * RDY/~BUSY line from the NAND device.
 600  */
 601 COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
 602 {
 603         struct nand_device *nand = NULL;
 604         struct at91sam9_nand *info = NULL;
 605         unsigned num, base_pioc, pin_num;
 606
 607         if (CMD_ARGC != 3)
 608                 return ERROR_COMMAND_SYNTAX_ERROR;
 609
 610         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
 611         nand = get_nand_device_by_num(num);
 612         if (!nand) {
 613                 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
 614                 return ERROR_COMMAND_ARGUMENT_INVALID;
 615         }
 616
 617         info = nand->controller_priv;
 618
 619         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
 620         info->busy.pioc = base_pioc;
 621
 622         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
 623         info->busy.num = pin_num;
 624
 625         return ERROR_OK;
 626 }
 627
 628 /**
 629  * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
 630  * or disable the NAND device.
 631  */
 632 COMMAND_HANDLER(handle_at91sam9_ce_command)
 633 {
 634         struct nand_device *nand = NULL;
 635         struct at91sam9_nand *info = NULL;
 636         unsigned num, base_pioc, pin_num;
 637
 638         if (CMD_ARGC != 3)
 639                 return ERROR_COMMAND_SYNTAX_ERROR;
 640
 641         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
 642         nand = get_nand_device_by_num(num);
 643         if (!nand) {
 644                 command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
 645                 return ERROR_COMMAND_ARGUMENT_INVALID;
 646         }
 647
 648         info = nand->controller_priv;
 649
 650         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
 651         info->ce.pioc = base_pioc;
 652
 653         COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
 654         info->ce.num = pin_num;
 655
 656         return ERROR_OK;
 657 }
 658
 659 static const struct command_registration at91sam9_sub_command_handlers[] = {
 660         {
 661                 .name = "cle",
 662                 .handler = handle_at91sam9_cle_command,
 663                 .mode = COMMAND_CONFIG,
 664                 .help = "set command latch enable address line (default is 22)",
 665                 .usage = "bank_id address_line",
 666         },
 667         {
 668                 .name = "ale",
 669                 .handler = handle_at91sam9_ale_command,
 670                 .mode = COMMAND_CONFIG,
 671                 .help = "set address latch enable address line (default is 21)",
 672                 .usage = "bank_id address_line",
 673         },
 674         {
 675                 .name = "rdy_busy",
 676                 .handler = handle_at91sam9_rdy_busy_command,
 677                 .mode = COMMAND_CONFIG,
 678                 .help = "set the GPIO input pin connected to "
 679                         "the RDY/~BUSY signal (no default)",
 680                 .usage = "bank_id pio_base_addr pin_num",
 681         },
 682         {
 683                 .name = "ce",
 684                 .handler = handle_at91sam9_ce_command,
 685                 .mode = COMMAND_CONFIG,
 686                 .help = "set the GPIO output pin connected to "
 687                         "the chip enable signal (no default)",
 688                 .usage = "bank_id pio_base_addr pin_num",
 689         },
 690         COMMAND_REGISTRATION_DONE
 691 };
 692
 693 static const struct command_registration at91sam9_command_handler[] = {
 694         {
 695                 .name = "at91sam9",
 696                 .mode = COMMAND_ANY,
 697                 .help = "AT91SAM9 NAND flash controller commands",
 698                 .usage = "",
 699                 .chain = at91sam9_sub_command_handlers,
 700         },
 701         COMMAND_REGISTRATION_DONE
 702 };
 703
 704 /**
 705  * Structure representing the AT91SAM9 NAND controller.
 706  */
 707 struct nand_flash_controller at91sam9_nand_controller = {
 708         .name = "at91sam9",
 709         .nand_device_command = at91sam9_nand_device_command,
 710         .commands = at91sam9_command_handler,
 711         .init = at91sam9_init,
 712         .command = at91sam9_command,
 713         .reset = at91sam9_reset,
 714         .address = at91sam9_address,
 715         .read_data = at91sam9_read_data,
 716         .write_data = at91sam9_write_data,
 717         .nand_ready = at91sam9_nand_ready,
 718         .read_block_data = at91sam9_read_block_data,
 719         .write_block_data = at91sam9_write_block_data,
 720         .read_page = at91sam9_read_page,
 721         .write_page = at91sam9_write_page,
 722 };