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   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 /*
  24  * Freescale iMX3* OpenOCD NAND Flash controller support.
  25  *
  26  * Many thanks to Ben Dooks for writing s3c24xx driver.
  27  */
  28
  29 /*
  30 driver tested with STMicro NAND512W3A @imx31
  31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
  32 get_next_halfword_from_sram_buffer() not tested
  33 */
  34 #ifdef HAVE_CONFIG_H
  35 #include "config.h"
  36 #endif
  37
  38 #include "mx3_nand.h"
  39
  40 static const char target_not_halted_err_msg[] =
  41         "target must be halted to use mx3 NAND flash controller";
  42 static const char data_block_size_err_msg[] =
  43         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  44 static const char sram_buffer_bounds_err_msg[] =
  45         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  46 static const char get_status_register_err_msg[] = "can't get NAND status";
  47 static uint32_t in_sram_address;
  48 unsigned char sign_of_sequental_byte_read;
  49
  50 static int test_iomux_settings (target_t * target, uint32_t value,
  51                                 uint32_t mask, const char *text);
  52 static int initialize_nf_controller (struct nand_device_s *device);
  53 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
  54 static int get_next_halfword_from_sram_buffer (target_t * target,
  55                                                uint16_t * value);
  56 static int poll_for_complete_op (target_t * target, const char *text);
  57 static int validate_target_state (struct nand_device_s *device);
  58 static int do_data_output (struct nand_device_s *device);
  59
  60 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
  61                                       char *cmd, char **args, int argc,
  62                                       struct nand_device_s *device);
  63 static int imx31_init (struct nand_device_s *device);
  64 static int imx31_read_data (struct nand_device_s *device, void *data);
  65 static int imx31_write_data (struct nand_device_s *device, uint16_t data);
  66 static int imx31_nand_ready (struct nand_device_s *device, int timeout);
  67 static int imx31_register_commands (struct command_context_s *cmd_ctx);
  68 static int imx31_reset (struct nand_device_s *device);
  69 static int imx31_command (struct nand_device_s *device, uint8_t command);
  70 static int imx31_address (struct nand_device_s *device, uint8_t address);
  71 static int imx31_controller_ready (struct nand_device_s *device, int tout);
  72 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
  73                              uint8_t * data, uint32_t data_size, uint8_t * oob,
  74                              uint32_t oob_size);
  75 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
  76                             uint8_t * data, uint32_t data_size, uint8_t * oob,
  77                             uint32_t oob_size);
  78
  79 nand_flash_controller_t imx31_nand_flash_controller = {
  80         .name = "imx31",
  81         .nand_device_command = imx31_nand_device_command,
  82         .register_commands = imx31_register_commands,
  83         .init = imx31_init,
  84         .reset = imx31_reset,
  85         .command = imx31_command,
  86         .address = imx31_address,
  87         .write_data = imx31_write_data,
  88         .read_data = imx31_read_data,
  89         .write_page = imx31_write_page,
  90         .read_page = imx31_read_page,
  91         .controller_ready = imx31_controller_ready,
  92         .nand_ready = imx31_nand_ready,
  93 };
  94
  95 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
  96                                       char *cmd, char **args, int argc,
  97                                       struct nand_device_s *device)
  98 {
  99         mx3_nf_controller_t *mx3_nf_info;
 100         mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
 101         if (mx3_nf_info == NULL)
 102         {
 103             LOG_ERROR ("no memory for nand controller");
 104             return ERROR_FAIL;
 105         }
 106
 107         device->controller_priv = mx3_nf_info;
 108
 109         mx3_nf_info->target = get_target (args[1]);
 110         if (mx3_nf_info->target == NULL)
 111         {
 112             LOG_ERROR ("target '%s' not defined", args[1]);
 113             return ERROR_FAIL;
 114         }
 115         if (argc < 3)
 116         {
 117             LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
 118             return ERROR_FAIL;
 119         }
 120         /*
 121         * check hwecc requirements
 122         */
 123         {
 124         int hwecc_needed;
 125         hwecc_needed = strcmp (args[2], "hwecc");
 126         if (hwecc_needed == 0)
 127             {
 128                 mx3_nf_info->flags.hw_ecc_enabled = 1;
 129             }
 130         else
 131             {
 132                 mx3_nf_info->flags.hw_ecc_enabled = 0;
 133             }
 134         }
 135
 136         mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 137         mx3_nf_info->fin = MX3_NF_FIN_NONE;
 138         mx3_nf_info->flags.target_little_endian =
 139         (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
 140         /*
 141         * testing host endianess
 142         */
 143         {
 144         int x = 1;
 145         if (*(char *) &x == 1)
 146             {
 147                 mx3_nf_info->flags.host_little_endian = 1;
 148             }
 149         else
 150             {
 151                 mx3_nf_info->flags.host_little_endian = 0;
 152             }
 153         }
 154         return ERROR_OK;
 155 }
 156
 157 static int imx31_init (struct nand_device_s *device)
 158 {
 159         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 160         target_t *target = mx3_nf_info->target;
 161
 162         {
 163         /*
 164          * validate target state
 165          */
 166         int validate_target_result;
 167         validate_target_result = validate_target_state (device);
 168         if (validate_target_result != ERROR_OK)
 169             {
 170                 return validate_target_result;
 171             }
 172         }
 173
 174         {
 175         uint16_t buffsize_register_content;
 176         target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
 177         mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 178         }
 179
 180         {
 181         uint32_t pcsr_register_content;
 182         target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
 183         if (!device->bus_width)
 184             {
 185                 device->bus_width =
 186                     (pcsr_register_content & 0x80000000) ? 16 : 8;
 187             }
 188         else
 189             {
 190                 pcsr_register_content |=
 191                     ((device->bus_width == 16) ? 0x80000000 : 0x00000000);
 192                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 193             }
 194
 195         if (!device->page_size)
 196             {
 197                 device->page_size =
 198                     (pcsr_register_content & 0x40000000) ? 2048 : 512;
 199             }
 200         else
 201             {
 202                 pcsr_register_content |=
 203                     ((device->page_size == 2048) ? 0x40000000 : 0x00000000);
 204                 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
 205             }
 206         if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048))
 207             {
 208                 LOG_ERROR
 209                     ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
 210             }
 211         }
 212
 213         {
 214         uint32_t cgr_register_content;
 215         target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
 216         if (!(cgr_register_content & 0x00000300))
 217             {
 218                 LOG_ERROR ("clock gating to EMI disabled");
 219                 return ERROR_FAIL;
 220             }
 221         }
 222
 223         {
 224         uint32_t gpr_register_content;
 225         target_read_u32 (target, MX3_GPR, &gpr_register_content);
 226         if (gpr_register_content & 0x00000060)
 227             {
 228                 LOG_ERROR ("pins mode overrided by GPR");
 229                 return ERROR_FAIL;
 230             }
 231         }
 232
 233         {
 234         /*
 235          * testing IOMUX settings; must be in "functional-mode output and
 236          * functional-mode input" mode
 237          */
 238         int test_iomux;
 239         test_iomux = ERROR_OK;
 240         test_iomux |=
 241             test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
 242         test_iomux |=
 243             test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
 244         test_iomux |=
 245             test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
 246         if (device->bus_width == 16)
 247             {
 248                 test_iomux |=
 249                     test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
 250                                          "d8,d9,d10");
 251                 test_iomux |=
 252                     test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
 253                                          "d11,d12,d13,d14");
 254                 test_iomux |=
 255                     test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
 256             }
 257         test_iomux |=
 258             test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
 259                                  "nfwp,nfce,nfrb");
 260         test_iomux |=
 261             test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
 262                                  "nfwe,nfre,nfale,nfcle");
 263         if (test_iomux != ERROR_OK)
 264             {
 265                 return ERROR_FAIL;
 266             }
 267         }
 268
 269         initialize_nf_controller (device);
 270
 271         {
 272         int retval;
 273         uint16_t nand_status_content;
 274         retval = ERROR_OK;
 275         retval |= imx31_command (device, NAND_CMD_STATUS);
 276         retval |= imx31_address (device, 0x00);
 277         retval |= do_data_output (device);
 278         if (retval != ERROR_OK)
 279             {
 280                 LOG_ERROR (get_status_register_err_msg);
 281                 return ERROR_FAIL;
 282             }
 283         target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 284         if (!(nand_status_content & 0x0080))
 285             {
 286                 /*
 287                  * is host-big-endian correctly ??
 288                  */
 289                 LOG_INFO ("NAND read-only");
 290                 mx3_nf_info->flags.nand_readonly = 1;
 291             }
 292         else
 293             {
 294                 mx3_nf_info->flags.nand_readonly = 0;
 295             }
 296         }
 297         return ERROR_OK;
 298 }
 299
 300 static int imx31_read_data (struct nand_device_s *device, void *data)
 301 {
 302         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 303         target_t *target = mx3_nf_info->target;
 304         {
 305         /*
 306          * validate target state
 307          */
 308         int validate_target_result;
 309         validate_target_result = validate_target_state (device);
 310         if (validate_target_result != ERROR_OK)
 311             {
 312                 return validate_target_result;
 313             }
 314         }
 315
 316         {
 317         /*
 318          * get data from nand chip
 319          */
 320         int try_data_output_from_nand_chip;
 321         try_data_output_from_nand_chip = do_data_output (device);
 322         if (try_data_output_from_nand_chip != ERROR_OK)
 323             {
 324                 return try_data_output_from_nand_chip;
 325             }
 326         }
 327
 328         if (device->bus_width == 16)
 329         {
 330             get_next_halfword_from_sram_buffer (target, data);
 331         }
 332         else
 333         {
 334             get_next_byte_from_sram_buffer (target, data);
 335         }
 336
 337         return ERROR_OK;
 338 }
 339
 340 static int imx31_write_data (struct nand_device_s *device, uint16_t data)
 341 {
 342         LOG_ERROR ("write_data() not implemented");
 343         return ERROR_NAND_OPERATION_FAILED;
 344 }
 345
 346 static int imx31_nand_ready (struct nand_device_s *device, int timeout)
 347 {
 348         return imx31_controller_ready (device, timeout);
 349 }
 350
 351 static int imx31_register_commands (struct command_context_s *cmd_ctx)
 352 {
 353         return ERROR_OK;
 354 }
 355
 356 static int imx31_reset (struct nand_device_s *device)
 357 {
 358         /*
 359         * validate target state
 360         */
 361         int validate_target_result;
 362         validate_target_result = validate_target_state (device);
 363         if (validate_target_result != ERROR_OK)
 364         {
 365             return validate_target_result;
 366         }
 367         initialize_nf_controller (device);
 368         return ERROR_OK;
 369 }
 370
 371 static int imx31_command (struct nand_device_s *device, uint8_t command)
 372 {
 373         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 374         target_t *target = mx3_nf_info->target;
 375         {
 376         /*
 377          * validate target state
 378          */
 379         int validate_target_result;
 380         validate_target_result = validate_target_state (device);
 381         if (validate_target_result != ERROR_OK)
 382             {
 383                 return validate_target_result;
 384             }
 385         }
 386
 387         switch (command)
 388         {
 389             case NAND_CMD_READOOB:
 390                 command = NAND_CMD_READ0;
 391                 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
 392                                                          * data_read() and
 393                                                          * read_block_data() to
 394                                                          * spare area in SRAM
 395                                                          * buffer */
 396                 break;
 397             case NAND_CMD_READ1:
 398                 command = NAND_CMD_READ0;
 399                 /*
 400                  * offset == one half of page size
 401                  */
 402                 in_sram_address =
 403                     MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1);
 404             default:
 405                 in_sram_address = MX3_NF_MAIN_BUFFER0;
 406         }
 407
 408         target_write_u16 (target, MX3_NF_FCMD, command);
 409         /*
 410         * start command input operation (set MX3_NF_BIT_OP_DONE==0)
 411         */
 412         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
 413         {
 414         int poll_result;
 415         poll_result = poll_for_complete_op (target, "command");
 416         if (poll_result != ERROR_OK)
 417             {
 418                 return poll_result;
 419             }
 420         }
 421         /*
 422         * reset cursor to begin of the buffer
 423         */
 424         sign_of_sequental_byte_read = 0;
 425         switch (command)
 426         {
 427             case NAND_CMD_READID:
 428                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
 429                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 430                 break;
 431             case NAND_CMD_STATUS:
 432                 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
 433                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 434                 break;
 435             case NAND_CMD_READ0:
 436                 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
 437                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 438                 break;
 439             default:
 440                 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
 441         }
 442         return ERROR_OK;
 443 }
 444
 445 static int imx31_address (struct nand_device_s *device, uint8_t address)
 446 {
 447         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 448         target_t *target = mx3_nf_info->target;
 449         {
 450         /*
 451          * validate target state
 452          */
 453         int validate_target_result;
 454         validate_target_result = validate_target_state (device);
 455         if (validate_target_result != ERROR_OK)
 456             {
 457                 return validate_target_result;
 458             }
 459         }
 460
 461         target_write_u16 (target, MX3_NF_FADDR, address);
 462         /*
 463         * start address input operation (set MX3_NF_BIT_OP_DONE==0)
 464         */
 465         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
 466         {
 467         int poll_result;
 468         poll_result = poll_for_complete_op (target, "address");
 469         if (poll_result != ERROR_OK)
 470             {
 471                 return poll_result;
 472             }
 473         }
 474         return ERROR_OK;
 475 }
 476
 477 static int imx31_controller_ready (struct nand_device_s *device, int tout)
 478 {
 479         uint16_t poll_complete_status;
 480         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 481         target_t *target = mx3_nf_info->target;
 482
 483         {
 484         /*
 485          * validate target state
 486          */
 487         int validate_target_result;
 488         validate_target_result = validate_target_state (device);
 489         if (validate_target_result != ERROR_OK)
 490             {
 491                 return validate_target_result;
 492             }
 493         }
 494
 495         do
 496         {
 497             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 498             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 499                 {
 500                     return tout;
 501                 }
 502             alive_sleep (1);
 503         }
 504         while (tout-- > 0);
 505         return tout;
 506 }
 507
 508 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
 509                              uint8_t * data, uint32_t data_size, uint8_t * oob,
 510                              uint32_t oob_size)
 511 {
 512         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 513         target_t *target = mx3_nf_info->target;
 514
 515         if (data_size % 2)
 516         {
 517             LOG_ERROR (data_block_size_err_msg, data_size);
 518             return ERROR_NAND_OPERATION_FAILED;
 519         }
 520         if (oob_size % 2)
 521         {
 522             LOG_ERROR (data_block_size_err_msg, oob_size);
 523             return ERROR_NAND_OPERATION_FAILED;
 524         }
 525         if (!data)
 526         {
 527             LOG_ERROR ("nothing to program");
 528             return ERROR_NAND_OPERATION_FAILED;
 529         }
 530         {
 531         /*
 532          * validate target state
 533          */
 534         int retval;
 535         retval = validate_target_state (device);
 536         if (retval != ERROR_OK)
 537             {
 538                 return retval;
 539             }
 540         }
 541         {
 542         int retval = ERROR_OK;
 543         retval |= imx31_command (device, NAND_CMD_SEQIN);
 544         retval |= imx31_address (device, 0x00);
 545         retval |= imx31_address (device, page & 0xff);
 546         retval |= imx31_address (device, (page >> 8) & 0xff);
 547         if (device->address_cycles >= 4)
 548             {
 549                 retval |= imx31_address (device, (page >> 16) & 0xff);
 550                 if (device->address_cycles >= 5)
 551                     {
 552                         retval |= imx31_address (device, (page >> 24) & 0xff);
 553                     }
 554             }
 555         target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
 556         if (oob)
 557             {
 558                 if (mx3_nf_info->flags.hw_ecc_enabled)
 559                     {
 560                         /*
 561                          * part of spare block will be overrided by hardware
 562                          * ECC generator
 563                          */
 564                         LOG_DEBUG
 565                             ("part of spare block will be overrided by hardware ECC generator");
 566                     }
 567                 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 568                                      oob);
 569             }
 570         /*
 571          * start data input operation (set MX3_NF_BIT_OP_DONE==0)
 572          */
 573         target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
 574         {
 575             int poll_result;
 576             poll_result = poll_for_complete_op (target, "data input");
 577             if (poll_result != ERROR_OK)
 578                 {
 579                     return poll_result;
 580                 }
 581         }
 582         retval |= imx31_command (device, NAND_CMD_PAGEPROG);
 583         if (retval != ERROR_OK)
 584             {
 585                 return retval;
 586             }
 587
 588         /*
 589          * check status register
 590          */
 591         {
 592             uint16_t nand_status_content;
 593             retval = ERROR_OK;
 594             retval |= imx31_command (device, NAND_CMD_STATUS);
 595             retval |= imx31_address (device, 0x00);
 596             retval |= do_data_output (device);
 597             if (retval != ERROR_OK)
 598                 {
 599                     LOG_ERROR (get_status_register_err_msg);
 600                     return retval;
 601                 }
 602             target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
 603             if (nand_status_content & 0x0001)
 604                 {
 605                     /*
 606                      * is host-big-endian correctly ??
 607                      */
 608                     return ERROR_NAND_OPERATION_FAILED;
 609                 }
 610         }
 611         }
 612         return ERROR_OK;
 613 }
 614
 615 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
 616                             uint8_t * data, uint32_t data_size, uint8_t * oob,
 617                             uint32_t oob_size)
 618 {
 619         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 620         target_t *target = mx3_nf_info->target;
 621
 622         if (data_size % 2)
 623         {
 624             LOG_ERROR (data_block_size_err_msg, data_size);
 625             return ERROR_NAND_OPERATION_FAILED;
 626         }
 627         if (oob_size % 2)
 628         {
 629             LOG_ERROR (data_block_size_err_msg, oob_size);
 630             return ERROR_NAND_OPERATION_FAILED;
 631         }
 632
 633         {
 634         /*
 635          * validate target state
 636          */
 637         int retval;
 638         retval = validate_target_state (device);
 639         if (retval != ERROR_OK)
 640             {
 641                 return retval;
 642             }
 643         }
 644         {
 645         int retval = ERROR_OK;
 646         retval |= imx31_command (device, NAND_CMD_READ0);
 647         retval |= imx31_address (device, 0x00);
 648         retval |= imx31_address (device, page & 0xff);
 649         retval |= imx31_address (device, (page >> 8) & 0xff);
 650         if (device->address_cycles >= 4)
 651             {
 652                 retval |= imx31_address (device, (page >> 16) & 0xff);
 653                 if (device->address_cycles >= 5)
 654                     {
 655                         retval |= imx31_address (device, (page >> 24) & 0xff);
 656                         retval |= imx31_command (device, NAND_CMD_READSTART);
 657                     }
 658             }
 659         retval |= do_data_output (device);
 660         if (retval != ERROR_OK)
 661             {
 662                 return retval;
 663             }
 664
 665         if (data)
 666             {
 667                 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
 668                                     data);
 669             }
 670         if (oob)
 671             {
 672                 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
 673                                     oob);
 674             }
 675         }
 676         return ERROR_OK;
 677 }
 678
 679 static int test_iomux_settings (target_t * target, uint32_t address,
 680                                 uint32_t mask, const char *text)
 681 {
 682         uint32_t register_content;
 683         target_read_u32 (target, address, &register_content);
 684         if ((register_content & mask) != (0x12121212 & mask))
 685         {
 686             LOG_ERROR ("IOMUX for {%s} is bad", text);
 687             return ERROR_FAIL;
 688         }
 689         return ERROR_OK;
 690 }
 691
 692 static int initialize_nf_controller (struct nand_device_s *device)
 693 {
 694         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 695         target_t *target = mx3_nf_info->target;
 696         /*
 697         * resets NAND flash controller in zero time ? I dont know.
 698         */
 699         target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 700         {
 701         uint16_t work_mode;
 702         work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
 703         if (target->endianness == TARGET_BIG_ENDIAN)
 704             {
 705                 work_mode |= MX3_NF_BIT_BE_EN;
 706             }
 707         if (mx3_nf_info->flags.hw_ecc_enabled)
 708             {
 709                 work_mode |= MX3_NF_BIT_ECC_EN;
 710             }
 711         target_write_u16 (target, MX3_NF_CFG1, work_mode);
 712         }
 713         /*
 714         * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 715         */
 716         target_write_u16 (target, MX3_NF_BUFCFG, 2);
 717         {
 718         uint16_t temp;
 719         target_read_u16 (target, MX3_NF_FWP, &temp);
 720         if ((temp & 0x0007) == 1)
 721             {
 722                 LOG_ERROR ("NAND flash is tight-locked, reset needed");
 723                 return ERROR_FAIL;
 724             }
 725
 726         }
 727         /*
 728         * unlock NAND flash for write
 729         */
 730         target_write_u16 (target, MX3_NF_FWP, 4);
 731         target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
 732         target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
 733         /*
 734         * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
 735         */
 736         target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
 737         /*
 738         * address of SRAM buffer
 739         */
 740         in_sram_address = MX3_NF_MAIN_BUFFER0;
 741         sign_of_sequental_byte_read = 0;
 742         return ERROR_OK;
 743 }
 744
 745 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
 746 {
 747         static uint8_t even_byte = 0;
 748         /*
 749         * host-big_endian ??
 750         */
 751         if (sign_of_sequental_byte_read == 0)
 752         {
 753             even_byte = 0;
 754         }
 755         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 756         {
 757             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 758             *value = 0;
 759             sign_of_sequental_byte_read = 0;
 760             even_byte = 0;
 761             return ERROR_NAND_OPERATION_FAILED;
 762         }
 763         else
 764         {
 765             uint16_t temp;
 766             target_read_u16 (target, in_sram_address, &temp);
 767             if (even_byte)
 768                 {
 769                     *value = temp >> 8;
 770                     even_byte = 0;
 771                     in_sram_address += 2;
 772                 }
 773             else
 774                 {
 775                     *value = temp & 0xff;
 776                     even_byte = 1;
 777                 }
 778         }
 779         sign_of_sequental_byte_read = 1;
 780         return ERROR_OK;
 781 }
 782
 783 static int get_next_halfword_from_sram_buffer (target_t * target,
 784                                                uint16_t * value)
 785 {
 786         if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
 787         {
 788             LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
 789             *value = 0;
 790             return ERROR_NAND_OPERATION_FAILED;
 791         }
 792         else
 793         {
 794             target_read_u16 (target, in_sram_address, value);
 795             in_sram_address += 2;
 796         }
 797         return ERROR_OK;
 798 }
 799
 800 static int poll_for_complete_op (target_t * target, const char *text)
 801 {
 802         uint16_t poll_complete_status;
 803         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
 804         {
 805             usleep (25);
 806             target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
 807             if (poll_complete_status & MX3_NF_BIT_OP_DONE)
 808                 {
 809                     break;
 810                 }
 811         }
 812         if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
 813         {
 814             LOG_ERROR ("%s sending timeout", text);
 815             return ERROR_NAND_OPERATION_FAILED;
 816         }
 817         return ERROR_OK;
 818 }
 819
 820 static int validate_target_state (struct nand_device_s *device)
 821 {
 822         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 823         target_t *target = mx3_nf_info->target;
 824
 825         if (target->state != TARGET_HALTED)
 826         {
 827             LOG_ERROR (target_not_halted_err_msg);
 828             return ERROR_NAND_OPERATION_FAILED;
 829         }
 830
 831         if (mx3_nf_info->flags.target_little_endian !=
 832         (target->endianness == TARGET_LITTLE_ENDIAN))
 833         {
 834             /*
 835              * endianness changed after NAND controller probed
 836              */
 837             return ERROR_NAND_OPERATION_FAILED;
 838         }
 839         return ERROR_OK;
 840 }
 841
 842 static int do_data_output (struct nand_device_s *device)
 843 {
 844         mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
 845         target_t *target = mx3_nf_info->target;
 846         switch (mx3_nf_info->fin)
 847         {
 848             case MX3_NF_FIN_DATAOUT:
 849                 /*
 850                  * start data output operation (set MX3_NF_BIT_OP_DONE==0)
 851                  */
 852                 target_write_u16 (target, MX3_NF_CFG2,
 853                                   MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
 854                                                            optype));
 855                 {
 856                     int poll_result;
 857                     poll_result = poll_for_complete_op (target, "data output");
 858                     if (poll_result != ERROR_OK)
 859                         {
 860                             return poll_result;
 861                         }
 862                 }
 863                 mx3_nf_info->fin = MX3_NF_FIN_NONE;
 864                 /*
 865                  * ECC stuff
 866                  */
 867                 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
 868                     && mx3_nf_info->flags.hw_ecc_enabled)
 869                     {
 870                         uint16_t ecc_status;
 871                         target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 872                         switch (ecc_status & 0x000c)
 873                             {
 874                                 case 1 << 2:
 875                                     LOG_DEBUG
 876                                         ("main area readed with 1 (correctable) error");
 877                                     break;
 878                                 case 2 << 2:
 879                                     LOG_DEBUG
 880                                         ("main area readed with more than 1 (incorrectable) error");
 881                                     return ERROR_NAND_OPERATION_FAILED;
 882                                     break;
 883                             }
 884                         switch (ecc_status & 0x0003)
 885                             {
 886                                 case 1:
 887                                     LOG_DEBUG
 888                                         ("spare area readed with 1 (correctable) error");
 889                                     break;
 890                                 case 2:
 891                                     LOG_DEBUG
 892                                         ("main area readed with more than 1 (incorrectable) error");
 893                                     return ERROR_NAND_OPERATION_FAILED;
 894                                     break;
 895                             }
 896                     }
 897                 break;
 898             case MX3_NF_FIN_NONE:
 899                 break;
 900         }
 901         return ERROR_OK;
 902 }