git.gag.com Git - fw/openocd/blob - src/flash/lpc3180_nand_controller.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "lpc3180_nand_controller.h"
  25 #include "nand.h"
  26
  27 static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
  28 static int lpc3180_register_commands(struct command_context_s *cmd_ctx);
  29 static int lpc3180_init(struct nand_device_s *device);
  30 static int lpc3180_reset(struct nand_device_s *device);
  31 static int lpc3180_command(struct nand_device_s *device, uint8_t command);
  32 static int lpc3180_address(struct nand_device_s *device, uint8_t address);
  33 static int lpc3180_write_data(struct nand_device_s *device, uint16_t data);
  34 static int lpc3180_read_data(struct nand_device_s *device, void *data);
  35 static int lpc3180_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  36 static int lpc3180_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
  37 static int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
  38 static int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
  39
  40 static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41
  42 nand_flash_controller_t lpc3180_nand_controller =
  43 {
  44         .name = "lpc3180",
  45         .nand_device_command = lpc3180_nand_device_command,
  46         .register_commands = lpc3180_register_commands,
  47         .init = lpc3180_init,
  48         .reset = lpc3180_reset,
  49         .command = lpc3180_command,
  50         .address = lpc3180_address,
  51         .write_data = lpc3180_write_data,
  52         .read_data = lpc3180_read_data,
  53         .write_page = lpc3180_write_page,
  54         .read_page = lpc3180_read_page,
  55         .controller_ready = lpc3180_controller_ready,
  56         .nand_ready = lpc3180_nand_ready,
  57 };
  58
  59 /* nand device lpc3180 <target#> <oscillator_frequency>
  60  */
  61 static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
  62 {
  63         if (argc < 3)
  64         {
  65                 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
  66                 return ERROR_FLASH_BANK_INVALID;
  67         }
  68
  69         target_t *target = get_target(args[1]);
  70         if (NULL == target)
  71         {
  72                 LOG_ERROR("target '%s' not defined", args[1]);
  73                 return ERROR_NAND_DEVICE_INVALID;
  74         }
  75
  76         uint32_t osc_freq;
  77         COMMAND_PARSE_NUMBER(u32, args[2], osc_freq);
  78
  79         lpc3180_nand_controller_t *lpc3180_info;
  80         lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
  81         device->controller_priv = lpc3180_info;
  82
  83         lpc3180_info->target = target;
  84         lpc3180_info->osc_freq = osc_freq;
  85
  86         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  87         {
  88                 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
  89         }
  90         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  91         lpc3180_info->sw_write_protection = 0;
  92         lpc3180_info->sw_wp_lower_bound = 0x0;
  93         lpc3180_info->sw_wp_upper_bound = 0x0;
  94
  95         return ERROR_OK;
  96 }
  97
  98 static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
  99 {
 100         command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
 101
 102         register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
 103
 104         return ERROR_OK;
 105 }
 106
 107 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
 108 {
 109         int bypass = (pll_ctrl & 0x8000) >> 15;
 110         int direct = (pll_ctrl & 0x4000) >> 14;
 111         int feedback = (pll_ctrl & 0x2000) >> 13;
 112         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
 113         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
 114         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
 115         int lock = (pll_ctrl & 0x1);
 116
 117         if (!lock)
 118                 LOG_WARNING("PLL is not locked");
 119
 120         if (!bypass && direct)  /* direct mode */
 121                 return (m * fclkin) / n;
 122
 123         if (bypass && !direct)  /* bypass mode */
 124                 return fclkin / (2 * p);
 125
 126         if (bypass & direct)    /* direct bypass mode */
 127                 return fclkin;
 128
 129         if (feedback)                   /* integer mode */
 130                 return m * (fclkin / n);
 131         else                                    /* non-integer mode */
 132                 return (m / (2 * p)) * (fclkin / n);
 133 }
 134
 135 static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
 136 {
 137         target_t *target = lpc3180_info->target;
 138         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 139         int sysclk;
 140         int hclk;
 141         int hclk_pll;
 142         float cycle;
 143
 144         /* calculate timings */
 145
 146         /* determine current SYSCLK (13'MHz or main oscillator) */
 147         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 148
 149         if ((sysclk_ctrl & 1) == 0)
 150                 sysclk = lpc3180_info->osc_freq;
 151         else
 152                 sysclk = 13000;
 153
 154         /* determine selected HCLK source */
 155         target_read_u32(target, 0x40004044, &pwr_ctrl);
 156
 157         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 158         {
 159                 hclk = sysclk;
 160         }
 161         else
 162         {
 163                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 164                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 165
 166                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 167
 168                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 169                 {
 170                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 171                 }
 172                 else /* HCLK uses HCLK_PLL */
 173                 {
 174                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 175                 }
 176         }
 177
 178         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 179
 180         cycle = (1.0 / hclk) * 1000000.0;
 181
 182         return cycle;
 183 }
 184
 185 static int lpc3180_init(struct nand_device_s *device)
 186 {
 187         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 188         target_t *target = lpc3180_info->target;
 189         int bus_width = (device->bus_width) ? (device->bus_width) : 8;
 190         int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3;
 191         int page_size = (device->page_size) ? (device->page_size) : 512;
 192
 193         if (target->state != TARGET_HALTED)
 194         {
 195                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 196                 return ERROR_NAND_OPERATION_FAILED;
 197         }
 198
 199         /* sanitize arguments */
 200         if ((bus_width != 8) && (bus_width != 16))
 201         {
 202                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 203                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 204         }
 205
 206         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 207          * would support 16 bit, too, so we just warn about this for now
 208          */
 209         if (bus_width == 16)
 210         {
 211                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 212         }
 213
 214         /* inform calling code about selected bus width */
 215         device->bus_width = bus_width;
 216
 217         if ((address_cycles != 3) && (address_cycles != 4))
 218         {
 219                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 220                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 221         }
 222
 223         if ((page_size != 512) && (page_size != 2048))
 224         {
 225                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 226                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 227         }
 228
 229         /* select MLC controller if none is currently selected */
 230         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 231         {
 232                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 233                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 234         }
 235
 236         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 237         {
 238                 uint32_t mlc_icr_value = 0x0;
 239                 float cycle;
 240                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 241
 242                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 243                 target_write_u32(target, 0x400040c8, 0x22);
 244
 245                 /* MLC_CEH = 0x0 (Force nCE assert) */
 246                 target_write_u32(target, 0x200b804c, 0x0);
 247
 248                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 249                 target_write_u32(target, 0x200b8044, 0xa25e);
 250
 251                 /* MLC_ICR = configuration */
 252                 if (lpc3180_info->sw_write_protection)
 253                         mlc_icr_value |= 0x8;
 254                 if (page_size == 2048)
 255                         mlc_icr_value |= 0x4;
 256                 if (address_cycles == 4)
 257                         mlc_icr_value |= 0x2;
 258                 if (bus_width == 16)
 259                         mlc_icr_value |= 0x1;
 260                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 261
 262                 /* calculate NAND controller timings */
 263                 cycle = lpc3180_cycle_time(lpc3180_info);
 264
 265                 twp = ((40 / cycle) + 1);
 266                 twh = ((20 / cycle) + 1);
 267                 trp = ((30 / cycle) + 1);
 268                 treh = ((15 / cycle) + 1);
 269                 trhz = ((30 / cycle) + 1);
 270                 trbwb = ((100 / cycle) + 1);
 271                 tcea = ((45 / cycle) + 1);
 272
 273                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 274                 target_write_u32(target, 0x200b8044, 0xa25e);
 275
 276                 /* MLC_TIME_REG */
 277                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 278                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 279                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 280
 281                 lpc3180_reset(device);
 282         }
 283         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 284         {
 285                 float cycle;
 286                 int r_setup, r_hold, r_width, r_rdy;
 287                 int w_setup, w_hold, w_width, w_rdy;
 288
 289                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 290                 target_write_u32(target, 0x400040c8, 0x05);
 291
 292                 /* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
 293                 target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
 294
 295                 /* calculate NAND controller timings */
 296                 cycle = lpc3180_cycle_time(lpc3180_info);
 297
 298                 r_setup = w_setup = 0;
 299                 r_hold = w_hold = 10 / cycle;
 300                 r_width = 30 / cycle;
 301                 w_width = 40 / cycle;
 302                 r_rdy = w_rdy = 100 / cycle;
 303
 304                 /* SLC_TAC: SLC timing arcs register */
 305                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 306                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 307                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 308
 309                 lpc3180_reset(device);
 310         }
 311
 312         return ERROR_OK;
 313 }
 314
 315 static int lpc3180_reset(struct nand_device_s *device)
 316 {
 317         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 318         target_t *target = lpc3180_info->target;
 319
 320         if (target->state != TARGET_HALTED)
 321         {
 322                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 323                 return ERROR_NAND_OPERATION_FAILED;
 324         }
 325
 326         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 327         {
 328                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 329                 return ERROR_NAND_OPERATION_FAILED;
 330         }
 331         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 332         {
 333                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 334                 target_write_u32(target, 0x200b8000, 0xff);
 335
 336                 if (!lpc3180_controller_ready(device, 100))
 337                 {
 338                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 339                         return ERROR_NAND_OPERATION_TIMEOUT;
 340                 }
 341         }
 342         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 343         {
 344                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 345                 target_write_u32(target, 0x20020010, 0x6);
 346
 347                 if (!lpc3180_controller_ready(device, 100))
 348                 {
 349                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 350                         return ERROR_NAND_OPERATION_TIMEOUT;
 351                 }
 352         }
 353
 354         return ERROR_OK;
 355 }
 356
 357 static int lpc3180_command(struct nand_device_s *device, uint8_t command)
 358 {
 359         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 360         target_t *target = lpc3180_info->target;
 361
 362         if (target->state != TARGET_HALTED)
 363         {
 364                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 365                 return ERROR_NAND_OPERATION_FAILED;
 366         }
 367
 368         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 369         {
 370                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 371                 return ERROR_NAND_OPERATION_FAILED;
 372         }
 373         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 374         {
 375                 /* MLC_CMD = command */
 376                 target_write_u32(target, 0x200b8000, command);
 377         }
 378         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 379         {
 380                 /* SLC_CMD = command */
 381                 target_write_u32(target, 0x20020008, command);
 382         }
 383
 384         return ERROR_OK;
 385 }
 386
 387 static int lpc3180_address(struct nand_device_s *device, uint8_t address)
 388 {
 389         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 390         target_t *target = lpc3180_info->target;
 391
 392         if (target->state != TARGET_HALTED)
 393         {
 394                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 395                 return ERROR_NAND_OPERATION_FAILED;
 396         }
 397
 398         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 399         {
 400                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 401                 return ERROR_NAND_OPERATION_FAILED;
 402         }
 403         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 404         {
 405                 /* MLC_ADDR = address */
 406                 target_write_u32(target, 0x200b8004, address);
 407         }
 408         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 409         {
 410                 /* SLC_ADDR = address */
 411                 target_write_u32(target, 0x20020004, address);
 412         }
 413
 414         return ERROR_OK;
 415 }
 416
 417 static int lpc3180_write_data(struct nand_device_s *device, uint16_t data)
 418 {
 419         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 420         target_t *target = lpc3180_info->target;
 421
 422         if (target->state != TARGET_HALTED)
 423         {
 424                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 425                 return ERROR_NAND_OPERATION_FAILED;
 426         }
 427
 428         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 429         {
 430                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 431                 return ERROR_NAND_OPERATION_FAILED;
 432         }
 433         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 434         {
 435                 /* MLC_DATA = data */
 436                 target_write_u32(target, 0x200b0000, data);
 437         }
 438         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 439         {
 440                 /* SLC_DATA = data */
 441                 target_write_u32(target, 0x20020000, data);
 442         }
 443
 444         return ERROR_OK;
 445 }
 446
 447 static int lpc3180_read_data(struct nand_device_s *device, void *data)
 448 {
 449         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 450         target_t *target = lpc3180_info->target;
 451
 452         if (target->state != TARGET_HALTED)
 453         {
 454                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 455                 return ERROR_NAND_OPERATION_FAILED;
 456         }
 457
 458         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 459         {
 460                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 461                 return ERROR_NAND_OPERATION_FAILED;
 462         }
 463         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 464         {
 465                 /* data = MLC_DATA, use sized access */
 466                 if (device->bus_width == 8)
 467                 {
 468                         uint8_t *data8 = data;
 469                         target_read_u8(target, 0x200b0000, data8);
 470                 }
 471                 else if (device->bus_width == 16)
 472                 {
 473                         uint16_t *data16 = data;
 474                         target_read_u16(target, 0x200b0000, data16);
 475                 }
 476                 else
 477                 {
 478                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 479                         return ERROR_NAND_OPERATION_FAILED;
 480                 }
 481         }
 482         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 483         {
 484                 uint32_t data32;
 485
 486                 /* data = SLC_DATA, must use 32-bit access */
 487                 target_read_u32(target, 0x20020000, &data32);
 488
 489                 if (device->bus_width == 8)
 490                 {
 491                         uint8_t *data8 = data;
 492                         *data8 = data32 & 0xff;
 493                 }
 494                 else if (device->bus_width == 16)
 495                 {
 496                         uint16_t *data16 = data;
 497                         *data16 = data32 & 0xffff;
 498                 }
 499                 else
 500                 {
 501                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 502                         return ERROR_NAND_OPERATION_FAILED;
 503                 }
 504         }
 505
 506         return ERROR_OK;
 507 }
 508
 509 static int lpc3180_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 510 {
 511         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 512         target_t *target = lpc3180_info->target;
 513         int retval;
 514         uint8_t status;
 515
 516         if (target->state != TARGET_HALTED)
 517         {
 518                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 519                 return ERROR_NAND_OPERATION_FAILED;
 520         }
 521
 522         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 523         {
 524                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 525                 return ERROR_NAND_OPERATION_FAILED;
 526         }
 527         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 528         {
 529                 uint8_t *page_buffer;
 530                 uint8_t *oob_buffer;
 531                 int quarter, num_quarters;
 532
 533                 if (!data && oob)
 534                 {
 535                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 536                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 537                 }
 538
 539                 if (oob && (oob_size > 6))
 540                 {
 541                         LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
 542                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 543                 }
 544
 545                 if (data_size > (uint32_t)device->page_size)
 546                 {
 547                         LOG_ERROR("data size exceeds page size");
 548                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 549                 }
 550
 551                 /* MLC_CMD = sequential input */
 552                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 553
 554                 page_buffer = malloc(512);
 555                 oob_buffer = malloc(6);
 556
 557                 if (device->page_size == 512)
 558                 {
 559                         /* MLC_ADDR = 0x0 (one column cycle) */
 560                         target_write_u32(target, 0x200b8004, 0x0);
 561
 562                         /* MLC_ADDR = row */
 563                         target_write_u32(target, 0x200b8004, page & 0xff);
 564                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 565
 566                         if (device->address_cycles == 4)
 567                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 568                 }
 569                 else
 570                 {
 571                         /* MLC_ADDR = 0x0 (two column cycles) */
 572                         target_write_u32(target, 0x200b8004, 0x0);
 573                         target_write_u32(target, 0x200b8004, 0x0);
 574
 575                         /* MLC_ADDR = row */
 576                         target_write_u32(target, 0x200b8004, page & 0xff);
 577                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 578                 }
 579
 580                 /* when using the MLC controller, we have to treat a large page device
 581                  * as being made out of four quarters, each the size of a small page device
 582                  */
 583                 num_quarters = (device->page_size == 2048) ? 4 : 1;
 584
 585                 for (quarter = 0; quarter < num_quarters; quarter++)
 586                 {
 587                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 588                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 589
 590                         memset(page_buffer, 0xff, 512);
 591                         if (data)
 592                         {
 593                                 memcpy(page_buffer, data, thisrun_data_size);
 594                                 data_size -= thisrun_data_size;
 595                                 data += thisrun_data_size;
 596                         }
 597
 598                         memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24);
 599                         if (oob)
 600                         {
 601                                 memcpy(page_buffer, oob, thisrun_oob_size);
 602                                 oob_size -= thisrun_oob_size;
 603                                 oob += thisrun_oob_size;
 604                         }
 605
 606                         /* write MLC_ECC_ENC_REG to start encode cycle */
 607                         target_write_u32(target, 0x200b8008, 0x0);
 608
 609                         target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
 610                         target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
 611
 612                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 613                         target_write_u32(target, 0x200b8010, 0x0);
 614
 615                         if (!lpc3180_controller_ready(device, 1000))
 616                         {
 617                                 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
 618                                 return ERROR_NAND_OPERATION_FAILED;
 619                         }
 620                 }
 621
 622                 /* MLC_CMD = auto program command */
 623                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 624
 625                 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
 626                 {
 627                         LOG_ERROR("couldn't read status");
 628                         return ERROR_NAND_OPERATION_FAILED;
 629                 }
 630
 631                 if (status & NAND_STATUS_FAIL)
 632                 {
 633                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 634                         return ERROR_NAND_OPERATION_FAILED;
 635                 }
 636
 637                 free(page_buffer);
 638                 free(oob_buffer);
 639         }
 640         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 641         {
 642                 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
 643         }
 644
 645         return ERROR_OK;
 646 }
 647
 648 static int lpc3180_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 649 {
 650         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 651         target_t *target = lpc3180_info->target;
 652
 653         if (target->state != TARGET_HALTED)
 654         {
 655                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 656                 return ERROR_NAND_OPERATION_FAILED;
 657         }
 658
 659         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 660         {
 661                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 662                 return ERROR_NAND_OPERATION_FAILED;
 663         }
 664         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 665         {
 666                 uint8_t *page_buffer;
 667                 uint8_t *oob_buffer;
 668                 uint32_t page_bytes_done = 0;
 669                 uint32_t oob_bytes_done = 0;
 670                 uint32_t mlc_isr;
 671
 672 #if 0
 673                 if (oob && (oob_size > 6))
 674                 {
 675                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 676                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 677                 }
 678 #endif
 679
 680                 if (data_size > (uint32_t)device->page_size)
 681                 {
 682                         LOG_ERROR("data size exceeds page size");
 683                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 684                 }
 685
 686                 if (device->page_size == 2048)
 687                 {
 688                         page_buffer = malloc(2048);
 689                         oob_buffer = malloc(64);
 690                 }
 691                 else
 692                 {
 693                         page_buffer = malloc(512);
 694                         oob_buffer = malloc(16);
 695                 }
 696
 697                 if (!data && oob)
 698                 {
 699                         /* MLC_CMD = Read OOB
 700                          * we can use the READOOB command on both small and large page devices,
 701                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 702                          * positioning of the serial buffer read pointer
 703                          */
 704                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 705                 }
 706                 else
 707                 {
 708                         /* MLC_CMD = Read0 */
 709                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 710                 }
 711
 712                 if (device->page_size == 512)
 713                 {
 714                         /* small page device */
 715                         /* MLC_ADDR = 0x0 (one column cycle) */
 716                         target_write_u32(target, 0x200b8004, 0x0);
 717
 718                         /* MLC_ADDR = row */
 719                         target_write_u32(target, 0x200b8004, page & 0xff);
 720                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 721
 722                         if (device->address_cycles == 4)
 723                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 724                 }
 725                 else
 726                 {
 727                         /* large page device */
 728                         /* MLC_ADDR = 0x0 (two column cycles) */
 729                         target_write_u32(target, 0x200b8004, 0x0);
 730                         target_write_u32(target, 0x200b8004, 0x0);
 731
 732                         /* MLC_ADDR = row */
 733                         target_write_u32(target, 0x200b8004, page & 0xff);
 734                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 735
 736                         /* MLC_CMD = Read Start */
 737                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 738                 }
 739
 740                 while (page_bytes_done < (uint32_t)device->page_size)
 741                 {
 742                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 743                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 744
 745                         if (!lpc3180_controller_ready(device, 1000))
 746                         {
 747                                 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
 748                                 return ERROR_NAND_OPERATION_FAILED;
 749                         }
 750
 751                         target_read_u32(target, 0x200b8048, &mlc_isr);
 752
 753                         if (mlc_isr & 0x8)
 754                         {
 755                                 if (mlc_isr & 0x40)
 756                                 {
 757                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
 758                                         return ERROR_NAND_OPERATION_FAILED;
 759                                 }
 760
 761                                 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
 762                         }
 763
 764                         if (data)
 765                         {
 766                                 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
 767                         }
 768
 769                         if (oob)
 770                         {
 771                                 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
 772                         }
 773
 774                         page_bytes_done += 512;
 775                         oob_bytes_done += 16;
 776                 }
 777
 778                 if (data)
 779                         memcpy(data, page_buffer, data_size);
 780
 781                 if (oob)
 782                         memcpy(oob, oob_buffer, oob_size);
 783
 784                 free(page_buffer);
 785                 free(oob_buffer);
 786         }
 787         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 788         {
 789                 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
 790         }
 791
 792         return ERROR_OK;
 793 }
 794
 795 static int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
 796 {
 797         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 798         target_t *target = lpc3180_info->target;
 799         uint8_t status = 0x0;
 800
 801         if (target->state != TARGET_HALTED)
 802         {
 803                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 804                 return ERROR_NAND_OPERATION_FAILED;
 805         }
 806
 807         do
 808         {
 809                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 810                 {
 811                         /* Read MLC_ISR, wait for controller to become ready */
 812                         target_read_u8(target, 0x200b8048, &status);
 813
 814                         if (status & 2)
 815                                 return 1;
 816                 }
 817                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 818                 {
 819                         /* we pretend that the SLC controller is always ready */
 820                         return 1;
 821                 }
 822
 823                 alive_sleep(1);
 824         } while (timeout-- > 0);
 825
 826         return 0;
 827 }
 828
 829 static int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
 830 {
 831         lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
 832         target_t *target = lpc3180_info->target;
 833
 834         if (target->state != TARGET_HALTED)
 835         {
 836                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 837                 return ERROR_NAND_OPERATION_FAILED;
 838         }
 839
 840         do
 841         {
 842                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 843                 {
 844                         uint8_t status = 0x0;
 845
 846                         /* Read MLC_ISR, wait for NAND flash device to become ready */
 847                         target_read_u8(target, 0x200b8048, &status);
 848
 849                         if (status & 1)
 850                                 return 1;
 851                 }
 852                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 853                 {
 854                         uint32_t status = 0x0;
 855
 856                         /* Read SLC_STAT and check READY bit */
 857                         target_read_u32(target, 0x20020018, &status);
 858
 859                         if (status & 1)
 860                                 return 1;
 861                 }
 862
 863                 alive_sleep(1);
 864         } while (timeout-- > 0);
 865
 866         return 0;
 867 }
 868
 869 static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 870 {
 871         lpc3180_nand_controller_t *lpc3180_info = NULL;
 872         char *selected[] =
 873         {
 874                 "no", "mlc", "slc"
 875         };
 876
 877         if ((argc < 1) || (argc > 2))
 878         {
 879                 return ERROR_COMMAND_SYNTAX_ERROR;
 880         }
 881
 882         unsigned num;
 883         COMMAND_PARSE_NUMBER(uint, args[1], num);
 884         nand_device_t *device = get_nand_device_by_num(num);
 885         if (!device)
 886         {
 887                 command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
 888                 return ERROR_OK;
 889         }
 890
 891         lpc3180_info = device->controller_priv;
 892
 893         if (argc == 2)
 894         {
 895                 if (strcmp(args[1], "mlc") == 0)
 896                 {
 897                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 898                 }
 899                 else if (strcmp(args[1], "slc") == 0)
 900                 {
 901                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
 902                 }
 903                 else
 904                 {
 905                         return ERROR_COMMAND_SYNTAX_ERROR;
 906                 }
 907         }
 908
 909         command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
 910
 911         return ERROR_OK;
 912 }