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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "lpc3180_nand_controller.h"
  25 #include "nand.h"
  26
  27 static int lpc3180_reset(struct nand_device_s *nand);
  28 static int lpc3180_controller_ready(struct nand_device_s *nand, int timeout);
  29
  30 /* nand device lpc3180 <target#> <oscillator_frequency>
  31  */
  32 static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *nand)
  33 {
  34         if (argc < 3)
  35         {
  36                 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
  37                 return ERROR_FLASH_BANK_INVALID;
  38         }
  39
  40         target_t *target = get_target(args[1]);
  41         if (NULL == target)
  42         {
  43                 LOG_ERROR("target '%s' not defined", args[1]);
  44                 return ERROR_NAND_DEVICE_INVALID;
  45         }
  46
  47         uint32_t osc_freq;
  48         COMMAND_PARSE_NUMBER(u32, args[2], osc_freq);
  49
  50         lpc3180_nand_controller_t *lpc3180_info;
  51         lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
  52         nand->controller_priv = lpc3180_info;
  53
  54         lpc3180_info->target = target;
  55         lpc3180_info->osc_freq = osc_freq;
  56
  57         if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
  58         {
  59                 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
  60         }
  61         lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
  62         lpc3180_info->sw_write_protection = 0;
  63         lpc3180_info->sw_wp_lower_bound = 0x0;
  64         lpc3180_info->sw_wp_upper_bound = 0x0;
  65
  66         return ERROR_OK;
  67 }
  68
  69 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
  70 {
  71         int bypass = (pll_ctrl & 0x8000) >> 15;
  72         int direct = (pll_ctrl & 0x4000) >> 14;
  73         int feedback = (pll_ctrl & 0x2000) >> 13;
  74         int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
  75         int n = ((pll_ctrl & 0x0600) >> 9) + 1;
  76         int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
  77         int lock = (pll_ctrl & 0x1);
  78
  79         if (!lock)
  80                 LOG_WARNING("PLL is not locked");
  81
  82         if (!bypass && direct)  /* direct mode */
  83                 return (m * fclkin) / n;
  84
  85         if (bypass && !direct)  /* bypass mode */
  86                 return fclkin / (2 * p);
  87
  88         if (bypass & direct)    /* direct bypass mode */
  89                 return fclkin;
  90
  91         if (feedback)                   /* integer mode */
  92                 return m * (fclkin / n);
  93         else                                    /* non-integer mode */
  94                 return (m / (2 * p)) * (fclkin / n);
  95 }
  96
  97 static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
  98 {
  99         target_t *target = lpc3180_info->target;
 100         uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
 101         int sysclk;
 102         int hclk;
 103         int hclk_pll;
 104         float cycle;
 105
 106         /* calculate timings */
 107
 108         /* determine current SYSCLK (13'MHz or main oscillator) */
 109         target_read_u32(target, 0x40004050, &sysclk_ctrl);
 110
 111         if ((sysclk_ctrl & 1) == 0)
 112                 sysclk = lpc3180_info->osc_freq;
 113         else
 114                 sysclk = 13000;
 115
 116         /* determine selected HCLK source */
 117         target_read_u32(target, 0x40004044, &pwr_ctrl);
 118
 119         if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
 120         {
 121                 hclk = sysclk;
 122         }
 123         else
 124         {
 125                 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
 126                 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
 127
 128                 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
 129
 130                 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
 131                 {
 132                         hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
 133                 }
 134                 else /* HCLK uses HCLK_PLL */
 135                 {
 136                         hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
 137                 }
 138         }
 139
 140         LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
 141
 142         cycle = (1.0 / hclk) * 1000000.0;
 143
 144         return cycle;
 145 }
 146
 147 static int lpc3180_init(struct nand_device_s *nand)
 148 {
 149         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 150         target_t *target = lpc3180_info->target;
 151         int bus_width = nand->bus_width ? : 8;
 152         int address_cycles = nand->address_cycles ? : 3;
 153         int page_size = nand->page_size ? : 512;
 154
 155         if (target->state != TARGET_HALTED)
 156         {
 157                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 158                 return ERROR_NAND_OPERATION_FAILED;
 159         }
 160
 161         /* sanitize arguments */
 162         if ((bus_width != 8) && (bus_width != 16))
 163         {
 164                 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
 165                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 166         }
 167
 168         /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
 169          * would support 16 bit, too, so we just warn about this for now
 170          */
 171         if (bus_width == 16)
 172         {
 173                 LOG_WARNING("LPC3180 only supports 8 bit bus width");
 174         }
 175
 176         /* inform calling code about selected bus width */
 177         nand->bus_width = bus_width;
 178
 179         if ((address_cycles != 3) && (address_cycles != 4))
 180         {
 181                 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
 182                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 183         }
 184
 185         if ((page_size != 512) && (page_size != 2048))
 186         {
 187                 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
 188                 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 189         }
 190
 191         /* select MLC controller if none is currently selected */
 192         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 193         {
 194                 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
 195                 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 196         }
 197
 198         if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 199         {
 200                 uint32_t mlc_icr_value = 0x0;
 201                 float cycle;
 202                 int twp, twh, trp, treh, trhz, trbwb, tcea;
 203
 204                 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
 205                 target_write_u32(target, 0x400040c8, 0x22);
 206
 207                 /* MLC_CEH = 0x0 (Force nCE assert) */
 208                 target_write_u32(target, 0x200b804c, 0x0);
 209
 210                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 211                 target_write_u32(target, 0x200b8044, 0xa25e);
 212
 213                 /* MLC_ICR = configuration */
 214                 if (lpc3180_info->sw_write_protection)
 215                         mlc_icr_value |= 0x8;
 216                 if (page_size == 2048)
 217                         mlc_icr_value |= 0x4;
 218                 if (address_cycles == 4)
 219                         mlc_icr_value |= 0x2;
 220                 if (bus_width == 16)
 221                         mlc_icr_value |= 0x1;
 222                 target_write_u32(target, 0x200b8030, mlc_icr_value);
 223
 224                 /* calculate NAND controller timings */
 225                 cycle = lpc3180_cycle_time(lpc3180_info);
 226
 227                 twp = ((40 / cycle) + 1);
 228                 twh = ((20 / cycle) + 1);
 229                 trp = ((30 / cycle) + 1);
 230                 treh = ((15 / cycle) + 1);
 231                 trhz = ((30 / cycle) + 1);
 232                 trbwb = ((100 / cycle) + 1);
 233                 tcea = ((45 / cycle) + 1);
 234
 235                 /* MLC_LOCK = 0xa25e (unlock protected registers) */
 236                 target_write_u32(target, 0x200b8044, 0xa25e);
 237
 238                 /* MLC_TIME_REG */
 239                 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
 240                         ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
 241                         ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
 242
 243                 lpc3180_reset(nand);
 244         }
 245         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 246         {
 247                 float cycle;
 248                 int r_setup, r_hold, r_width, r_rdy;
 249                 int w_setup, w_hold, w_width, w_rdy;
 250
 251                 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 252                 target_write_u32(target, 0x400040c8, 0x05);
 253
 254                 /* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
 255                 target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
 256
 257                 /* calculate NAND controller timings */
 258                 cycle = lpc3180_cycle_time(lpc3180_info);
 259
 260                 r_setup = w_setup = 0;
 261                 r_hold = w_hold = 10 / cycle;
 262                 r_width = 30 / cycle;
 263                 w_width = 40 / cycle;
 264                 r_rdy = w_rdy = 100 / cycle;
 265
 266                 /* SLC_TAC: SLC timing arcs register */
 267                 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
 268                         ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) |  ((w_setup & 0xf) << 16) |
 269                         ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
 270
 271                 lpc3180_reset(nand);
 272         }
 273
 274         return ERROR_OK;
 275 }
 276
 277 static int lpc3180_reset(struct nand_device_s *nand)
 278 {
 279         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 280         target_t *target = lpc3180_info->target;
 281
 282         if (target->state != TARGET_HALTED)
 283         {
 284                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 285                 return ERROR_NAND_OPERATION_FAILED;
 286         }
 287
 288         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 289         {
 290                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 291                 return ERROR_NAND_OPERATION_FAILED;
 292         }
 293         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 294         {
 295                 /* MLC_CMD = 0xff (reset controller and NAND device) */
 296                 target_write_u32(target, 0x200b8000, 0xff);
 297
 298                 if (!lpc3180_controller_ready(nand, 100))
 299                 {
 300                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 301                         return ERROR_NAND_OPERATION_TIMEOUT;
 302                 }
 303         }
 304         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 305         {
 306                 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
 307                 target_write_u32(target, 0x20020010, 0x6);
 308
 309                 if (!lpc3180_controller_ready(nand, 100))
 310                 {
 311                         LOG_ERROR("LPC3180 NAND controller timed out after reset");
 312                         return ERROR_NAND_OPERATION_TIMEOUT;
 313                 }
 314         }
 315
 316         return ERROR_OK;
 317 }
 318
 319 static int lpc3180_command(struct nand_device_s *nand, uint8_t command)
 320 {
 321         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 322         target_t *target = lpc3180_info->target;
 323
 324         if (target->state != TARGET_HALTED)
 325         {
 326                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 327                 return ERROR_NAND_OPERATION_FAILED;
 328         }
 329
 330         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 331         {
 332                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 333                 return ERROR_NAND_OPERATION_FAILED;
 334         }
 335         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 336         {
 337                 /* MLC_CMD = command */
 338                 target_write_u32(target, 0x200b8000, command);
 339         }
 340         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 341         {
 342                 /* SLC_CMD = command */
 343                 target_write_u32(target, 0x20020008, command);
 344         }
 345
 346         return ERROR_OK;
 347 }
 348
 349 static int lpc3180_address(struct nand_device_s *nand, uint8_t address)
 350 {
 351         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 352         target_t *target = lpc3180_info->target;
 353
 354         if (target->state != TARGET_HALTED)
 355         {
 356                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 357                 return ERROR_NAND_OPERATION_FAILED;
 358         }
 359
 360         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 361         {
 362                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 363                 return ERROR_NAND_OPERATION_FAILED;
 364         }
 365         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 366         {
 367                 /* MLC_ADDR = address */
 368                 target_write_u32(target, 0x200b8004, address);
 369         }
 370         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 371         {
 372                 /* SLC_ADDR = address */
 373                 target_write_u32(target, 0x20020004, address);
 374         }
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int lpc3180_write_data(struct nand_device_s *nand, uint16_t data)
 380 {
 381         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 382         target_t *target = lpc3180_info->target;
 383
 384         if (target->state != TARGET_HALTED)
 385         {
 386                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 387                 return ERROR_NAND_OPERATION_FAILED;
 388         }
 389
 390         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 391         {
 392                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 393                 return ERROR_NAND_OPERATION_FAILED;
 394         }
 395         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 396         {
 397                 /* MLC_DATA = data */
 398                 target_write_u32(target, 0x200b0000, data);
 399         }
 400         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 401         {
 402                 /* SLC_DATA = data */
 403                 target_write_u32(target, 0x20020000, data);
 404         }
 405
 406         return ERROR_OK;
 407 }
 408
 409 static int lpc3180_read_data(struct nand_device_s *nand, void *data)
 410 {
 411         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 412         target_t *target = lpc3180_info->target;
 413
 414         if (target->state != TARGET_HALTED)
 415         {
 416                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 417                 return ERROR_NAND_OPERATION_FAILED;
 418         }
 419
 420         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 421         {
 422                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 423                 return ERROR_NAND_OPERATION_FAILED;
 424         }
 425         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 426         {
 427                 /* data = MLC_DATA, use sized access */
 428                 if (nand->bus_width == 8)
 429                 {
 430                         uint8_t *data8 = data;
 431                         target_read_u8(target, 0x200b0000, data8);
 432                 }
 433                 else if (nand->bus_width == 16)
 434                 {
 435                         uint16_t *data16 = data;
 436                         target_read_u16(target, 0x200b0000, data16);
 437                 }
 438                 else
 439                 {
 440                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 441                         return ERROR_NAND_OPERATION_FAILED;
 442                 }
 443         }
 444         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 445         {
 446                 uint32_t data32;
 447
 448                 /* data = SLC_DATA, must use 32-bit access */
 449                 target_read_u32(target, 0x20020000, &data32);
 450
 451                 if (nand->bus_width == 8)
 452                 {
 453                         uint8_t *data8 = data;
 454                         *data8 = data32 & 0xff;
 455                 }
 456                 else if (nand->bus_width == 16)
 457                 {
 458                         uint16_t *data16 = data;
 459                         *data16 = data32 & 0xffff;
 460                 }
 461                 else
 462                 {
 463                         LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
 464                         return ERROR_NAND_OPERATION_FAILED;
 465                 }
 466         }
 467
 468         return ERROR_OK;
 469 }
 470
 471 static int lpc3180_write_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 472 {
 473         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 474         target_t *target = lpc3180_info->target;
 475         int retval;
 476         uint8_t status;
 477
 478         if (target->state != TARGET_HALTED)
 479         {
 480                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 481                 return ERROR_NAND_OPERATION_FAILED;
 482         }
 483
 484         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 485         {
 486                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 487                 return ERROR_NAND_OPERATION_FAILED;
 488         }
 489         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 490         {
 491                 uint8_t *page_buffer;
 492                 uint8_t *oob_buffer;
 493                 int quarter, num_quarters;
 494
 495                 if (!data && oob)
 496                 {
 497                         LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
 498                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 499                 }
 500
 501                 if (oob && (oob_size > 6))
 502                 {
 503                         LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
 504                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 505                 }
 506
 507                 if (data_size > (uint32_t)nand->page_size)
 508                 {
 509                         LOG_ERROR("data size exceeds page size");
 510                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 511                 }
 512
 513                 /* MLC_CMD = sequential input */
 514                 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
 515
 516                 page_buffer = malloc(512);
 517                 oob_buffer = malloc(6);
 518
 519                 if (nand->page_size == 512)
 520                 {
 521                         /* MLC_ADDR = 0x0 (one column cycle) */
 522                         target_write_u32(target, 0x200b8004, 0x0);
 523
 524                         /* MLC_ADDR = row */
 525                         target_write_u32(target, 0x200b8004, page & 0xff);
 526                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 527
 528                         if (nand->address_cycles == 4)
 529                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 530                 }
 531                 else
 532                 {
 533                         /* MLC_ADDR = 0x0 (two column cycles) */
 534                         target_write_u32(target, 0x200b8004, 0x0);
 535                         target_write_u32(target, 0x200b8004, 0x0);
 536
 537                         /* MLC_ADDR = row */
 538                         target_write_u32(target, 0x200b8004, page & 0xff);
 539                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 540                 }
 541
 542                 /* when using the MLC controller, we have to treat a large page device
 543                  * as being made out of four quarters, each the size of a small page device
 544                  */
 545                 num_quarters = (nand->page_size == 2048) ? 4 : 1;
 546
 547                 for (quarter = 0; quarter < num_quarters; quarter++)
 548                 {
 549                         int thisrun_data_size = (data_size > 512) ? 512 : data_size;
 550                         int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
 551
 552                         memset(page_buffer, 0xff, 512);
 553                         if (data)
 554                         {
 555                                 memcpy(page_buffer, data, thisrun_data_size);
 556                                 data_size -= thisrun_data_size;
 557                                 data += thisrun_data_size;
 558                         }
 559
 560                         memset(oob_buffer, 0xff, (nand->page_size == 512) ? 6 : 24);
 561                         if (oob)
 562                         {
 563                                 memcpy(page_buffer, oob, thisrun_oob_size);
 564                                 oob_size -= thisrun_oob_size;
 565                                 oob += thisrun_oob_size;
 566                         }
 567
 568                         /* write MLC_ECC_ENC_REG to start encode cycle */
 569                         target_write_u32(target, 0x200b8008, 0x0);
 570
 571                         target_write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
 572                         target_write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
 573
 574                         /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
 575                         target_write_u32(target, 0x200b8010, 0x0);
 576
 577                         if (!lpc3180_controller_ready(nand, 1000))
 578                         {
 579                                 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
 580                                 return ERROR_NAND_OPERATION_FAILED;
 581                         }
 582                 }
 583
 584                 /* MLC_CMD = auto program command */
 585                 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
 586
 587                 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
 588                 {
 589                         LOG_ERROR("couldn't read status");
 590                         return ERROR_NAND_OPERATION_FAILED;
 591                 }
 592
 593                 if (status & NAND_STATUS_FAIL)
 594                 {
 595                         LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
 596                         return ERROR_NAND_OPERATION_FAILED;
 597                 }
 598
 599                 free(page_buffer);
 600                 free(oob_buffer);
 601         }
 602         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 603         {
 604                 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
 605         }
 606
 607         return ERROR_OK;
 608 }
 609
 610 static int lpc3180_read_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
 611 {
 612         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 613         target_t *target = lpc3180_info->target;
 614
 615         if (target->state != TARGET_HALTED)
 616         {
 617                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 618                 return ERROR_NAND_OPERATION_FAILED;
 619         }
 620
 621         if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
 622         {
 623                 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
 624                 return ERROR_NAND_OPERATION_FAILED;
 625         }
 626         else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 627         {
 628                 uint8_t *page_buffer;
 629                 uint8_t *oob_buffer;
 630                 uint32_t page_bytes_done = 0;
 631                 uint32_t oob_bytes_done = 0;
 632                 uint32_t mlc_isr;
 633
 634 #if 0
 635                 if (oob && (oob_size > 6))
 636                 {
 637                         LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
 638                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 639                 }
 640 #endif
 641
 642                 if (data_size > (uint32_t)nand->page_size)
 643                 {
 644                         LOG_ERROR("data size exceeds page size");
 645                         return ERROR_NAND_OPERATION_NOT_SUPPORTED;
 646                 }
 647
 648                 if (nand->page_size == 2048)
 649                 {
 650                         page_buffer = malloc(2048);
 651                         oob_buffer = malloc(64);
 652                 }
 653                 else
 654                 {
 655                         page_buffer = malloc(512);
 656                         oob_buffer = malloc(16);
 657                 }
 658
 659                 if (!data && oob)
 660                 {
 661                         /* MLC_CMD = Read OOB
 662                          * we can use the READOOB command on both small and large page devices,
 663                          * as the controller translates the 0x50 command to a 0x0 with appropriate
 664                          * positioning of the serial buffer read pointer
 665                          */
 666                         target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
 667                 }
 668                 else
 669                 {
 670                         /* MLC_CMD = Read0 */
 671                         target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
 672                 }
 673
 674                 if (nand->page_size == 512)
 675                 {
 676                         /* small page device */
 677                         /* MLC_ADDR = 0x0 (one column cycle) */
 678                         target_write_u32(target, 0x200b8004, 0x0);
 679
 680                         /* MLC_ADDR = row */
 681                         target_write_u32(target, 0x200b8004, page & 0xff);
 682                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 683
 684                         if (nand->address_cycles == 4)
 685                                 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
 686                 }
 687                 else
 688                 {
 689                         /* large page device */
 690                         /* MLC_ADDR = 0x0 (two column cycles) */
 691                         target_write_u32(target, 0x200b8004, 0x0);
 692                         target_write_u32(target, 0x200b8004, 0x0);
 693
 694                         /* MLC_ADDR = row */
 695                         target_write_u32(target, 0x200b8004, page & 0xff);
 696                         target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
 697
 698                         /* MLC_CMD = Read Start */
 699                         target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
 700                 }
 701
 702                 while (page_bytes_done < (uint32_t)nand->page_size)
 703                 {
 704                         /* MLC_ECC_AUTO_DEC_REG = dummy */
 705                         target_write_u32(target, 0x200b8014, 0xaa55aa55);
 706
 707                         if (!lpc3180_controller_ready(nand, 1000))
 708                         {
 709                                 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
 710                                 return ERROR_NAND_OPERATION_FAILED;
 711                         }
 712
 713                         target_read_u32(target, 0x200b8048, &mlc_isr);
 714
 715                         if (mlc_isr & 0x8)
 716                         {
 717                                 if (mlc_isr & 0x40)
 718                                 {
 719                                         LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr);
 720                                         return ERROR_NAND_OPERATION_FAILED;
 721                                 }
 722
 723                                 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr & 0x30) >> 4) + 1)));
 724                         }
 725
 726                         if (data)
 727                         {
 728                                 target_read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
 729                         }
 730
 731                         if (oob)
 732                         {
 733                                 target_read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
 734                         }
 735
 736                         page_bytes_done += 512;
 737                         oob_bytes_done += 16;
 738                 }
 739
 740                 if (data)
 741                         memcpy(data, page_buffer, data_size);
 742
 743                 if (oob)
 744                         memcpy(oob, oob_buffer, oob_size);
 745
 746                 free(page_buffer);
 747                 free(oob_buffer);
 748         }
 749         else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 750         {
 751                 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
 752         }
 753
 754         return ERROR_OK;
 755 }
 756
 757 static int lpc3180_controller_ready(struct nand_device_s *nand, int timeout)
 758 {
 759         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 760         target_t *target = lpc3180_info->target;
 761         uint8_t status = 0x0;
 762
 763         if (target->state != TARGET_HALTED)
 764         {
 765                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 766                 return ERROR_NAND_OPERATION_FAILED;
 767         }
 768
 769         do
 770         {
 771                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 772                 {
 773                         /* Read MLC_ISR, wait for controller to become ready */
 774                         target_read_u8(target, 0x200b8048, &status);
 775
 776                         if (status & 2)
 777                                 return 1;
 778                 }
 779                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 780                 {
 781                         /* we pretend that the SLC controller is always ready */
 782                         return 1;
 783                 }
 784
 785                 alive_sleep(1);
 786         } while (timeout-- > 0);
 787
 788         return 0;
 789 }
 790
 791 static int lpc3180_nand_ready(struct nand_device_s *nand, int timeout)
 792 {
 793         lpc3180_nand_controller_t *lpc3180_info = nand->controller_priv;
 794         target_t *target = lpc3180_info->target;
 795
 796         if (target->state != TARGET_HALTED)
 797         {
 798                 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
 799                 return ERROR_NAND_OPERATION_FAILED;
 800         }
 801
 802         do
 803         {
 804                 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
 805                 {
 806                         uint8_t status = 0x0;
 807
 808                         /* Read MLC_ISR, wait for NAND flash device to become ready */
 809                         target_read_u8(target, 0x200b8048, &status);
 810
 811                         if (status & 1)
 812                                 return 1;
 813                 }
 814                 else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
 815                 {
 816                         uint32_t status = 0x0;
 817
 818                         /* Read SLC_STAT and check READY bit */
 819                         target_read_u32(target, 0x20020018, &status);
 820
 821                         if (status & 1)
 822                                 return 1;
 823                 }
 824
 825                 alive_sleep(1);
 826         } while (timeout-- > 0);
 827
 828         return 0;
 829 }
 830
 831 COMMAND_HANDLER(handle_lpc3180_select_command)
 832 {
 833         lpc3180_nand_controller_t *lpc3180_info = NULL;
 834         char *selected[] =
 835         {
 836                 "no", "mlc", "slc"
 837         };
 838
 839         if ((argc < 1) || (argc > 2))
 840         {
 841                 return ERROR_COMMAND_SYNTAX_ERROR;
 842         }
 843
 844         unsigned num;
 845         COMMAND_PARSE_NUMBER(uint, args[1], num);
 846         nand_device_t *nand = get_nand_device_by_num(num);
 847         if (!nand)
 848         {
 849                 command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
 850                 return ERROR_OK;
 851         }
 852
 853         lpc3180_info = nand->controller_priv;
 854
 855         if (argc == 2)
 856         {
 857                 if (strcmp(args[1], "mlc") == 0)
 858                 {
 859                         lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
 860                 }
 861                 else if (strcmp(args[1], "slc") == 0)
 862                 {
 863                         lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
 864                 }
 865                 else
 866                 {
 867                         return ERROR_COMMAND_SYNTAX_ERROR;
 868                 }
 869         }
 870
 871         command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
 872
 873         return ERROR_OK;
 874 }
 875
 876 static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
 877 {
 878         command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
 879
 880         register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
 881
 882         return ERROR_OK;
 883 }
 884
 885 nand_flash_controller_t lpc3180_nand_controller = {
 886                 .name = "lpc3180",
 887                 .nand_device_command = lpc3180_nand_device_command,
 888                 .register_commands = lpc3180_register_commands,
 889                 .init = lpc3180_init,
 890                 .reset = lpc3180_reset,
 891                 .command = lpc3180_command,
 892                 .address = lpc3180_address,
 893                 .write_data = lpc3180_write_data,
 894                 .read_data = lpc3180_read_data,
 895                 .write_page = lpc3180_write_page,
 896                 .read_page = lpc3180_read_page,
 897                 .controller_ready = lpc3180_controller_ready,
 898                 .nand_ready = lpc3180_nand_ready,
 899         };