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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28 #include "armv4_5.h"
  29 #include "binarybuffer.h"
  30
  31
  32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
  33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
  35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  36 static int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
  37 static int cfi_probe(struct flash_bank_s *bank);
  38 static int cfi_auto_probe(struct flash_bank_s *bank);
  39 static int cfi_protect_check(struct flash_bank_s *bank);
  40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  41
  42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 #define CFI_MAX_BUS_WIDTH       4
  45 #define CFI_MAX_CHIP_WIDTH      4
  46
  47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  48 #define CFI_MAX_INTEL_CODESIZE 256
  49
  50 flash_driver_t cfi_flash =
  51 {
  52         .name = "cfi",
  53         .register_commands = cfi_register_commands,
  54         .flash_bank_command = cfi_flash_bank_command,
  55         .erase = cfi_erase,
  56         .protect = cfi_protect,
  57         .write = cfi_write,
  58         .probe = cfi_probe,
  59         .auto_probe = cfi_auto_probe,
  60         .erase_check = default_flash_blank_check,
  61         .protect_check = cfi_protect_check,
  62         .info = cfi_info
  63 };
  64
  65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
  66 {
  67         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  68         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  69 };
  70
  71 /* CFI fixups foward declarations */
  72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  75
  76 /* fixup after reading cmdset 0002 primary query table */
  77 static const cfi_fixup_t cfi_0002_fixups[] = {
  78         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  79         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  80         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  81         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  82         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  83         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  84         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  85         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  86         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  87         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  88         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  89         {0, 0, NULL, NULL}
  90 };
  91
  92 /* fixup after reading cmdset 0001 primary query table */
  93 static const cfi_fixup_t cfi_0001_fixups[] = {
  94         {0, 0, NULL, NULL}
  95 };
  96
  97 static void cfi_fixup(flash_bank_t *bank, const cfi_fixup_t *fixups)
  98 {
  99         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 100         const cfi_fixup_t *f;
 101
 102         for (f = fixups; f->fixup; f++)
 103         {
 104                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 105                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 106                 {
 107                         f->fixup(bank, f->param);
 108                 }
 109         }
 110 }
 111
 112 /* inline uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset) */
 113 static __inline__ uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset)
 114 {
 115         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 116
 117         if (cfi_info->x16_as_x8) offset *= 2;
 118
 119         /* while the sector list isn't built, only accesses to sector 0 work */
 120         if (sector == 0)
 121                 return bank->base + offset * bank->bus_width;
 122         else
 123         {
 124                 if (!bank->sectors)
 125                 {
 126                         LOG_ERROR("BUG: sector list not yet built");
 127                         exit(-1);
 128                 }
 129                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 130         }
 131
 132 }
 133
 134 static void cfi_command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
 135 {
 136         int i;
 137
 138         /* clear whole buffer, to ensure bits that exceed the bus_width
 139          * are set to zero
 140          */
 141         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 142                 cmd_buf[i] = 0;
 143
 144         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 145         {
 146                 for (i = bank->bus_width; i > 0; i--)
 147                 {
 148                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 149                 }
 150         }
 151         else
 152         {
 153                 for (i = 1; i <= bank->bus_width; i++)
 154                 {
 155                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 156                 }
 157         }
 158 }
 159
 160 /* read unsigned 8-bit value from the bank
 161  * flash banks are expected to be made of similar chips
 162  * the query result should be the same for all
 163  */
 164 static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
 165 {
 166         target_t *target = bank->target;
 167         uint8_t data[CFI_MAX_BUS_WIDTH];
 168
 169         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 170
 171         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 172                 return data[0];
 173         else
 174                 return data[bank->bus_width - 1];
 175 }
 176
 177 /* read unsigned 8-bit value from the bank
 178  * in case of a bank made of multiple chips,
 179  * the individual values are ORed
 180  */
 181 static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
 182 {
 183         target_t *target = bank->target;
 184         uint8_t data[CFI_MAX_BUS_WIDTH];
 185         int i;
 186
 187         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 188
 189         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 190         {
 191                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 192                         data[0] |= data[i];
 193
 194                 return data[0];
 195         }
 196         else
 197         {
 198                 uint8_t value = 0;
 199                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 200                         value |= data[bank->bus_width - 1 - i];
 201
 202                 return value;
 203         }
 204 }
 205
 206 static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
 207 {
 208         target_t *target = bank->target;
 209         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 210         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 211
 212         if (cfi_info->x16_as_x8)
 213         {
 214                 uint8_t i;
 215                 for (i = 0;i < 2;i++)
 216                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 217                                 &data[i*bank->bus_width]);
 218         }
 219         else
 220                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 221
 222         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 223                 return data[0] | data[bank->bus_width] << 8;
 224         else
 225                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 226 }
 227
 228 static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
 229 {
 230         target_t *target = bank->target;
 231         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 232         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 233
 234         if (cfi_info->x16_as_x8)
 235         {
 236                 uint8_t i;
 237                 for (i = 0;i < 4;i++)
 238                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 239                                 &data[i*bank->bus_width]);
 240         }
 241         else
 242                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 243
 244         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 245                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 246         else
 247                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 248                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 249 }
 250
 251 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 252 {
 253         target_t *target = bank->target;
 254         uint8_t command[8];
 255
 256         if (target->state != TARGET_HALTED)
 257         {
 258                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 259                 exit(-1);
 260         }
 261
 262         cfi_command(bank, 0x50, command);
 263         target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 264 }
 265
 266 uint8_t cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 267 {
 268         uint8_t status;
 269
 270         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 271         {
 272                 LOG_DEBUG("status: 0x%x", status);
 273                 alive_sleep(1);
 274         }
 275
 276         /* mask out bit 0 (reserved) */
 277         status = status & 0xfe;
 278
 279         LOG_DEBUG("status: 0x%x", status);
 280
 281         if ((status & 0x80) != 0x80)
 282         {
 283                 LOG_ERROR("timeout while waiting for WSM to become ready");
 284         }
 285         else if (status != 0x80)
 286         {
 287                 LOG_ERROR("status register: 0x%x", status);
 288                 if (status & 0x2)
 289                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 290                 if (status & 0x4)
 291                         LOG_ERROR("Program suspended");
 292                 if (status & 0x8)
 293                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 294                 if (status & 0x10)
 295                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 296                 if (status & 0x20)
 297                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 298                 if (status & 0x40)
 299                         LOG_ERROR("Block Erase Suspended");
 300
 301                 cfi_intel_clear_status_register(bank);
 302         }
 303
 304         return status;
 305 }
 306
 307 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 308 {
 309         uint8_t status, oldstatus;
 310         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 311
 312         oldstatus = cfi_get_u8(bank, 0, 0x0);
 313
 314         do {
 315                 status = cfi_get_u8(bank, 0, 0x0);
 316                 if ((status ^ oldstatus) & 0x40) {
 317                         if (status & cfi_info->status_poll_mask & 0x20) {
 318                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 319                                 status = cfi_get_u8(bank, 0, 0x0);
 320                                 if ((status ^ oldstatus) & 0x40) {
 321                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 322                                         return(ERROR_FLASH_OPERATION_FAILED);
 323                                 } else {
 324                                         LOG_DEBUG("status: 0x%x", status);
 325                                         return(ERROR_OK);
 326                                 }
 327                         }
 328                 } else { /* no toggle: finished, OK */
 329                         LOG_DEBUG("status: 0x%x", status);
 330                         return(ERROR_OK);
 331                 }
 332
 333                 oldstatus = status;
 334                 alive_sleep(1);
 335         } while (timeout-- > 0);
 336
 337         LOG_ERROR("timeout, status: 0x%x", status);
 338
 339         return(ERROR_FLASH_BUSY);
 340 }
 341
 342 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 343 {
 344         int retval;
 345         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 346         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 347         target_t *target = bank->target;
 348         uint8_t command[8];
 349
 350         cfi_info->pri_ext = pri_ext;
 351
 352         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 353         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 354         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 355
 356         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 357         {
 358                 cfi_command(bank, 0xf0, command);
 359                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 360                 {
 361                         return retval;
 362                 }
 363                 cfi_command(bank, 0xff, command);
 364                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 365                 {
 366                         return retval;
 367                 }
 368                 LOG_ERROR("Could not read bank flash bank information");
 369                 return ERROR_FLASH_BANK_INVALID;
 370         }
 371
 372         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 373         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 374
 375         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 376
 377         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 378         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 379         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 380
 381         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 382                   pri_ext->feature_support,
 383                   pri_ext->suspend_cmd_support,
 384                   pri_ext->blk_status_reg_mask);
 385
 386         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 387         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 388
 389         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 390                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 391                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 392
 393         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 394         if (pri_ext->num_protection_fields != 1)
 395         {
 396                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 397         }
 398
 399         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 400         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 401         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 402
 403         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 404
 405         return ERROR_OK;
 406 }
 407
 408 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 409 {
 410         int retval;
 411         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 412         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 413         target_t *target = bank->target;
 414         uint8_t command[8];
 415
 416         cfi_info->pri_ext = pri_ext;
 417
 418         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 419         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 420         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 421
 422         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 423         {
 424                 cfi_command(bank, 0xf0, command);
 425                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 426                 {
 427                         return retval;
 428                 }
 429                 LOG_ERROR("Could not read spansion bank information");
 430                 return ERROR_FLASH_BANK_INVALID;
 431         }
 432
 433         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 434         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 435
 436         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 437
 438         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 439         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 440         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 441         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 442         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 443         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 444         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 445         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 446         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 447         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 448         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 449
 450         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 451               pri_ext->EraseSuspend, pri_ext->BlkProt);
 452
 453         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 454               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 455
 456         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 457
 458
 459         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 460                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 461                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 462
 463         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 464
 465         /* default values for implementation specific workarounds */
 466         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 467         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 468         pri_ext->_reversed_geometry = 0;
 469
 470         return ERROR_OK;
 471 }
 472
 473 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 474 {
 475         int retval;
 476         cfi_atmel_pri_ext_t atmel_pri_ext;
 477         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 478         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 479         target_t *target = bank->target;
 480         uint8_t command[8];
 481
 482         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 483          * but a different primary extended query table.
 484          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 485          */
 486
 487         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 488
 489         cfi_info->pri_ext = pri_ext;
 490
 491         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 492         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 493         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 494
 495         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 496         {
 497                 cfi_command(bank, 0xf0, command);
 498                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 499                 {
 500                         return retval;
 501                 }
 502                 LOG_ERROR("Could not read atmel bank information");
 503                 return ERROR_FLASH_BANK_INVALID;
 504         }
 505
 506         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 507         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 508         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 509
 510         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 511         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 512
 513         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 514
 515         pri_ext->major_version = atmel_pri_ext.major_version;
 516         pri_ext->minor_version = atmel_pri_ext.minor_version;
 517
 518         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 519         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 520         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 521         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 522
 523         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 524                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 525
 526         if (atmel_pri_ext.features & 0x02)
 527                 pri_ext->EraseSuspend = 2;
 528
 529         if (atmel_pri_ext.bottom_boot)
 530                 pri_ext->TopBottom = 2;
 531         else
 532                 pri_ext->TopBottom = 3;
 533
 534         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 535         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 536
 537         return ERROR_OK;
 538 }
 539
 540 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 541 {
 542         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 543
 544         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 545         {
 546                 return cfi_read_atmel_pri_ext(bank);
 547         }
 548         else
 549         {
 550                 return cfi_read_spansion_pri_ext(bank);
 551         }
 552 }
 553
 554 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 555 {
 556         int printed;
 557         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 558         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 559
 560         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 561         buf += printed;
 562         buf_size -= printed;
 563
 564         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 565                            pri_ext->pri[1], pri_ext->pri[2],
 566                            pri_ext->major_version, pri_ext->minor_version);
 567         buf += printed;
 568         buf_size -= printed;
 569
 570         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 571                            (pri_ext->SiliconRevision) >> 2,
 572                            (pri_ext->SiliconRevision) & 0x03);
 573         buf += printed;
 574         buf_size -= printed;
 575
 576         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 577                            pri_ext->EraseSuspend,
 578                            pri_ext->BlkProt);
 579         buf += printed;
 580         buf_size -= printed;
 581
 582         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 583                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 584                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 585
 586         return ERROR_OK;
 587 }
 588
 589 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 590 {
 591         int printed;
 592         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 593         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 594
 595         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 596         buf += printed;
 597         buf_size -= printed;
 598
 599         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 600         buf += printed;
 601         buf_size -= printed;
 602
 603         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 604         buf += printed;
 605         buf_size -= printed;
 606
 607         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 608                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 609                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 610         buf += printed;
 611         buf_size -= printed;
 612
 613         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 614
 615         return ERROR_OK;
 616 }
 617
 618 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 619 {
 620         /*command_t *cfi_cmd = */
 621         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 622         /*
 623         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 624                                          "print part id of cfi flash bank <num>");
 625         */
 626         return ERROR_OK;
 627 }
 628
 629 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 630  */
 631 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 632 {
 633         cfi_flash_bank_t *cfi_info;
 634         int i;
 635         (void) cmd_ctx;
 636         (void) cmd;
 637
 638         if (argc < 6)
 639         {
 640                 LOG_WARNING("incomplete flash_bank cfi configuration");
 641                 return ERROR_FLASH_BANK_INVALID;
 642         }
 643
 644         uint16_t chip_width, bus_width;
 645         COMMAND_PARSE_NUMBER(u16, args[3], bus_width);
 646         COMMAND_PARSE_NUMBER(u16, args[4], chip_width);
 647
 648         if ((chip_width > CFI_MAX_CHIP_WIDTH)
 649                         || (bus_width > CFI_MAX_BUS_WIDTH))
 650         {
 651                 LOG_ERROR("chip and bus width have to specified in bytes");
 652                 return ERROR_FLASH_BANK_INVALID;
 653         }
 654
 655         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 656         cfi_info->probed = 0;
 657         bank->driver_priv = cfi_info;
 658
 659         cfi_info->write_algorithm = NULL;
 660
 661         cfi_info->x16_as_x8 = 0;
 662         cfi_info->jedec_probe = 0;
 663         cfi_info->not_cfi = 0;
 664
 665         for (i = 6; i < argc; i++)
 666         {
 667                 if (strcmp(args[i], "x16_as_x8") == 0)
 668                 {
 669                         cfi_info->x16_as_x8 = 1;
 670                 }
 671                 else if (strcmp(args[i], "jedec_probe") == 0)
 672                 {
 673                         cfi_info->jedec_probe = 1;
 674                 }
 675         }
 676
 677         cfi_info->write_algorithm = NULL;
 678
 679         /* bank wasn't probed yet */
 680         cfi_info->qry[0] = -1;
 681
 682         return ERROR_OK;
 683 }
 684
 685 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 686 {
 687         int retval;
 688         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 689         target_t *target = bank->target;
 690         uint8_t command[8];
 691         int i;
 692
 693         cfi_intel_clear_status_register(bank);
 694
 695         for (i = first; i <= last; i++)
 696         {
 697                 cfi_command(bank, 0x20, command);
 698                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 699                 {
 700                         return retval;
 701                 }
 702
 703                 cfi_command(bank, 0xd0, command);
 704                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 705                 {
 706                         return retval;
 707                 }
 708
 709                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 710                         bank->sectors[i].is_erased = 1;
 711                 else
 712                 {
 713                         cfi_command(bank, 0xff, command);
 714                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 715                         {
 716                                 return retval;
 717                         }
 718
 719                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 720                         return ERROR_FLASH_OPERATION_FAILED;
 721                 }
 722         }
 723
 724         cfi_command(bank, 0xff, command);
 725         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 726
 727 }
 728
 729 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 730 {
 731         int retval;
 732         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 733         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 734         target_t *target = bank->target;
 735         uint8_t command[8];
 736         int i;
 737
 738         for (i = first; i <= last; i++)
 739         {
 740                 cfi_command(bank, 0xaa, command);
 741                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 742                 {
 743                         return retval;
 744                 }
 745
 746                 cfi_command(bank, 0x55, command);
 747                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 748                 {
 749                         return retval;
 750                 }
 751
 752                 cfi_command(bank, 0x80, command);
 753                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 754                 {
 755                         return retval;
 756                 }
 757
 758                 cfi_command(bank, 0xaa, command);
 759                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 760                 {
 761                         return retval;
 762                 }
 763
 764                 cfi_command(bank, 0x55, command);
 765                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 766                 {
 767                         return retval;
 768                 }
 769
 770                 cfi_command(bank, 0x30, command);
 771                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 772                 {
 773                         return retval;
 774                 }
 775
 776                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 777                         bank->sectors[i].is_erased = 1;
 778                 else
 779                 {
 780                         cfi_command(bank, 0xf0, command);
 781                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 782                         {
 783                                 return retval;
 784                         }
 785
 786                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 787                         return ERROR_FLASH_OPERATION_FAILED;
 788                 }
 789         }
 790
 791         cfi_command(bank, 0xf0, command);
 792         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 793 }
 794
 795 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 796 {
 797         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 798
 799         if (bank->target->state != TARGET_HALTED)
 800         {
 801                 LOG_ERROR("Target not halted");
 802                 return ERROR_TARGET_NOT_HALTED;
 803         }
 804
 805         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 806         {
 807                 return ERROR_FLASH_SECTOR_INVALID;
 808         }
 809
 810         if (cfi_info->qry[0] != 'Q')
 811                 return ERROR_FLASH_BANK_NOT_PROBED;
 812
 813         switch (cfi_info->pri_id)
 814         {
 815                 case 1:
 816                 case 3:
 817                         return cfi_intel_erase(bank, first, last);
 818                         break;
 819                 case 2:
 820                         return cfi_spansion_erase(bank, first, last);
 821                         break;
 822                 default:
 823                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 824                         break;
 825         }
 826
 827         return ERROR_OK;
 828 }
 829
 830 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 831 {
 832         int retval;
 833         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 834         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 835         target_t *target = bank->target;
 836         uint8_t command[8];
 837         int retry = 0;
 838         int i;
 839
 840         /* if the device supports neither legacy lock/unlock (bit 3) nor
 841          * instant individual block locking (bit 5).
 842          */
 843         if (!(pri_ext->feature_support & 0x28))
 844                 return ERROR_FLASH_OPERATION_FAILED;
 845
 846         cfi_intel_clear_status_register(bank);
 847
 848         for (i = first; i <= last; i++)
 849         {
 850                 cfi_command(bank, 0x60, command);
 851                 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 852                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 853                 {
 854                         return retval;
 855                 }
 856                 if (set)
 857                 {
 858                         cfi_command(bank, 0x01, command);
 859                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 860                         if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 861                         {
 862                                 return retval;
 863                         }
 864                         bank->sectors[i].is_protected = 1;
 865                 }
 866                 else
 867                 {
 868                         cfi_command(bank, 0xd0, command);
 869                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 870                         if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 871                         {
 872                                 return retval;
 873                         }
 874                         bank->sectors[i].is_protected = 0;
 875                 }
 876
 877                 /* instant individual block locking doesn't require reading of the status register */
 878                 if (!(pri_ext->feature_support & 0x20))
 879                 {
 880                         /* Clear lock bits operation may take up to 1.4s */
 881                         cfi_intel_wait_status_busy(bank, 1400);
 882                 }
 883                 else
 884                 {
 885                         uint8_t block_status;
 886                         /* read block lock bit, to verify status */
 887                         cfi_command(bank, 0x90, command);
 888                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 889                         {
 890                                 return retval;
 891                         }
 892                         block_status = cfi_get_u8(bank, i, 0x2);
 893
 894                         if ((block_status & 0x1) != set)
 895                         {
 896                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 897                                 cfi_command(bank, 0x70, command);
 898                                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 899                                 {
 900                                         return retval;
 901                                 }
 902                                 cfi_intel_wait_status_busy(bank, 10);
 903
 904                                 if (retry > 10)
 905                                         return ERROR_FLASH_OPERATION_FAILED;
 906                                 else
 907                                 {
 908                                         i--;
 909                                         retry++;
 910                                 }
 911                         }
 912                 }
 913         }
 914
 915         /* if the device doesn't support individual block lock bits set/clear,
 916          * all blocks have been unlocked in parallel, so we set those that should be protected
 917          */
 918         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 919         {
 920                 for (i = 0; i < bank->num_sectors; i++)
 921                 {
 922                         if (bank->sectors[i].is_protected == 1)
 923                         {
 924                                 cfi_intel_clear_status_register(bank);
 925
 926                                 cfi_command(bank, 0x60, command);
 927                                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 928                                 {
 929                                         return retval;
 930                                 }
 931
 932                                 cfi_command(bank, 0x01, command);
 933                                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 934                                 {
 935                                         return retval;
 936                                 }
 937
 938                                 cfi_intel_wait_status_busy(bank, 100);
 939                         }
 940                 }
 941         }
 942
 943         cfi_command(bank, 0xff, command);
 944         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 945 }
 946
 947 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 948 {
 949         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 950
 951         if (bank->target->state != TARGET_HALTED)
 952         {
 953                 LOG_ERROR("Target not halted");
 954                 return ERROR_TARGET_NOT_HALTED;
 955         }
 956
 957         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 958         {
 959                 return ERROR_FLASH_SECTOR_INVALID;
 960         }
 961
 962         if (cfi_info->qry[0] != 'Q')
 963                 return ERROR_FLASH_BANK_NOT_PROBED;
 964
 965         switch (cfi_info->pri_id)
 966         {
 967                 case 1:
 968                 case 3:
 969                         cfi_intel_protect(bank, set, first, last);
 970                         break;
 971                 default:
 972                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 973                         break;
 974         }
 975
 976         return ERROR_OK;
 977 }
 978
 979 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 980 static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
 981 {
 982         /* target_t *target = bank->target; */
 983
 984         int i;
 985
 986         /* NOTE:
 987          * The data to flash must not be changed in endian! We write a bytestrem in
 988          * target byte order already. Only the control and status byte lane of the flash
 989          * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
 990          * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
 991          */
 992
 993 #if 0
 994         if (target->endianness == TARGET_LITTLE_ENDIAN)
 995         {
 996 #endif
 997                 /* shift bytes */
 998                 for (i = 0; i < bank->bus_width - 1; i++)
 999                         word[i] = word[i + 1];
1000                 word[bank->bus_width - 1] = byte;
1001 #if 0
1002         }
1003         else
1004         {
1005                 /* shift bytes */
1006                 for (i = bank->bus_width - 1; i > 0; i--)
1007                         word[i] = word[i - 1];
1008                 word[0] = byte;
1009         }
1010 #endif
1011 }
1012
1013 /* Convert code image to target endian */
1014 /* FIXME create general block conversion fcts in target.c?) */
1015 static void cfi_fix_code_endian(target_t *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1016 {
1017         uint32_t i;
1018         for (i = 0; i< count; i++)
1019         {
1020                 target_buffer_set_u32(target, dest, *src);
1021                 dest += 4;
1022                 src++;
1023         }
1024 }
1025
1026 static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
1027 {
1028         target_t *target = bank->target;
1029
1030         uint8_t buf[CFI_MAX_BUS_WIDTH];
1031         cfi_command(bank, cmd, buf);
1032         switch (bank->bus_width)
1033         {
1034         case 1 :
1035                 return buf[0];
1036                 break;
1037         case 2 :
1038                 return target_buffer_get_u16(target, buf);
1039                 break;
1040         case 4 :
1041                 return target_buffer_get_u32(target, buf);
1042                 break;
1043         default :
1044                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1045                 return 0;
1046         }
1047 }
1048
1049 static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1050 {
1051         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1052         target_t *target = bank->target;
1053         reg_param_t reg_params[7];
1054         armv4_5_algorithm_t armv4_5_info;
1055         working_area_t *source;
1056         uint32_t buffer_size = 32768;
1057         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1058
1059         /* algorithm register usage:
1060          * r0: source address (in RAM)
1061          * r1: target address (in Flash)
1062          * r2: count
1063          * r3: flash write command
1064          * r4: status byte (returned to host)
1065          * r5: busy test pattern
1066          * r6: error test pattern
1067          */
1068
1069         static const uint32_t word_32_code[] = {
1070                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1071                 0xe5813000,   /*                str r3, [r1] */
1072                 0xe5814000,   /*                str r4, [r1] */
1073                 0xe5914000,   /* busy:  ldr r4, [r1] */
1074                 0xe0047005,   /*                and r7, r4, r5 */
1075                 0xe1570005,   /*                cmp r7, r5 */
1076                 0x1afffffb,   /*                bne busy */
1077                 0xe1140006,   /*                tst r4, r6 */
1078                 0x1a000003,   /*                bne done */
1079                 0xe2522001,   /*                subs r2, r2, #1 */
1080                 0x0a000001,   /*                beq done */
1081                 0xe2811004,   /*                add r1, r1 #4 */
1082                 0xeafffff2,   /*                b loop */
1083                 0xeafffffe    /* done:  b -2 */
1084         };
1085
1086         static const uint32_t word_16_code[] = {
1087                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1088                 0xe1c130b0,   /*                strh r3, [r1] */
1089                 0xe1c140b0,   /*                strh r4, [r1] */
1090                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1091                 0xe0047005,   /*                and r7, r4, r5 */
1092                 0xe1570005,   /*                cmp r7, r5 */
1093                 0x1afffffb,   /*                bne busy */
1094                 0xe1140006,   /*                tst r4, r6 */
1095                 0x1a000003,   /*                bne done */
1096                 0xe2522001,   /*                subs r2, r2, #1 */
1097                 0x0a000001,   /*                beq done */
1098                 0xe2811002,   /*                add r1, r1 #2 */
1099                 0xeafffff2,   /*                b loop */
1100                 0xeafffffe    /* done:  b -2 */
1101         };
1102
1103         static const uint32_t word_8_code[] = {
1104                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1105                 0xe5c13000,   /*                strb r3, [r1] */
1106                 0xe5c14000,   /*                strb r4, [r1] */
1107                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1108                 0xe0047005,   /*                and r7, r4, r5 */
1109                 0xe1570005,   /*                cmp r7, r5 */
1110                 0x1afffffb,   /*                bne busy */
1111                 0xe1140006,   /*                tst r4, r6 */
1112                 0x1a000003,   /*                bne done */
1113                 0xe2522001,   /*                subs r2, r2, #1 */
1114                 0x0a000001,   /*                beq done */
1115                 0xe2811001,   /*                add r1, r1 #1 */
1116                 0xeafffff2,   /*                b loop */
1117                 0xeafffffe    /* done:  b -2 */
1118         };
1119         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1120         const uint32_t *target_code_src;
1121         uint32_t target_code_size;
1122         int retval = ERROR_OK;
1123
1124
1125         cfi_intel_clear_status_register(bank);
1126
1127         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1128         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1129         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1130
1131         /* If we are setting up the write_algorith, we need target_code_src */
1132         /* if not we only need target_code_size. */
1133
1134         /* However, we don't want to create multiple code paths, so we */
1135         /* do the unecessary evaluation of target_code_src, which the */
1136         /* compiler will probably nicely optimize away if not needed */
1137
1138         /* prepare algorithm code for target endian */
1139         switch (bank->bus_width)
1140         {
1141         case 1 :
1142                 target_code_src = word_8_code;
1143                 target_code_size = sizeof(word_8_code);
1144                 break;
1145         case 2 :
1146                 target_code_src = word_16_code;
1147                 target_code_size = sizeof(word_16_code);
1148                 break;
1149         case 4 :
1150                 target_code_src = word_32_code;
1151                 target_code_size = sizeof(word_32_code);
1152                 break;
1153         default:
1154                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1155                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1156         }
1157
1158         /* flash write code */
1159         if (!cfi_info->write_algorithm)
1160         {
1161                 if (target_code_size > sizeof(target_code))
1162                 {
1163                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1164                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1165                 }
1166                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1167
1168                 /* Get memory for block write handler */
1169                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1170                 if (retval != ERROR_OK)
1171                 {
1172                         LOG_WARNING("No working area available, can't do block memory writes");
1173                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1174                 };
1175
1176                 /* write algorithm code to working area */
1177                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1178                 if (retval != ERROR_OK)
1179                 {
1180                         LOG_ERROR("Unable to write block write code to target");
1181                         goto cleanup;
1182                 }
1183         }
1184
1185         /* Get a workspace buffer for the data to flash starting with 32k size.
1186            Half size until buffer would be smaller 256 Bytem then fail back */
1187         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1188         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1189         {
1190                 buffer_size /= 2;
1191                 if (buffer_size <= 256)
1192                 {
1193                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1194                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1195                         goto cleanup;
1196                 }
1197         };
1198
1199         /* setup algo registers */
1200         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1201         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1202         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1203         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1204         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1205         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1206         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1207
1208         /* prepare command and status register patterns */
1209         write_command_val = cfi_command_val(bank, 0x40);
1210         busy_pattern_val  = cfi_command_val(bank, 0x80);
1211         error_pattern_val = cfi_command_val(bank, 0x7e);
1212
1213         LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1214
1215         /* Programming main loop */
1216         while (count > 0)
1217         {
1218                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1219                 uint32_t wsm_error;
1220
1221                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1222                 {
1223                         goto cleanup;
1224                 }
1225
1226                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1227                 buf_set_u32(reg_params[1].value, 0, 32, address);
1228                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1229
1230                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1231                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1232                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1233
1234                 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1235
1236                 /* Execute algorithm, assume breakpoint for last instruction */
1237                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1238                         cfi_info->write_algorithm->address,
1239                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1240                         10000, /* 10s should be enough for max. 32k of data */
1241                         &armv4_5_info);
1242
1243                 /* On failure try a fall back to direct word writes */
1244                 if (retval != ERROR_OK)
1245                 {
1246                         cfi_intel_clear_status_register(bank);
1247                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1248                         retval = ERROR_FLASH_OPERATION_FAILED;
1249                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1250                         /* FIXME To allow fall back or recovery, we must save the actual status
1251                            somewhere, so that a higher level code can start recovery. */
1252                         goto cleanup;
1253                 }
1254
1255                 /* Check return value from algo code */
1256                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1257                 if (wsm_error)
1258                 {
1259                         /* read status register (outputs debug inforation) */
1260                         cfi_intel_wait_status_busy(bank, 100);
1261                         cfi_intel_clear_status_register(bank);
1262                         retval = ERROR_FLASH_OPERATION_FAILED;
1263                         goto cleanup;
1264                 }
1265
1266                 buffer += thisrun_count;
1267                 address += thisrun_count;
1268                 count -= thisrun_count;
1269         }
1270
1271         /* free up resources */
1272 cleanup:
1273         if (source)
1274                 target_free_working_area(target, source);
1275
1276         if (cfi_info->write_algorithm)
1277         {
1278                 target_free_working_area(target, cfi_info->write_algorithm);
1279                 cfi_info->write_algorithm = NULL;
1280         }
1281
1282         destroy_reg_param(&reg_params[0]);
1283         destroy_reg_param(&reg_params[1]);
1284         destroy_reg_param(&reg_params[2]);
1285         destroy_reg_param(&reg_params[3]);
1286         destroy_reg_param(&reg_params[4]);
1287         destroy_reg_param(&reg_params[5]);
1288         destroy_reg_param(&reg_params[6]);
1289
1290         return retval;
1291 }
1292
1293 static int cfi_spansion_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1294 {
1295         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1296         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1297         target_t *target = bank->target;
1298         reg_param_t reg_params[10];
1299         armv4_5_algorithm_t armv4_5_info;
1300         working_area_t *source;
1301         uint32_t buffer_size = 32768;
1302         uint32_t status;
1303         int retval, retvaltemp;
1304         int exit_code = ERROR_OK;
1305
1306         /* input parameters - */
1307         /*      R0 = source address */
1308         /*      R1 = destination address */
1309         /*      R2 = number of writes */
1310         /*      R3 = flash write command */
1311         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1312         /* output parameters - */
1313         /*      R5 = 0x80 ok 0x00 bad */
1314         /* temp registers - */
1315         /*      R6 = value read from flash to test status */
1316         /*      R7 = holding register */
1317         /* unlock registers - */
1318         /*  R8 = unlock1_addr */
1319         /*  R9 = unlock1_cmd */
1320         /*  R10 = unlock2_addr */
1321         /*  R11 = unlock2_cmd */
1322
1323         static const uint32_t word_32_code[] = {
1324                                                 /* 00008100 <sp_32_code>:               */
1325                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1326                 0xe5889000,     /* str  r9, [r8]                                */
1327                 0xe58ab000,     /* str  r11, [r10]                              */
1328                 0xe5883000,     /* str  r3, [r8]                                */
1329                 0xe5815000,     /* str  r5, [r1]                                */
1330                 0xe1a00000,     /* nop                                                  */
1331                                                 /*                                                              */
1332                                                 /* 00008110 <sp_32_busy>:               */
1333                 0xe5916000,     /* ldr  r6, [r1]                                */
1334                 0xe0257006,     /* eor  r7, r5, r6                              */
1335                 0xe0147007,     /* ands r7, r4, r7                              */
1336                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1337                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1338                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1339                 0xe5916000,     /* ldr  r6, [r1]                                */
1340                 0xe0257006,     /* eor  r7, r5, r6                              */
1341                 0xe0147007,     /* ands r7, r4, r7                              */
1342                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1343                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1344                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1345                                                 /*                                                              */
1346                                 /* 00008140 <sp_32_cont>:                               */
1347                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1348                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1349                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1350                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1351                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1352                                                 /*                                                              */
1353                                                 /* 00008154 <sp_32_done>:               */
1354                 0xeafffffe              /* b    8154 <sp_32_done>               */
1355                 };
1356
1357                 static const uint32_t word_16_code[] = {
1358                                 /* 00008158 <sp_16_code>:              */
1359                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1360                 0xe1c890b0,     /* strh r9, [r8]                                */
1361                 0xe1cab0b0,     /* strh r11, [r10]                              */
1362                 0xe1c830b0,     /* strh r3, [r8]                                */
1363                 0xe1c150b0,     /* strh r5, [r1]                       */
1364                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1365                                 /*                                     */
1366                                 /* 00008168 <sp_16_busy>:              */
1367                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1368                 0xe0257006,     /* eor  r7, r5, r6                     */
1369                 0xe0147007,     /* ands r7, r4, r7                     */
1370                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1371                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1372                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1373                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1374                 0xe0257006,     /* eor  r7, r5, r6                     */
1375                 0xe0147007,     /* ands r7, r4, r7                     */
1376                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1377                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1378                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1379                                 /*                                     */
1380                                 /* 00008198 <sp_16_cont>:              */
1381                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1382                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1383                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1384                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1385                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1386                                 /*                                     */
1387                                 /* 000081ac <sp_16_done>:              */
1388                 0xeafffffe      /* b    81ac <sp_16_done>              */
1389                 };
1390
1391                 static const uint32_t word_16_code_dq7only[] = {
1392                                 /* <sp_16_code>:                       */
1393                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1394                 0xe1c890b0,     /* strh r9, [r8]                       */
1395                 0xe1cab0b0,     /* strh r11, [r10]                              */
1396                 0xe1c830b0,     /* strh r3, [r8]                                */
1397                 0xe1c150b0,     /* strh r5, [r1]                       */
1398                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1399                                 /*                                     */
1400                                 /* <sp_16_busy>:                       */
1401                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1402                 0xe0257006,     /* eor  r7, r5, r6                     */
1403                 0xe2177080,     /* ands r7, #0x80                      */
1404                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1405                                 /*                                     */
1406                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1407                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1408                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1409                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1410                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1411                                 /*                                     */
1412                                 /* 000081ac <sp_16_done>:              */
1413                 0xeafffffe      /* b    81ac <sp_16_done>              */
1414                 };
1415
1416                 static const uint32_t word_8_code[] = {
1417                                 /* 000081b0 <sp_16_code_end>:          */
1418                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1419                 0xe5c89000,     /* strb r9, [r8]                                */
1420                 0xe5cab000,     /* strb r11, [r10]                              */
1421                 0xe5c83000,     /* strb r3, [r8]                                */
1422                 0xe5c15000,     /* strb r5, [r1]                       */
1423                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1424                                 /*                                     */
1425                                 /* 000081c0 <sp_8_busy>:               */
1426                 0xe5d16000,     /* ldrb r6, [r1]                       */
1427                 0xe0257006,     /* eor  r7, r5, r6                     */
1428                 0xe0147007,     /* ands r7, r4, r7                     */
1429                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1430                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1431                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1432                 0xe5d16000,     /* ldrb r6, [r1]                       */
1433                 0xe0257006,     /* eor  r7, r5, r6                     */
1434                 0xe0147007,     /* ands r7, r4, r7                     */
1435                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1436                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1437                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1438                                 /*                                     */
1439                                 /* 000081f0 <sp_8_cont>:               */
1440                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1441                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1442                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1443                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1444                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1445                                 /*                                     */
1446                                 /* 00008204 <sp_8_done>:               */
1447                 0xeafffffe      /* b    8204 <sp_8_done>               */
1448         };
1449
1450         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1451         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1452         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1453
1454         int target_code_size;
1455         const uint32_t *target_code_src;
1456
1457         switch (bank->bus_width)
1458         {
1459         case 1 :
1460                 target_code_src = word_8_code;
1461                 target_code_size = sizeof(word_8_code);
1462                 break;
1463         case 2 :
1464                 /* Check for DQ5 support */
1465                 if( cfi_info->status_poll_mask & (1 << 5) )
1466                 {
1467                         target_code_src = word_16_code;
1468                         target_code_size = sizeof(word_16_code);
1469                 }
1470                 else
1471                 {
1472                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1473                         target_code_src = word_16_code_dq7only;
1474                         target_code_size = sizeof(word_16_code_dq7only);
1475                 }
1476                 break;
1477         case 4 :
1478                 target_code_src = word_32_code;
1479                 target_code_size = sizeof(word_32_code);
1480                 break;
1481         default:
1482                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1483                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1484         }
1485
1486         /* flash write code */
1487         if (!cfi_info->write_algorithm)
1488         {
1489                 uint8_t *target_code;
1490
1491                 /* convert bus-width dependent algorithm code to correct endiannes */
1492                 target_code = malloc(target_code_size);
1493                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1494
1495                 /* allocate working area */
1496                 retval = target_alloc_working_area(target, target_code_size,
1497                                 &cfi_info->write_algorithm);
1498                 if (retval != ERROR_OK)
1499                 {
1500                         free(target_code);
1501                         return retval;
1502                 }
1503
1504                 /* write algorithm code to working area */
1505                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1506                                     target_code_size, target_code)) != ERROR_OK)
1507                 {
1508                         free(target_code);
1509                         return retval;
1510                 }
1511
1512                 free(target_code);
1513         }
1514         /* the following code still assumes target code is fixed 24*4 bytes */
1515
1516         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1517         {
1518                 buffer_size /= 2;
1519                 if (buffer_size <= 256)
1520                 {
1521                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1522                         if (cfi_info->write_algorithm)
1523                                 target_free_working_area(target, cfi_info->write_algorithm);
1524
1525                         LOG_WARNING("not enough working area available, can't do block memory writes");
1526                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1527                 }
1528         };
1529
1530         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1531         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1532         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1533         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1534         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1535         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1536         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1537         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1538         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1539         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1540
1541         while (count > 0)
1542         {
1543                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1544
1545                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1546
1547                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1548                 buf_set_u32(reg_params[1].value, 0, 32, address);
1549                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1550                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1551                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1552                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1553                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1554                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1555                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1556
1557                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1558                                                      cfi_info->write_algorithm->address,
1559                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1560                                                      10000, &armv4_5_info);
1561
1562                 status = buf_get_u32(reg_params[5].value, 0, 32);
1563
1564                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1565                 {
1566                         LOG_DEBUG("status: 0x%" PRIx32 , status);
1567                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1568                         break;
1569                 }
1570
1571                 buffer += thisrun_count;
1572                 address += thisrun_count;
1573                 count -= thisrun_count;
1574         }
1575
1576         target_free_all_working_areas(target);
1577
1578         destroy_reg_param(&reg_params[0]);
1579         destroy_reg_param(&reg_params[1]);
1580         destroy_reg_param(&reg_params[2]);
1581         destroy_reg_param(&reg_params[3]);
1582         destroy_reg_param(&reg_params[4]);
1583         destroy_reg_param(&reg_params[5]);
1584         destroy_reg_param(&reg_params[6]);
1585         destroy_reg_param(&reg_params[7]);
1586         destroy_reg_param(&reg_params[8]);
1587         destroy_reg_param(&reg_params[9]);
1588
1589         return exit_code;
1590 }
1591
1592 static int cfi_intel_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1593 {
1594         int retval;
1595         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1596         target_t *target = bank->target;
1597         uint8_t command[8];
1598
1599         cfi_intel_clear_status_register(bank);
1600         cfi_command(bank, 0x40, command);
1601         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1602         {
1603                 return retval;
1604         }
1605
1606         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1607         {
1608                 return retval;
1609         }
1610
1611         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1612         {
1613                 cfi_command(bank, 0xff, command);
1614                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1615                 {
1616                         return retval;
1617                 }
1618
1619                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1620                 return ERROR_FLASH_OPERATION_FAILED;
1621         }
1622
1623         return ERROR_OK;
1624 }
1625
1626 static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1627 {
1628         int retval;
1629         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1630         target_t *target = bank->target;
1631         uint8_t command[8];
1632
1633         /* Calculate buffer size and boundary mask */
1634         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1635         uint32_t buffermask = buffersize-1;
1636         uint32_t bufferwsize;
1637
1638         /* Check for valid range */
1639         if (address & buffermask)
1640         {
1641                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1642                           bank->base, address, cfi_info->max_buf_write_size);
1643                 return ERROR_FLASH_OPERATION_FAILED;
1644         }
1645         switch (bank->chip_width)
1646         {
1647         case 4 : bufferwsize = buffersize / 4; break;
1648         case 2 : bufferwsize = buffersize / 2; break;
1649         case 1 : bufferwsize = buffersize; break;
1650         default:
1651                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1652                 return ERROR_FLASH_OPERATION_FAILED;
1653         }
1654
1655         bufferwsize/=(bank->bus_width / bank->chip_width);
1656
1657
1658         /* Check for valid size */
1659         if (wordcount > bufferwsize)
1660         {
1661                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1662                 return ERROR_FLASH_OPERATION_FAILED;
1663         }
1664
1665         /* Write to flash buffer */
1666         cfi_intel_clear_status_register(bank);
1667
1668         /* Initiate buffer operation _*/
1669         cfi_command(bank, 0xE8, command);
1670         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1671         {
1672                 return retval;
1673         }
1674         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1675         {
1676                 cfi_command(bank, 0xff, command);
1677                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1678                 {
1679                         return retval;
1680                 }
1681
1682                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1683                 return ERROR_FLASH_OPERATION_FAILED;
1684         }
1685
1686         /* Write buffer wordcount-1 and data words */
1687         cfi_command(bank, bufferwsize-1, command);
1688         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1689         {
1690                 return retval;
1691         }
1692
1693         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1694         {
1695                 return retval;
1696         }
1697
1698         /* Commit write operation */
1699         cfi_command(bank, 0xd0, command);
1700         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1701         {
1702                 return retval;
1703         }
1704         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1705         {
1706                 cfi_command(bank, 0xff, command);
1707                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1708                 {
1709                         return retval;
1710                 }
1711
1712                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1713                 return ERROR_FLASH_OPERATION_FAILED;
1714         }
1715
1716         return ERROR_OK;
1717 }
1718
1719 static int cfi_spansion_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1720 {
1721         int retval;
1722         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1723         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1724         target_t *target = bank->target;
1725         uint8_t command[8];
1726
1727         cfi_command(bank, 0xaa, command);
1728         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1729         {
1730                 return retval;
1731         }
1732
1733         cfi_command(bank, 0x55, command);
1734         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1735         {
1736                 return retval;
1737         }
1738
1739         cfi_command(bank, 0xa0, command);
1740         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1741         {
1742                 return retval;
1743         }
1744
1745         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1746         {
1747                 return retval;
1748         }
1749
1750         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1751         {
1752                 cfi_command(bank, 0xf0, command);
1753                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1754                 {
1755                         return retval;
1756                 }
1757
1758                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1759                 return ERROR_FLASH_OPERATION_FAILED;
1760         }
1761
1762         return ERROR_OK;
1763 }
1764
1765 static int cfi_spansion_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1766 {
1767         int retval;
1768         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1769         target_t *target = bank->target;
1770         uint8_t command[8];
1771         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1772
1773         /* Calculate buffer size and boundary mask */
1774         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1775         uint32_t buffermask = buffersize-1;
1776         uint32_t bufferwsize;
1777
1778         /* Check for valid range */
1779         if (address & buffermask)
1780         {
1781                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1782                 return ERROR_FLASH_OPERATION_FAILED;
1783         }
1784         switch (bank->chip_width)
1785         {
1786         case 4 : bufferwsize = buffersize / 4; break;
1787         case 2 : bufferwsize = buffersize / 2; break;
1788         case 1 : bufferwsize = buffersize; break;
1789         default:
1790                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1791                 return ERROR_FLASH_OPERATION_FAILED;
1792         }
1793
1794         bufferwsize/=(bank->bus_width / bank->chip_width);
1795
1796         /* Check for valid size */
1797         if (wordcount > bufferwsize)
1798         {
1799                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1800                 return ERROR_FLASH_OPERATION_FAILED;
1801         }
1802
1803         // Unlock
1804         cfi_command(bank, 0xaa, command);
1805         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1806         {
1807                 return retval;
1808         }
1809
1810         cfi_command(bank, 0x55, command);
1811         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1812         {
1813                 return retval;
1814         }
1815
1816         // Buffer load command
1817         cfi_command(bank, 0x25, command);
1818         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1819         {
1820                 return retval;
1821         }
1822
1823         /* Write buffer wordcount-1 and data words */
1824         cfi_command(bank, bufferwsize-1, command);
1825         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1826         {
1827                 return retval;
1828         }
1829
1830         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1831         {
1832                 return retval;
1833         }
1834
1835         /* Commit write operation */
1836         cfi_command(bank, 0x29, command);
1837         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1838         {
1839                 return retval;
1840         }
1841
1842         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1843         {
1844                 cfi_command(bank, 0xf0, command);
1845                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1846                 {
1847                         return retval;
1848                 }
1849
1850                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1851                 return ERROR_FLASH_OPERATION_FAILED;
1852         }
1853
1854         return ERROR_OK;
1855 }
1856
1857 static int cfi_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1858 {
1859         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1860
1861         switch (cfi_info->pri_id)
1862         {
1863                 case 1:
1864                 case 3:
1865                         return cfi_intel_write_word(bank, word, address);
1866                         break;
1867                 case 2:
1868                         return cfi_spansion_write_word(bank, word, address);
1869                         break;
1870                 default:
1871                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1872                         break;
1873         }
1874
1875         return ERROR_FLASH_OPERATION_FAILED;
1876 }
1877
1878 static int cfi_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1879 {
1880         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1881
1882         switch (cfi_info->pri_id)
1883         {
1884                 case 1:
1885                 case 3:
1886                         return cfi_intel_write_words(bank, word, wordcount, address);
1887                         break;
1888                 case 2:
1889                         return cfi_spansion_write_words(bank, word, wordcount, address);
1890                         break;
1891                 default:
1892                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1893                         break;
1894         }
1895
1896         return ERROR_FLASH_OPERATION_FAILED;
1897 }
1898
1899 int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1900 {
1901         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1902         target_t *target = bank->target;
1903         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1904         uint32_t write_p, copy_p;
1905         int align;      /* number of unaligned bytes */
1906         int blk_count; /* number of bus_width bytes for block copy */
1907         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
1908         int i;
1909         int retval;
1910
1911         if (bank->target->state != TARGET_HALTED)
1912         {
1913                 LOG_ERROR("Target not halted");
1914                 return ERROR_TARGET_NOT_HALTED;
1915         }
1916
1917         if (offset + count > bank->size)
1918                 return ERROR_FLASH_DST_OUT_OF_BANK;
1919
1920         if (cfi_info->qry[0] != 'Q')
1921                 return ERROR_FLASH_BANK_NOT_PROBED;
1922
1923         /* start at the first byte of the first word (bus_width size) */
1924         write_p = address & ~(bank->bus_width - 1);
1925         if ((align = address - write_p) != 0)
1926         {
1927                 LOG_INFO("Fixup %d unaligned head bytes", align);
1928
1929                 for (i = 0; i < bank->bus_width; i++)
1930                         current_word[i] = 0;
1931                 copy_p = write_p;
1932
1933                 /* copy bytes before the first write address */
1934                 for (i = 0; i < align; ++i, ++copy_p)
1935                 {
1936                         uint8_t byte;
1937                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1938                         {
1939                                 return retval;
1940                         }
1941                         cfi_add_byte(bank, current_word, byte);
1942                 }
1943
1944                 /* add bytes from the buffer */
1945                 for (; (i < bank->bus_width) && (count > 0); i++)
1946                 {
1947                         cfi_add_byte(bank, current_word, *buffer++);
1948                         count--;
1949                         copy_p++;
1950                 }
1951
1952                 /* if the buffer is already finished, copy bytes after the last write address */
1953                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1954                 {
1955                         uint8_t byte;
1956                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1957                         {
1958                                 return retval;
1959                         }
1960                         cfi_add_byte(bank, current_word, byte);
1961                 }
1962
1963                 retval = cfi_write_word(bank, current_word, write_p);
1964                 if (retval != ERROR_OK)
1965                         return retval;
1966                 write_p = copy_p;
1967         }
1968
1969         /* handle blocks of bus_size aligned bytes */
1970         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1971         switch (cfi_info->pri_id)
1972         {
1973                 /* try block writes (fails without working area) */
1974                 case 1:
1975                 case 3:
1976                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1977                         break;
1978                 case 2:
1979                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1980                         break;
1981                 default:
1982                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1983                         retval = ERROR_FLASH_OPERATION_FAILED;
1984                         break;
1985         }
1986         if (retval == ERROR_OK)
1987         {
1988                 /* Increment pointers and decrease count on succesful block write */
1989                 buffer += blk_count;
1990                 write_p += blk_count;
1991                 count -= blk_count;
1992         }
1993         else
1994         {
1995                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1996                 {
1997                         //adjust buffersize for chip width
1998                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1999                         uint32_t buffermask = buffersize-1;
2000                         uint32_t bufferwsize;
2001
2002                         switch (bank->chip_width)
2003                         {
2004                         case 4 : bufferwsize = buffersize / 4; break;
2005                         case 2 : bufferwsize = buffersize / 2; break;
2006                         case 1 : bufferwsize = buffersize; break;
2007                         default:
2008                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
2009                                 return ERROR_FLASH_OPERATION_FAILED;
2010                         }
2011
2012                         bufferwsize/=(bank->bus_width / bank->chip_width);
2013
2014                         /* fall back to memory writes */
2015                         while (count >= (uint32_t)bank->bus_width)
2016                         {
2017                                 int fallback;
2018                                 if ((write_p & 0xff) == 0)
2019                                 {
2020                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2021                                 }
2022                                 fallback = 1;
2023                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2024                                 {
2025                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2026                                         if (retval == ERROR_OK)
2027                                         {
2028                                                 buffer += buffersize;
2029                                                 write_p += buffersize;
2030                                                 count -= buffersize;
2031                                                 fallback = 0;
2032                                         }
2033                                 }
2034                                 /* try the slow way? */
2035                                 if (fallback)
2036                                 {
2037                                         for (i = 0; i < bank->bus_width; i++)
2038                                                 current_word[i] = 0;
2039
2040                                         for (i = 0; i < bank->bus_width; i++)
2041                                         {
2042                                                 cfi_add_byte(bank, current_word, *buffer++);
2043                                         }
2044
2045                                         retval = cfi_write_word(bank, current_word, write_p);
2046                                         if (retval != ERROR_OK)
2047                                                 return retval;
2048
2049                                         write_p += bank->bus_width;
2050                                         count -= bank->bus_width;
2051                                 }
2052                         }
2053                 }
2054                 else
2055                         return retval;
2056         }
2057
2058         /* return to read array mode, so we can read from flash again for padding */
2059         cfi_command(bank, 0xf0, current_word);
2060         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2061         {
2062                 return retval;
2063         }
2064         cfi_command(bank, 0xff, current_word);
2065         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2066         {
2067                 return retval;
2068         }
2069
2070         /* handle unaligned tail bytes */
2071         if (count > 0)
2072         {
2073                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2074
2075                 copy_p = write_p;
2076                 for (i = 0; i < bank->bus_width; i++)
2077                         current_word[i] = 0;
2078
2079                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2080                 {
2081                         cfi_add_byte(bank, current_word, *buffer++);
2082                         count--;
2083                 }
2084                 for (; i < bank->bus_width; ++i, ++copy_p)
2085                 {
2086                         uint8_t byte;
2087                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2088                         {
2089                                 return retval;
2090                         }
2091                         cfi_add_byte(bank, current_word, byte);
2092                 }
2093                 retval = cfi_write_word(bank, current_word, write_p);
2094                 if (retval != ERROR_OK)
2095                         return retval;
2096         }
2097
2098         /* return to read array mode */
2099         cfi_command(bank, 0xf0, current_word);
2100         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2101         {
2102                 return retval;
2103         }
2104         cfi_command(bank, 0xff, current_word);
2105         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2106 }
2107
2108 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2109 {
2110         (void) param;
2111         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2112         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2113
2114         pri_ext->_reversed_geometry = 1;
2115 }
2116
2117 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2118 {
2119         int i;
2120         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2121         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2122         (void) param;
2123
2124         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2125         {
2126                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2127
2128                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2129                 {
2130                         int j = (cfi_info->num_erase_regions - 1) - i;
2131                         uint32_t swap;
2132
2133                         swap = cfi_info->erase_region_info[i];
2134                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2135                         cfi_info->erase_region_info[j] = swap;
2136                 }
2137         }
2138 }
2139
2140 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2141 {
2142         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2143         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2144         cfi_unlock_addresses_t *unlock_addresses = param;
2145
2146         pri_ext->_unlock1 = unlock_addresses->unlock1;
2147         pri_ext->_unlock2 = unlock_addresses->unlock2;
2148 }
2149
2150
2151 static int cfi_query_string(struct flash_bank_s *bank, int address)
2152 {
2153         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2154         target_t *target = bank->target;
2155         int retval;
2156         uint8_t command[8];
2157
2158         cfi_command(bank, 0x98, command);
2159         if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2160         {
2161                 return retval;
2162         }
2163
2164         cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2165         cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2166         cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2167
2168         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2169
2170         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2171         {
2172                 cfi_command(bank, 0xf0, command);
2173                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2174                 {
2175                         return retval;
2176                 }
2177                 cfi_command(bank, 0xff, command);
2178                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2179                 {
2180                         return retval;
2181                 }
2182                 LOG_ERROR("Could not probe bank: no QRY");
2183                 return ERROR_FLASH_BANK_INVALID;
2184         }
2185
2186         return ERROR_OK;
2187 }
2188
2189 static int cfi_probe(struct flash_bank_s *bank)
2190 {
2191         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2192         target_t *target = bank->target;
2193         uint8_t command[8];
2194         int num_sectors = 0;
2195         int i;
2196         int sector = 0;
2197         uint32_t unlock1 = 0x555;
2198         uint32_t unlock2 = 0x2aa;
2199         int retval;
2200
2201         if (bank->target->state != TARGET_HALTED)
2202         {
2203                 LOG_ERROR("Target not halted");
2204                 return ERROR_TARGET_NOT_HALTED;
2205         }
2206
2207         cfi_info->probed = 0;
2208
2209         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2210          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2211          */
2212         if (cfi_info->jedec_probe)
2213         {
2214                 unlock1 = 0x5555;
2215                 unlock2 = 0x2aaa;
2216         }
2217
2218         /* switch to read identifier codes mode ("AUTOSELECT") */
2219         cfi_command(bank, 0xaa, command);
2220         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2221         {
2222                 return retval;
2223         }
2224         cfi_command(bank, 0x55, command);
2225         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2226         {
2227                 return retval;
2228         }
2229         cfi_command(bank, 0x90, command);
2230         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2231         {
2232                 return retval;
2233         }
2234
2235         if (bank->chip_width == 1)
2236         {
2237                 uint8_t manufacturer, device_id;
2238                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2239                 {
2240                         return retval;
2241                 }
2242                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2243                 {
2244                         return retval;
2245                 }
2246                 cfi_info->manufacturer = manufacturer;
2247                 cfi_info->device_id = device_id;
2248         }
2249         else if (bank->chip_width == 2)
2250         {
2251                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2252                 {
2253                         return retval;
2254                 }
2255                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2256                 {
2257                         return retval;
2258                 }
2259         }
2260
2261         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2262         /* switch back to read array mode */
2263         cfi_command(bank, 0xf0, command);
2264         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2265         {
2266                 return retval;
2267         }
2268         cfi_command(bank, 0xff, command);
2269         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2270         {
2271                 return retval;
2272         }
2273
2274         /* check device/manufacturer ID for known non-CFI flashes. */
2275         cfi_fixup_non_cfi(bank);
2276
2277         /* query only if this is a CFI compatible flash,
2278          * otherwise the relevant info has already been filled in
2279          */
2280         if (cfi_info->not_cfi == 0)
2281         {
2282                 int retval;
2283
2284                 /* enter CFI query mode
2285                  * according to JEDEC Standard No. 68.01,
2286                  * a single bus sequence with address = 0x55, data = 0x98 should put
2287                  * the device into CFI query mode.
2288                  *
2289                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2290                  */
2291
2292                 retval = cfi_query_string(bank, 0x55);
2293                 if (retval != ERROR_OK)
2294                 {
2295                         /*
2296                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2297                          * be harmless enough:
2298                          *
2299                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2300                          */
2301                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2302                         retval = cfi_query_string(bank, 0x555);
2303                 }
2304                 if (retval != ERROR_OK)
2305                         return retval;
2306
2307                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2308                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2309                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2310                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2311
2312                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2313
2314                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2315                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2316                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2317                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2318                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2319                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2320                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2321                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2322                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2323                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2324                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2325                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2326
2327                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2328                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2329                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2330                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2331                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2332                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2333                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2334                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2335                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2336                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2337                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2338
2339                 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2340                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2341                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2342                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2343
2344                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2345
2346                 if (cfi_info->num_erase_regions)
2347                 {
2348                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2349                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2350                         {
2351                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2352                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2353                                           i,
2354                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2355                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2356                         }
2357                 }
2358                 else
2359                 {
2360                         cfi_info->erase_region_info = NULL;
2361                 }
2362
2363                 /* We need to read the primary algorithm extended query table before calculating
2364                  * the sector layout to be able to apply fixups
2365                  */
2366                 switch (cfi_info->pri_id)
2367                 {
2368                         /* Intel command set (standard and extended) */
2369                         case 0x0001:
2370                         case 0x0003:
2371                                 cfi_read_intel_pri_ext(bank);
2372                                 break;
2373                         /* AMD/Spansion, Atmel, ... command set */
2374                         case 0x0002:
2375                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2376                                 cfi_read_0002_pri_ext(bank);
2377                                 break;
2378                         default:
2379                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2380                                 break;
2381                 }
2382
2383                 /* return to read array mode
2384                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2385                  */
2386                 cfi_command(bank, 0xf0, command);
2387                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2388                 {
2389                         return retval;
2390                 }
2391                 cfi_command(bank, 0xff, command);
2392                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2393                 {
2394                         return retval;
2395                 }
2396         } /* end CFI case */
2397
2398         /* apply fixups depending on the primary command set */
2399         switch (cfi_info->pri_id)
2400         {
2401                 /* Intel command set (standard and extended) */
2402                 case 0x0001:
2403                 case 0x0003:
2404                         cfi_fixup(bank, cfi_0001_fixups);
2405                         break;
2406                 /* AMD/Spansion, Atmel, ... command set */
2407                 case 0x0002:
2408                         cfi_fixup(bank, cfi_0002_fixups);
2409                         break;
2410                 default:
2411                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2412                         break;
2413         }
2414
2415         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2416         {
2417                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2418         }
2419
2420         if (cfi_info->num_erase_regions == 0)
2421         {
2422                 /* a device might have only one erase block, spanning the whole device */
2423                 bank->num_sectors = 1;
2424                 bank->sectors = malloc(sizeof(flash_sector_t));
2425
2426                 bank->sectors[sector].offset = 0x0;
2427                 bank->sectors[sector].size = bank->size;
2428                 bank->sectors[sector].is_erased = -1;
2429                 bank->sectors[sector].is_protected = -1;
2430         }
2431         else
2432         {
2433                 uint32_t offset = 0;
2434
2435                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2436                 {
2437                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2438                 }
2439
2440                 bank->num_sectors = num_sectors;
2441                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2442
2443                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2444                 {
2445                         uint32_t j;
2446                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2447                         {
2448                                 bank->sectors[sector].offset = offset;
2449                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2450                                 offset += bank->sectors[sector].size;
2451                                 bank->sectors[sector].is_erased = -1;
2452                                 bank->sectors[sector].is_protected = -1;
2453                                 sector++;
2454                         }
2455                 }
2456                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2457                 {
2458                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2459                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2460                 }
2461         }
2462
2463         cfi_info->probed = 1;
2464
2465         return ERROR_OK;
2466 }
2467
2468 static int cfi_auto_probe(struct flash_bank_s *bank)
2469 {
2470         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2471         if (cfi_info->probed)
2472                 return ERROR_OK;
2473         return cfi_probe(bank);
2474 }
2475
2476
2477 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2478 {
2479         int retval;
2480         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2481         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2482         target_t *target = bank->target;
2483         uint8_t command[CFI_MAX_BUS_WIDTH];
2484         int i;
2485
2486         /* check if block lock bits are supported on this device */
2487         if (!(pri_ext->blk_status_reg_mask & 0x1))
2488                 return ERROR_FLASH_OPERATION_FAILED;
2489
2490         cfi_command(bank, 0x90, command);
2491         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2492         {
2493                 return retval;
2494         }
2495
2496         for (i = 0; i < bank->num_sectors; i++)
2497         {
2498                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2499
2500                 if (block_status & 1)
2501                         bank->sectors[i].is_protected = 1;
2502                 else
2503                         bank->sectors[i].is_protected = 0;
2504         }
2505
2506         cfi_command(bank, 0xff, command);
2507         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2508 }
2509
2510 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2511 {
2512         int retval;
2513         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2514         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2515         target_t *target = bank->target;
2516         uint8_t command[8];
2517         int i;
2518
2519         cfi_command(bank, 0xaa, command);
2520         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2521         {
2522                 return retval;
2523         }
2524
2525         cfi_command(bank, 0x55, command);
2526         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2527         {
2528                 return retval;
2529         }
2530
2531         cfi_command(bank, 0x90, command);
2532         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2533         {
2534                 return retval;
2535         }
2536
2537         for (i = 0; i < bank->num_sectors; i++)
2538         {
2539                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2540
2541                 if (block_status & 1)
2542                         bank->sectors[i].is_protected = 1;
2543                 else
2544                         bank->sectors[i].is_protected = 0;
2545         }
2546
2547         cfi_command(bank, 0xf0, command);
2548         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2549 }
2550
2551 static int cfi_protect_check(struct flash_bank_s *bank)
2552 {
2553         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2554
2555         if (bank->target->state != TARGET_HALTED)
2556         {
2557                 LOG_ERROR("Target not halted");
2558                 return ERROR_TARGET_NOT_HALTED;
2559         }
2560
2561         if (cfi_info->qry[0] != 'Q')
2562                 return ERROR_FLASH_BANK_NOT_PROBED;
2563
2564         switch (cfi_info->pri_id)
2565         {
2566                 case 1:
2567                 case 3:
2568                         return cfi_intel_protect_check(bank);
2569                         break;
2570                 case 2:
2571                         return cfi_spansion_protect_check(bank);
2572                         break;
2573                 default:
2574                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2575                         break;
2576         }
2577
2578         return ERROR_OK;
2579 }
2580
2581 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2582 {
2583         int printed;
2584         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2585
2586         if (cfi_info->qry[0] == (char)-1)
2587         {
2588                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2589                 return ERROR_OK;
2590         }
2591
2592         if (cfi_info->not_cfi == 0)
2593                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2594         else
2595                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2596         buf += printed;
2597         buf_size -= printed;
2598
2599         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2600                 cfi_info->manufacturer, cfi_info->device_id);
2601         buf += printed;
2602         buf_size -= printed;
2603
2604         if (cfi_info->not_cfi == 0)
2605         {
2606         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2607         buf += printed;
2608         buf_size -= printed;
2609
2610                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2611                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2612         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2613         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2614         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2615         buf += printed;
2616         buf_size -= printed;
2617
2618                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2619                                    1 << cfi_info->word_write_timeout_typ,
2620                                    1 << cfi_info->buf_write_timeout_typ,
2621                                    1 << cfi_info->block_erase_timeout_typ,
2622                                    1 << cfi_info->chip_erase_timeout_typ);
2623         buf += printed;
2624         buf_size -= printed;
2625
2626                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2627                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2628                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2629                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2630                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2631         buf += printed;
2632         buf_size -= printed;
2633
2634                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2635                                    cfi_info->dev_size,
2636                                    cfi_info->interface_desc,
2637                                    1 << cfi_info->max_buf_write_size);
2638         buf += printed;
2639         buf_size -= printed;
2640
2641         switch (cfi_info->pri_id)
2642         {
2643                 case 1:
2644                 case 3:
2645                         cfi_intel_info(bank, buf, buf_size);
2646                         break;
2647                 case 2:
2648                         cfi_spansion_info(bank, buf, buf_size);
2649                         break;
2650                 default:
2651                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2652                         break;
2653         }
2654         }
2655
2656         return ERROR_OK;
2657 }