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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28
  29 #include "flash.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "armv4_5.h"
  33 #include "algorithm.h"
  34 #include "binarybuffer.h"
  35 #include "types.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40
  41 int cfi_register_commands(struct command_context_s *cmd_ctx);
  42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
  44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  46 int cfi_probe(struct flash_bank_s *bank);
  47 int cfi_auto_probe(struct flash_bank_s *bank);
  48 int cfi_protect_check(struct flash_bank_s *bank);
  49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52
  53 #define CFI_MAX_BUS_WIDTH       4
  54 #define CFI_MAX_CHIP_WIDTH      4
  55
  56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  57 #define CFI_MAX_INTEL_CODESIZE 256
  58
  59 flash_driver_t cfi_flash =
  60 {
  61         .name = "cfi",
  62         .register_commands = cfi_register_commands,
  63         .flash_bank_command = cfi_flash_bank_command,
  64         .erase = cfi_erase,
  65         .protect = cfi_protect,
  66         .write = cfi_write,
  67         .probe = cfi_probe,
  68         .auto_probe = cfi_auto_probe,
  69         .erase_check = default_flash_blank_check,
  70         .protect_check = cfi_protect_check,
  71         .info = cfi_info
  72 };
  73
  74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
  75 {
  76         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  77         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  78 };
  79
  80 /* CFI fixups foward declarations */
  81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  84
  85 /* fixup after identifying JEDEC manufactuer and ID */
  86 cfi_fixup_t cfi_jedec_fixups[] = {
  87         {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
  88         {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
  89         {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
  90         {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
  91         {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
  92         {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
  93         {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
  94         {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
  95         {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
  96         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
  97         {0, 0, NULL, NULL}
  98 };
  99
 100 /* fixup after reading cmdset 0002 primary query table */
 101 cfi_fixup_t cfi_0002_fixups[] = {
 102         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 103         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 104         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 105         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 106         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 107         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
 108         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 109         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 110         {0, 0, NULL, NULL}
 111 };
 112
 113 /* fixup after reading cmdset 0001 primary query table */
 114 cfi_fixup_t cfi_0001_fixups[] = {
 115         {0, 0, NULL, NULL}
 116 };
 117
 118 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 119 {
 120         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 121         cfi_fixup_t *f;
 122
 123         for (f = fixups; f->fixup; f++)
 124         {
 125                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 126                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 127                 {
 128                         f->fixup(bank, f->param);
 129                 }
 130         }
 131 }
 132
 133 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 134 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 135 {
 136         /* while the sector list isn't built, only accesses to sector 0 work */
 137         if (sector == 0)
 138                 return bank->base + offset * bank->bus_width;
 139         else
 140         {
 141                 if (!bank->sectors)
 142                 {
 143                         LOG_ERROR("BUG: sector list not yet built");
 144                         exit(-1);
 145                 }
 146                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 147         }
 148
 149 }
 150
 151 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 152 {
 153         int i;
 154
 155         /* clear whole buffer, to ensure bits that exceed the bus_width
 156          * are set to zero
 157          */
 158         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 159                 cmd_buf[i] = 0;
 160
 161         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 162         {
 163                 for (i = bank->bus_width; i > 0; i--)
 164                 {
 165                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 166                 }
 167         }
 168         else
 169         {
 170                 for (i = 1; i <= bank->bus_width; i++)
 171                 {
 172                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 173                 }
 174         }
 175 }
 176
 177 /* read unsigned 8-bit value from the bank
 178  * flash banks are expected to be made of similar chips
 179  * the query result should be the same for all
 180  */
 181 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 182 {
 183         target_t *target = bank->target;
 184         u8 data[CFI_MAX_BUS_WIDTH];
 185
 186         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 187
 188         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 189                 return data[0];
 190         else
 191                 return data[bank->bus_width - 1];
 192 }
 193
 194 /* read unsigned 8-bit value from the bank
 195  * in case of a bank made of multiple chips,
 196  * the individual values are ORed
 197  */
 198 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 199 {
 200         target_t *target = bank->target;
 201         u8 data[CFI_MAX_BUS_WIDTH];
 202         int i;
 203
 204         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 205
 206         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 207         {
 208                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 209                         data[0] |= data[i];
 210
 211                 return data[0];
 212         }
 213         else
 214         {
 215                 u8 value = 0;
 216                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 217                         value |= data[bank->bus_width - 1 - i];
 218
 219                 return value;
 220         }
 221 }
 222
 223 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 224 {
 225         target_t *target = bank->target;
 226         u8 data[CFI_MAX_BUS_WIDTH * 2];
 227
 228         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 229
 230         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 231                 return data[0] | data[bank->bus_width] << 8;
 232         else
 233                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 234 }
 235
 236 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 237 {
 238         target_t *target = bank->target;
 239         u8 data[CFI_MAX_BUS_WIDTH * 4];
 240
 241         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 242
 243         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 244                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 245         else
 246                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 247                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 248 }
 249
 250 void cfi_intel_clear_status_register(flash_bank_t *bank)
 251 {
 252         target_t *target = bank->target;
 253         u8 command[8];
 254
 255         if (target->state != TARGET_HALTED)
 256         {
 257                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 258                 exit(-1);
 259         }
 260
 261         cfi_command(bank, 0x50, command);
 262         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 263 }
 264
 265 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 266 {
 267         u8 status;
 268
 269         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 270         {
 271                 LOG_DEBUG("status: 0x%x", status);
 272                 usleep(1000);
 273         }
 274
 275         /* mask out bit 0 (reserved) */
 276         status = status & 0xfe;
 277
 278         LOG_DEBUG("status: 0x%x", status);
 279
 280         if ((status & 0x80) != 0x80)
 281         {
 282                 LOG_ERROR("timeout while waiting for WSM to become ready");
 283         }
 284         else if (status != 0x80)
 285         {
 286                 LOG_ERROR("status register: 0x%x", status);
 287                 if (status & 0x2)
 288                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 289                 if (status & 0x4)
 290                         LOG_ERROR("Program suspended");
 291                 if (status & 0x8)
 292                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 293                 if (status & 0x10)
 294                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 295                 if (status & 0x20)
 296                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 297                 if (status & 0x40)
 298                         LOG_ERROR("Block Erase Suspended");
 299
 300                 cfi_intel_clear_status_register(bank);
 301         }
 302
 303         return status;
 304 }
 305
 306 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 307 {
 308         u8 status, oldstatus;
 309
 310         oldstatus = cfi_get_u8(bank, 0, 0x0);
 311
 312         do {
 313                 status = cfi_get_u8(bank, 0, 0x0);
 314                 if ((status ^ oldstatus) & 0x40) {
 315                         if (status & 0x20) {
 316                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 317                                 status = cfi_get_u8(bank, 0, 0x0);
 318                                 if ((status ^ oldstatus) & 0x40) {
 319                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 320                                         return(ERROR_FLASH_OPERATION_FAILED);
 321                                 } else {
 322                                         LOG_DEBUG("status: 0x%x", status);
 323                                         return(ERROR_OK);
 324                                 }
 325                         }
 326                 } else {
 327                         LOG_DEBUG("status: 0x%x", status);
 328                         return(ERROR_OK);
 329                 }
 330
 331                 oldstatus = status;
 332                 usleep(1000);
 333         } while (timeout-- > 0);
 334
 335         LOG_ERROR("timeout, status: 0x%x", status);
 336
 337         return(ERROR_FLASH_BUSY);
 338 }
 339
 340 int cfi_read_intel_pri_ext(flash_bank_t *bank)
 341 {
 342         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 343         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 344         target_t *target = bank->target;
 345         u8 command[8];
 346
 347         cfi_info->pri_ext = pri_ext;
 348
 349         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 350         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 351         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 352
 353         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 354         {
 355                 cfi_command(bank, 0xf0, command);
 356                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 357                 cfi_command(bank, 0xff, command);
 358                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 359                 LOG_ERROR("Could not read bank flash bank information");
 360                 return ERROR_FLASH_BANK_INVALID;
 361         }
 362
 363         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 364         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 365
 366         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 367
 368         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 369         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 370         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 371
 372         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 373
 374         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 375         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 376
 377         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 378                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 379                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 380
 381         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 382         if (pri_ext->num_protection_fields != 1)
 383         {
 384                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 385         }
 386
 387         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 388         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 389         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 390
 391         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 392
 393         return ERROR_OK;
 394 }
 395
 396 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 397 {
 398         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 399         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 400         target_t *target = bank->target;
 401         u8 command[8];
 402
 403         cfi_info->pri_ext = pri_ext;
 404
 405         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 406         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 407         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 408
 409         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 410         {
 411                 cfi_command(bank, 0xf0, command);
 412                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 413                 LOG_ERROR("Could not read spansion bank information");
 414                 return ERROR_FLASH_BANK_INVALID;
 415         }
 416
 417         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 418         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 419
 420         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 421
 422         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 423         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 424         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 425         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 426         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 427         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 428         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 429         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 430         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 431         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 432         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 433
 434         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 435               pri_ext->EraseSuspend, pri_ext->BlkProt);
 436
 437         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 438               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 439
 440         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 441
 442
 443         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 444                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 445                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 446
 447         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 448
 449         /* default values for implementation specific workarounds */
 450         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 451         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 452         pri_ext->_reversed_geometry = 0;
 453
 454         return ERROR_OK;
 455 }
 456
 457 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 458 {
 459         cfi_atmel_pri_ext_t atmel_pri_ext;
 460         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 461         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 462         target_t *target = bank->target;
 463         u8 command[8];
 464
 465         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 466          * but a different primary extended query table.
 467          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 468          */
 469
 470         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 471
 472         cfi_info->pri_ext = pri_ext;
 473
 474         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 475         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 476         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 477
 478         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 479         {
 480                 cfi_command(bank, 0xf0, command);
 481                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 482                 LOG_ERROR("Could not read atmel bank information");
 483                 return ERROR_FLASH_BANK_INVALID;
 484         }
 485
 486         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 487         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 488         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 489
 490         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 491         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 492
 493         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 494
 495         pri_ext->major_version = atmel_pri_ext.major_version;
 496         pri_ext->minor_version = atmel_pri_ext.minor_version;
 497
 498         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 499         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 500         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 501         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 502
 503         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 504                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 505
 506         if (atmel_pri_ext.features & 0x02)
 507                 pri_ext->EraseSuspend = 2;
 508
 509         if (atmel_pri_ext.bottom_boot)
 510                 pri_ext->TopBottom = 2;
 511         else
 512                 pri_ext->TopBottom = 3;
 513
 514         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 515         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 516
 517         return ERROR_OK;
 518 }
 519
 520 int cfi_read_0002_pri_ext(flash_bank_t *bank)
 521 {
 522         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 523
 524         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 525         {
 526                 return cfi_read_atmel_pri_ext(bank);
 527         }
 528         else
 529         {
 530                 return cfi_read_spansion_pri_ext(bank);
 531         }
 532 }
 533
 534 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 535 {
 536         int printed;
 537         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 538         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 539
 540         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 541         buf += printed;
 542         buf_size -= printed;
 543
 544         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 545                            pri_ext->pri[1], pri_ext->pri[2],
 546                            pri_ext->major_version, pri_ext->minor_version);
 547         buf += printed;
 548         buf_size -= printed;
 549
 550         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 551                            (pri_ext->SiliconRevision) >> 2,
 552                            (pri_ext->SiliconRevision) & 0x03);
 553         buf += printed;
 554         buf_size -= printed;
 555
 556         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 557                            pri_ext->EraseSuspend,
 558                            pri_ext->BlkProt);
 559         buf += printed;
 560         buf_size -= printed;
 561
 562         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 563                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 564                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 565
 566         return ERROR_OK;
 567 }
 568
 569 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 570 {
 571         int printed;
 572         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 573         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 574
 575         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 576         buf += printed;
 577         buf_size -= printed;
 578
 579         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 580         buf += printed;
 581         buf_size -= printed;
 582
 583         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 584         buf += printed;
 585         buf_size -= printed;
 586
 587         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 588                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 589                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 590         buf += printed;
 591         buf_size -= printed;
 592
 593         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 594
 595         return ERROR_OK;
 596 }
 597
 598 int cfi_register_commands(struct command_context_s *cmd_ctx)
 599 {
 600         /*command_t *cfi_cmd = */
 601         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 602         /*
 603         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 604                                          "print part id of cfi flash bank <num>");
 605         */
 606         return ERROR_OK;
 607 }
 608
 609 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 610  */
 611 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 612 {
 613         cfi_flash_bank_t *cfi_info;
 614         int i;
 615
 616         if (argc < 6)
 617         {
 618                 LOG_WARNING("incomplete flash_bank cfi configuration");
 619                 return ERROR_FLASH_BANK_INVALID;
 620         }
 621
 622         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 623                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 624         {
 625                 LOG_ERROR("chip and bus width have to specified in bytes");
 626                 return ERROR_FLASH_BANK_INVALID;
 627         }
 628
 629         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 630         cfi_info->probed = 0;
 631         bank->driver_priv = cfi_info;
 632
 633         cfi_info->write_algorithm = NULL;
 634
 635         cfi_info->x16_as_x8 = 0;
 636         cfi_info->jedec_probe = 0;
 637         cfi_info->not_cfi = 0;
 638
 639         for (i = 6; i < argc; i++)
 640         {
 641                 if (strcmp(args[i], "x16_as_x8") == 0)
 642                 {
 643                         cfi_info->x16_as_x8 = 1;
 644                 }
 645                 else if (strcmp(args[i], "jedec_probe") == 0)
 646                 {
 647                         cfi_info->jedec_probe = 1;
 648                 }
 649         }
 650
 651         cfi_info->write_algorithm = NULL;
 652
 653         /* bank wasn't probed yet */
 654         cfi_info->qry[0] = -1;
 655
 656         return ERROR_OK;
 657 }
 658
 659 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 660 {
 661         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 662         target_t *target = bank->target;
 663         u8 command[8];
 664         int i;
 665
 666         cfi_intel_clear_status_register(bank);
 667
 668         for (i = first; i <= last; i++)
 669         {
 670                 cfi_command(bank, 0x20, command);
 671                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 672
 673                 cfi_command(bank, 0xd0, command);
 674                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 675
 676                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 677                         bank->sectors[i].is_erased = 1;
 678                 else
 679                 {
 680                         cfi_command(bank, 0xff, command);
 681                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 682
 683                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 684                         return ERROR_FLASH_OPERATION_FAILED;
 685                 }
 686         }
 687
 688         cfi_command(bank, 0xff, command);
 689         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 690
 691         return ERROR_OK;
 692 }
 693
 694 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 695 {
 696         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 697         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 698         target_t *target = bank->target;
 699         u8 command[8];
 700         int i;
 701
 702         for (i = first; i <= last; i++)
 703         {
 704                 cfi_command(bank, 0xaa, command);
 705                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 706
 707                 cfi_command(bank, 0x55, command);
 708                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 709
 710                 cfi_command(bank, 0x80, command);
 711                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 712
 713                 cfi_command(bank, 0xaa, command);
 714                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 715
 716                 cfi_command(bank, 0x55, command);
 717                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 718
 719                 cfi_command(bank, 0x30, command);
 720                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 721
 722                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 723                         bank->sectors[i].is_erased = 1;
 724                 else
 725                 {
 726                         cfi_command(bank, 0xf0, command);
 727                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 728
 729                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 730                         return ERROR_FLASH_OPERATION_FAILED;
 731                 }
 732         }
 733
 734         cfi_command(bank, 0xf0, command);
 735         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 736
 737         return ERROR_OK;
 738 }
 739
 740 int cfi_erase(struct flash_bank_s *bank, int first, int last)
 741 {
 742         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 743
 744         if (bank->target->state != TARGET_HALTED)
 745         {
 746                 return ERROR_TARGET_NOT_HALTED;
 747         }
 748
 749         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 750         {
 751                 return ERROR_FLASH_SECTOR_INVALID;
 752         }
 753
 754         if (cfi_info->qry[0] != 'Q')
 755                 return ERROR_FLASH_BANK_NOT_PROBED;
 756
 757         switch(cfi_info->pri_id)
 758         {
 759                 case 1:
 760                 case 3:
 761                         return cfi_intel_erase(bank, first, last);
 762                         break;
 763                 case 2:
 764                         return cfi_spansion_erase(bank, first, last);
 765                         break;
 766                 default:
 767                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 768                         break;
 769         }
 770
 771         return ERROR_OK;
 772 }
 773
 774 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 775 {
 776         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 777         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 778         target_t *target = bank->target;
 779         u8 command[8];
 780         int retry = 0;
 781         int i;
 782
 783         /* if the device supports neither legacy lock/unlock (bit 3) nor
 784          * instant individual block locking (bit 5).
 785          */
 786         if (!(pri_ext->feature_support & 0x28))
 787                 return ERROR_FLASH_OPERATION_FAILED;
 788
 789         cfi_intel_clear_status_register(bank);
 790
 791         for (i = first; i <= last; i++)
 792         {
 793                 cfi_command(bank, 0x60, command);
 794                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 795                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 796                 if (set)
 797                 {
 798                         cfi_command(bank, 0x01, command);
 799                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 800                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 801                         bank->sectors[i].is_protected = 1;
 802                 }
 803                 else
 804                 {
 805                         cfi_command(bank, 0xd0, command);
 806                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 807                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 808                         bank->sectors[i].is_protected = 0;
 809                 }
 810
 811                 /* instant individual block locking doesn't require reading of the status register */
 812                 if (!(pri_ext->feature_support & 0x20))
 813                 {
 814                         /* Clear lock bits operation may take up to 1.4s */
 815                         cfi_intel_wait_status_busy(bank, 1400);
 816                 }
 817                 else
 818                 {
 819                         u8 block_status;
 820                         /* read block lock bit, to verify status */
 821                         cfi_command(bank, 0x90, command);
 822                         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 823                         block_status = cfi_get_u8(bank, i, 0x2);
 824
 825                         if ((block_status & 0x1) != set)
 826                         {
 827                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 828                                 cfi_command(bank, 0x70, command);
 829                                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 830                                 cfi_intel_wait_status_busy(bank, 10);
 831
 832                                 if (retry > 10)
 833                                         return ERROR_FLASH_OPERATION_FAILED;
 834                                 else
 835                                 {
 836                                         i--;
 837                                         retry++;
 838                                 }
 839                         }
 840                 }
 841         }
 842
 843         /* if the device doesn't support individual block lock bits set/clear,
 844          * all blocks have been unlocked in parallel, so we set those that should be protected
 845          */
 846         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 847         {
 848                 for (i = 0; i < bank->num_sectors; i++)
 849                 {
 850                         if (bank->sectors[i].is_protected == 1)
 851                         {
 852                                 cfi_intel_clear_status_register(bank);
 853
 854                                 cfi_command(bank, 0x60, command);
 855                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 856
 857                                 cfi_command(bank, 0x01, command);
 858                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 859
 860                                 cfi_intel_wait_status_busy(bank, 100);
 861                         }
 862                 }
 863         }
 864
 865         cfi_command(bank, 0xff, command);
 866         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 867
 868         return ERROR_OK;
 869 }
 870
 871 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 872 {
 873         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 874
 875         if (bank->target->state != TARGET_HALTED)
 876         {
 877                 return ERROR_TARGET_NOT_HALTED;
 878         }
 879
 880         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 881         {
 882                 return ERROR_FLASH_SECTOR_INVALID;
 883         }
 884
 885         if (cfi_info->qry[0] != 'Q')
 886                 return ERROR_FLASH_BANK_NOT_PROBED;
 887
 888         switch(cfi_info->pri_id)
 889         {
 890                 case 1:
 891                 case 3:
 892                         cfi_intel_protect(bank, set, first, last);
 893                         break;
 894                 default:
 895                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 896                         break;
 897         }
 898
 899         return ERROR_OK;
 900 }
 901
 902 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 903 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 904 {
 905         /* target_t *target = bank->target; */
 906
 907         int i;
 908
 909         /* NOTE:
 910          * The data to flash must not be changed in endian! We write a bytestrem in
 911          * target byte order already. Only the control and status byte lane of the flash
 912          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 913          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 914          */
 915
 916 #if 0
 917         if (target->endianness == TARGET_LITTLE_ENDIAN)
 918         {
 919 #endif
 920                 /* shift bytes */
 921                 for (i = 0; i < bank->bus_width - 1; i++)
 922                         word[i] = word[i + 1];
 923                 word[bank->bus_width - 1] = byte;
 924 #if 0
 925         }
 926         else
 927         {
 928                 /* shift bytes */
 929                 for (i = bank->bus_width - 1; i > 0; i--)
 930                         word[i] = word[i - 1];
 931                 word[0] = byte;
 932         }
 933 #endif
 934 }
 935
 936 /* Convert code image to target endian */
 937 /* FIXME create general block conversion fcts in target.c?) */
 938 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 939 {
 940         u32 i;
 941         for (i=0; i< count; i++)
 942         {
 943                 target_buffer_set_u32(target, dest, *src);
 944                 dest+=4;
 945                 src++;
 946         }
 947 }
 948
 949 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
 950 {
 951         target_t *target = bank->target;
 952
 953         u8 buf[CFI_MAX_BUS_WIDTH];
 954         cfi_command(bank, cmd, buf);
 955         switch (bank->bus_width)
 956         {
 957         case 1 :
 958                 return buf[0];
 959                 break;
 960         case 2 :
 961                 return target_buffer_get_u16(target, buf);
 962                 break;
 963         case 4 :
 964                 return target_buffer_get_u32(target, buf);
 965                 break;
 966         default :
 967                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
 968                 return 0;
 969         }
 970 }
 971
 972 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
 973 {
 974         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 975         target_t *target = bank->target;
 976         reg_param_t reg_params[7];
 977         armv4_5_algorithm_t armv4_5_info;
 978         working_area_t *source;
 979         u32 buffer_size = 32768;
 980         u32 write_command_val, busy_pattern_val, error_pattern_val;
 981
 982         /* algorithm register usage:
 983          * r0: source address (in RAM)
 984          * r1: target address (in Flash)
 985          * r2: count
 986          * r3: flash write command
 987          * r4: status byte (returned to host)
 988          * r5: busy test pattern
 989          * r6: error test pattern
 990          */
 991
 992         static const u32 word_32_code[] = {
 993                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
 994                 0xe5813000,   /*                str r3, [r1] */
 995                 0xe5814000,   /*                str r4, [r1] */
 996                 0xe5914000,   /* busy:  ldr r4, [r1] */
 997                 0xe0047005,   /*                and r7, r4, r5 */
 998                 0xe1570005,   /*                cmp r7, r5 */
 999                 0x1afffffb,   /*                bne busy */
1000                 0xe1140006,   /*                tst r4, r6 */
1001                 0x1a000003,   /*                bne done */
1002                 0xe2522001,   /*                subs r2, r2, #1 */
1003                 0x0a000001,   /*                beq done */
1004                 0xe2811004,   /*                add r1, r1 #4 */
1005                 0xeafffff2,   /*                b loop */
1006                 0xeafffffe    /* done:  b -2 */
1007         };
1008
1009         static const u32 word_16_code[] = {
1010                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1011                 0xe1c130b0,   /*                strh r3, [r1] */
1012                 0xe1c140b0,   /*                strh r4, [r1] */
1013                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1014                 0xe0047005,   /*                and r7, r4, r5 */
1015                 0xe1570005,   /*                cmp r7, r5 */
1016                 0x1afffffb,   /*                bne busy */
1017                 0xe1140006,   /*                tst r4, r6 */
1018                 0x1a000003,   /*                bne done */
1019                 0xe2522001,   /*                subs r2, r2, #1 */
1020                 0x0a000001,   /*                beq done */
1021                 0xe2811002,   /*                add r1, r1 #2 */
1022                 0xeafffff2,   /*                b loop */
1023                 0xeafffffe    /* done:  b -2 */
1024         };
1025
1026         static const u32 word_8_code[] = {
1027                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1028                 0xe5c13000,   /*                strb r3, [r1] */
1029                 0xe5c14000,   /*                strb r4, [r1] */
1030                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1031                 0xe0047005,   /*                and r7, r4, r5 */
1032                 0xe1570005,   /*                cmp r7, r5 */
1033                 0x1afffffb,   /*                bne busy */
1034                 0xe1140006,   /*                tst r4, r6 */
1035                 0x1a000003,   /*                bne done */
1036                 0xe2522001,   /*                subs r2, r2, #1 */
1037                 0x0a000001,   /*                beq done */
1038                 0xe2811001,   /*                add r1, r1 #1 */
1039                 0xeafffff2,   /*                b loop */
1040                 0xeafffffe    /* done:  b -2 */
1041         };
1042         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1043         const u32 *target_code_src;
1044         int target_code_size;
1045         int retval = ERROR_OK;
1046
1047
1048         cfi_intel_clear_status_register(bank);
1049
1050         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1051         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1052         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1053
1054         /* If we are setting up the write_algorith, we need target_code_src */
1055         /* if not we only need target_code_size.                                                                                                                */
1056         /*                                                                                                                                                                                                                                                                      */
1057         /* However, we don't want to create multiple code paths, so we                  */
1058         /* do the unecessary evaluation of target_code_src, which the                   */
1059         /* compiler will probably nicely optimize away if not needed                            */
1060
1061         /* prepare algorithm code for target endian */
1062         switch (bank->bus_width)
1063         {
1064         case 1 :
1065                 target_code_src = word_8_code;
1066                 target_code_size = sizeof(word_8_code);
1067                 break;
1068         case 2 :
1069                 target_code_src = word_16_code;
1070                 target_code_size = sizeof(word_16_code);
1071                 break;
1072         case 4 :
1073                 target_code_src = word_32_code;
1074                 target_code_size = sizeof(word_32_code);
1075                 break;
1076         default:
1077                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1078                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1079         }
1080
1081         /* flash write code */
1082         if (!cfi_info->write_algorithm)
1083         {
1084                 if ( target_code_size > sizeof(target_code) )
1085                 {
1086                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1087                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1088                 }
1089                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1090
1091                 /* Get memory for block write handler */
1092                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1093                 if (retval != ERROR_OK)
1094                 {
1095                         LOG_WARNING("No working area available, can't do block memory writes");
1096                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1097                 };
1098
1099                 /* write algorithm code to working area */
1100                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1101                 if (retval != ERROR_OK)
1102                 {
1103                         LOG_ERROR("Unable to write block write code to target");
1104                         goto cleanup;
1105                 }
1106         }
1107
1108         /* Get a workspace buffer for the data to flash starting with 32k size.
1109            Half size until buffer would be smaller 256 Bytem then fail back */
1110         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1111         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1112         {
1113                 buffer_size /= 2;
1114                 if (buffer_size <= 256)
1115                 {
1116                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1117                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1118                         goto cleanup;
1119                 }
1120         };
1121
1122         /* setup algo registers */
1123         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1124         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1125         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1126         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1127         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1128         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1129         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1130
1131         /* prepare command and status register patterns */
1132         write_command_val = cfi_command_val(bank, 0x40);
1133         busy_pattern_val  = cfi_command_val(bank, 0x80);
1134         error_pattern_val = cfi_command_val(bank, 0x7e);
1135
1136         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1137
1138         /* Programming main loop */
1139         while (count > 0)
1140         {
1141                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1142                 u32 wsm_error;
1143
1144                 target_write_buffer(target, source->address, thisrun_count, buffer);
1145
1146                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1147                 buf_set_u32(reg_params[1].value, 0, 32, address);
1148                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1149
1150                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1151                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1152                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1153
1154                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1155
1156                 /* Execute algorithm, assume breakpoint for last instruction */
1157                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1158                         cfi_info->write_algorithm->address,
1159                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1160                         10000, /* 10s should be enough for max. 32k of data */
1161                         &armv4_5_info);
1162
1163                 /* On failure try a fall back to direct word writes */
1164                 if (retval != ERROR_OK)
1165                 {
1166                         cfi_intel_clear_status_register(bank);
1167                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1168                         retval = ERROR_FLASH_OPERATION_FAILED;
1169                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1170                         /* FIXME To allow fall back or recovery, we must save the actual status
1171                            somewhere, so that a higher level code can start recovery. */
1172                         goto cleanup;
1173                 }
1174
1175                 /* Check return value from algo code */
1176                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1177                 if (wsm_error)
1178                 {
1179                         /* read status register (outputs debug inforation) */
1180                         cfi_intel_wait_status_busy(bank, 100);
1181                         cfi_intel_clear_status_register(bank);
1182                         retval = ERROR_FLASH_OPERATION_FAILED;
1183                         goto cleanup;
1184                 }
1185
1186                 buffer += thisrun_count;
1187                 address += thisrun_count;
1188                 count -= thisrun_count;
1189         }
1190
1191         /* free up resources */
1192 cleanup:
1193         if (source)
1194                 target_free_working_area(target, source);
1195
1196         if (cfi_info->write_algorithm)
1197         {
1198                 target_free_working_area(target, cfi_info->write_algorithm);
1199                 cfi_info->write_algorithm = NULL;
1200         }
1201
1202         destroy_reg_param(&reg_params[0]);
1203         destroy_reg_param(&reg_params[1]);
1204         destroy_reg_param(&reg_params[2]);
1205         destroy_reg_param(&reg_params[3]);
1206         destroy_reg_param(&reg_params[4]);
1207         destroy_reg_param(&reg_params[5]);
1208         destroy_reg_param(&reg_params[6]);
1209
1210         return retval;
1211 }
1212
1213 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1214 {
1215         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1216         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1217         target_t *target = bank->target;
1218         reg_param_t reg_params[10];
1219         armv4_5_algorithm_t armv4_5_info;
1220         working_area_t *source;
1221         u32 buffer_size = 32768;
1222         u32 status;
1223         int retval;
1224         int exit_code = ERROR_OK;
1225
1226         /* input parameters - */
1227         /*      R0 = source address */
1228         /*      R1 = destination address */
1229         /*      R2 = number of writes */
1230         /*      R3 = flash write command */
1231         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1232         /* output parameters - */
1233         /*      R5 = 0x80 ok 0x00 bad */
1234         /* temp registers - */
1235         /*      R6 = value read from flash to test status */
1236         /*      R7 = holding register */
1237         /* unlock registers - */
1238         /*  R8 = unlock1_addr */
1239         /*  R9 = unlock1_cmd */
1240         /*  R10 = unlock2_addr */
1241         /*  R11 = unlock2_cmd */
1242
1243         static const u32 word_32_code[] = {
1244                                                 /* 00008100 <sp_32_code>:               */
1245                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1246                 0xe5889000,     /* str  r9, [r8]                                */
1247                 0xe58ab000,     /* str  r11, [r10]                              */
1248                 0xe5883000,     /* str  r3, [r8]                                */
1249                 0xe5815000,     /* str  r5, [r1]                                */
1250                 0xe1a00000,     /* nop                                                  */
1251                                                 /*                                                              */
1252                                                 /* 00008110 <sp_32_busy>:               */
1253                 0xe5916000,     /* ldr  r6, [r1]                                */
1254                 0xe0257006,     /* eor  r7, r5, r6                              */
1255                 0xe0147007,     /* ands r7, r4, r7                              */
1256                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1257                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1258                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1259                 0xe5916000,     /* ldr  r6, [r1]                                */
1260                 0xe0257006,     /* eor  r7, r5, r6                              */
1261                 0xe0147007,     /* ands r7, r4, r7                              */
1262                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1263                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1264                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1265                                                 /*                                                              */
1266                                 /* 00008140 <sp_32_cont>:                               */
1267                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1268                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1269                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1270                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1271                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1272                                                 /*                                                              */
1273                                                 /* 00008154 <sp_32_done>:               */
1274                 0xeafffffe              /* b    8154 <sp_32_done>               */
1275                 };
1276
1277                 static const u32 word_16_code[] = {
1278                                 /* 00008158 <sp_16_code>:              */
1279                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1280                 0xe1c890b0,     /* strh r9, [r8]                                */
1281                 0xe1cab0b0,     /* strh r11, [r10]                              */
1282                 0xe1c830b0,     /* strh r3, [r8]                                */
1283                 0xe1c150b0,     /* strh r5, [r1]                       */
1284                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1285                                 /*                                     */
1286                                 /* 00008168 <sp_16_busy>:              */
1287                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1288                 0xe0257006,     /* eor  r7, r5, r6                     */
1289                 0xe0147007,     /* ands r7, r4, r7                     */
1290                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1291                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1292                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1293                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1294                 0xe0257006,     /* eor  r7, r5, r6                     */
1295                 0xe0147007,     /* ands r7, r4, r7                     */
1296                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1297                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1298                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1299                                 /*                                     */
1300                                 /* 00008198 <sp_16_cont>:              */
1301                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1302                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1303                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1304                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1305                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1306                                 /*                                     */
1307                                 /* 000081ac <sp_16_done>:              */
1308                 0xeafffffe      /* b    81ac <sp_16_done>              */
1309                 };
1310
1311                 static const u32 word_8_code[] = {
1312                                 /* 000081b0 <sp_16_code_end>:          */
1313                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1314                 0xe5c89000,     /* strb r9, [r8]                                */
1315                 0xe5cab000,     /* strb r11, [r10]                              */
1316                 0xe5c83000,     /* strb r3, [r8]                                */
1317                 0xe5c15000,     /* strb r5, [r1]                       */
1318                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1319                                 /*                                     */
1320                                 /* 000081c0 <sp_8_busy>:               */
1321                 0xe5d16000,     /* ldrb r6, [r1]                       */
1322                 0xe0257006,     /* eor  r7, r5, r6                     */
1323                 0xe0147007,     /* ands r7, r4, r7                     */
1324                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1325                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1326                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1327                 0xe5d16000,     /* ldrb r6, [r1]                       */
1328                 0xe0257006,     /* eor  r7, r5, r6                     */
1329                 0xe0147007,     /* ands r7, r4, r7                     */
1330                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1331                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1332                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1333                                 /*                                     */
1334                                 /* 000081f0 <sp_8_cont>:               */
1335                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1336                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1337                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1338                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1339                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1340                                 /*                                     */
1341                                 /* 00008204 <sp_8_done>:               */
1342                 0xeafffffe      /* b    8204 <sp_8_done>               */
1343         };
1344
1345         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1346         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1347         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1348
1349         /* flash write code */
1350         if (!cfi_info->write_algorithm)
1351         {
1352                 u8 *target_code;
1353                 int target_code_size;
1354                 const u32 *src;
1355
1356                 /* convert bus-width dependent algorithm code to correct endiannes */
1357                 switch (bank->bus_width)
1358                 {
1359                 case 1:
1360                         src = word_8_code;
1361                         target_code_size = sizeof(word_8_code);
1362                         break;
1363                 case 2:
1364                         src = word_16_code;
1365                         target_code_size = sizeof(word_16_code);
1366                         break;
1367                 case 4:
1368                         src = word_32_code;
1369                         target_code_size = sizeof(word_32_code);
1370                         break;
1371                 default:
1372                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1373                         return ERROR_FLASH_OPERATION_FAILED;
1374                 }
1375                 target_code = malloc(target_code_size);
1376                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1377
1378                 /* allocate working area */
1379                 retval=target_alloc_working_area(target, target_code_size,
1380                                 &cfi_info->write_algorithm);
1381                 if (retval != ERROR_OK)
1382                         return retval;
1383
1384                 /* write algorithm code to working area */
1385                 target_write_buffer(target, cfi_info->write_algorithm->address,
1386                                     target_code_size, target_code);
1387
1388                 free(target_code);
1389         }
1390         /* the following code still assumes target code is fixed 24*4 bytes */
1391
1392         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1393         {
1394                 buffer_size /= 2;
1395                 if (buffer_size <= 256)
1396                 {
1397                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1398                         if (cfi_info->write_algorithm)
1399                                 target_free_working_area(target, cfi_info->write_algorithm);
1400
1401                         LOG_WARNING("not enough working area available, can't do block memory writes");
1402                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1403                 }
1404         };
1405
1406         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1407         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1408         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1409         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1410         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1411         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1412         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1413         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1414         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1415         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1416
1417         while (count > 0)
1418         {
1419                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1420
1421                 target_write_buffer(target, source->address, thisrun_count, buffer);
1422
1423                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1424                 buf_set_u32(reg_params[1].value, 0, 32, address);
1425                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1426                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1427                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1428                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1429                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1430                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1431                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1432
1433                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1434                                                      cfi_info->write_algorithm->address,
1435                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1436                                                      10000, &armv4_5_info);
1437
1438                 status = buf_get_u32(reg_params[5].value, 0, 32);
1439
1440                 if ((retval != ERROR_OK) || status != 0x80)
1441                 {
1442                         LOG_DEBUG("status: 0x%x", status);
1443                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1444                         break;
1445                 }
1446
1447                 buffer += thisrun_count;
1448                 address += thisrun_count;
1449                 count -= thisrun_count;
1450         }
1451
1452         target_free_working_area(target, source);
1453
1454         destroy_reg_param(&reg_params[0]);
1455         destroy_reg_param(&reg_params[1]);
1456         destroy_reg_param(&reg_params[2]);
1457         destroy_reg_param(&reg_params[3]);
1458         destroy_reg_param(&reg_params[4]);
1459         destroy_reg_param(&reg_params[5]);
1460         destroy_reg_param(&reg_params[6]);
1461         destroy_reg_param(&reg_params[7]);
1462         destroy_reg_param(&reg_params[8]);
1463         destroy_reg_param(&reg_params[9]);
1464
1465         return exit_code;
1466 }
1467
1468 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1469 {
1470         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1471         target_t *target = bank->target;
1472         u8 command[8];
1473
1474         cfi_intel_clear_status_register(bank);
1475         cfi_command(bank, 0x40, command);
1476         target->type->write_memory(target, address, bank->bus_width, 1, command);
1477
1478         target->type->write_memory(target, address, bank->bus_width, 1, word);
1479
1480         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1481         {
1482                 cfi_command(bank, 0xff, command);
1483                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1484
1485                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1486                 return ERROR_FLASH_OPERATION_FAILED;
1487         }
1488
1489         return ERROR_OK;
1490 }
1491
1492 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1493 {
1494         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1495         target_t *target = bank->target;
1496         u8 command[8];
1497
1498         /* Calculate buffer size and boundary mask */
1499         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1500         u32 buffermask = buffersize-1;
1501         u32 bufferwsize;
1502
1503         /* Check for valid range */
1504         if (address & buffermask)
1505         {
1506                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1507                 return ERROR_FLASH_OPERATION_FAILED;
1508         }
1509         switch(bank->chip_width)
1510         {
1511         case 4 : bufferwsize = buffersize / 4; break;
1512         case 2 : bufferwsize = buffersize / 2; break;
1513         case 1 : bufferwsize = buffersize; break;
1514         default:
1515                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1516                 return ERROR_FLASH_OPERATION_FAILED;
1517         }
1518
1519         /* Check for valid size */
1520         if (wordcount > bufferwsize)
1521         {
1522                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1523                 return ERROR_FLASH_OPERATION_FAILED;
1524         }
1525
1526         /* Write to flash buffer */
1527         cfi_intel_clear_status_register(bank);
1528
1529         /* Initiate buffer operation _*/
1530         cfi_command(bank, 0xE8, command);
1531         target->type->write_memory(target, address, bank->bus_width, 1, command);
1532         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1533         {
1534                 cfi_command(bank, 0xff, command);
1535                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1536
1537                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1538                 return ERROR_FLASH_OPERATION_FAILED;
1539         }
1540
1541         /* Write buffer wordcount-1 and data words */
1542         cfi_command(bank, bufferwsize-1, command);
1543         target->type->write_memory(target, address, bank->bus_width, 1, command);
1544
1545         target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1546
1547         /* Commit write operation */
1548         cfi_command(bank, 0xd0, command);
1549         target->type->write_memory(target, address, bank->bus_width, 1, command);
1550         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1551         {
1552                 cfi_command(bank, 0xff, command);
1553                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1554
1555                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1556                 return ERROR_FLASH_OPERATION_FAILED;
1557         }
1558
1559         return ERROR_OK;
1560 }
1561
1562 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1563 {
1564         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1565         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1566         target_t *target = bank->target;
1567         u8 command[8];
1568
1569         cfi_command(bank, 0xaa, command);
1570         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1571
1572         cfi_command(bank, 0x55, command);
1573         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1574
1575         cfi_command(bank, 0xa0, command);
1576         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1577
1578         target->type->write_memory(target, address, bank->bus_width, 1, word);
1579
1580         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1581         {
1582                 cfi_command(bank, 0xf0, command);
1583                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1584
1585                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1586                 return ERROR_FLASH_OPERATION_FAILED;
1587         }
1588
1589         return ERROR_OK;
1590 }
1591
1592 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1593 {
1594         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1595
1596         switch(cfi_info->pri_id)
1597         {
1598                 case 1:
1599                 case 3:
1600                         return cfi_intel_write_word(bank, word, address);
1601                         break;
1602                 case 2:
1603                         return cfi_spansion_write_word(bank, word, address);
1604                         break;
1605                 default:
1606                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1607                         break;
1608         }
1609
1610         return ERROR_FLASH_OPERATION_FAILED;
1611 }
1612
1613 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1614 {
1615         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1616
1617         switch(cfi_info->pri_id)
1618         {
1619                 case 1:
1620                 case 3:
1621                         return cfi_intel_write_words(bank, word, wordcount, address);
1622                         break;
1623                 case 2:
1624                         /* return cfi_spansion_write_words(bank, word, address); */
1625                         LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1626                         break;
1627                 default:
1628                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1629                         break;
1630         }
1631
1632         return ERROR_FLASH_OPERATION_FAILED;
1633 }
1634
1635 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1636 {
1637         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1638         target_t *target = bank->target;
1639         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1640         u32 write_p, copy_p;
1641         int align;      /* number of unaligned bytes */
1642         int blk_count; /* number of bus_width bytes for block copy */
1643         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1644         int i;
1645         int retval;
1646
1647         if (bank->target->state != TARGET_HALTED)
1648                 return ERROR_TARGET_NOT_HALTED;
1649
1650         if (offset + count > bank->size)
1651                 return ERROR_FLASH_DST_OUT_OF_BANK;
1652
1653         if (cfi_info->qry[0] != 'Q')
1654                 return ERROR_FLASH_BANK_NOT_PROBED;
1655
1656         /* start at the first byte of the first word (bus_width size) */
1657         write_p = address & ~(bank->bus_width - 1);
1658         if ((align = address - write_p) != 0)
1659         {
1660                 LOG_INFO("Fixup %d unaligned head bytes", align );
1661
1662                 for (i = 0; i < bank->bus_width; i++)
1663                         current_word[i] = 0;
1664                 copy_p = write_p;
1665
1666                 /* copy bytes before the first write address */
1667                 for (i = 0; i < align; ++i, ++copy_p)
1668                 {
1669                         u8 byte;
1670                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1671                         cfi_add_byte(bank, current_word, byte);
1672                 }
1673
1674                 /* add bytes from the buffer */
1675                 for (; (i < bank->bus_width) && (count > 0); i++)
1676                 {
1677                         cfi_add_byte(bank, current_word, *buffer++);
1678                         count--;
1679                         copy_p++;
1680                 }
1681
1682                 /* if the buffer is already finished, copy bytes after the last write address */
1683                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1684                 {
1685                         u8 byte;
1686                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1687                         cfi_add_byte(bank, current_word, byte);
1688                 }
1689
1690                 retval = cfi_write_word(bank, current_word, write_p);
1691                 if (retval != ERROR_OK)
1692                         return retval;
1693                 write_p = copy_p;
1694         }
1695
1696         /* handle blocks of bus_size aligned bytes */
1697         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1698         switch(cfi_info->pri_id)
1699         {
1700                 /* try block writes (fails without working area) */
1701                 case 1:
1702                 case 3:
1703                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1704                         break;
1705                 case 2:
1706                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1707                         break;
1708                 default:
1709                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1710                         retval = ERROR_FLASH_OPERATION_FAILED;
1711                         break;
1712         }
1713         if (retval == ERROR_OK)
1714         {
1715                 /* Increment pointers and decrease count on succesful block write */
1716                 buffer += blk_count;
1717                 write_p += blk_count;
1718                 count -= blk_count;
1719         }
1720         else
1721         {
1722                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1723                 {
1724                         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1725                         u32 buffermask = buffersize-1;
1726                         u32 bufferwsize;
1727
1728                         switch(bank->chip_width)
1729                         {
1730                         case 4 : bufferwsize = buffersize / 4; break;
1731                         case 2 : bufferwsize = buffersize / 2; break;
1732                         case 1 : bufferwsize = buffersize; break;
1733                         default:
1734                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1735                                 return ERROR_FLASH_OPERATION_FAILED;
1736                         }
1737
1738                         /* fall back to memory writes */
1739                         while (count >= bank->bus_width)
1740                         {
1741                                 if ((write_p & 0xff) == 0)
1742                                 {
1743                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1744                                 }
1745                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1746                                 {
1747                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1748                                         if (retval != ERROR_OK)
1749                                                 return retval;
1750
1751                                         buffer += buffersize;
1752                                         write_p += buffersize;
1753                                         count -= buffersize;
1754                                 }
1755                                 else
1756                                 {
1757                                         for (i = 0; i < bank->bus_width; i++)
1758                                                 current_word[i] = 0;
1759
1760                                         for (i = 0; i < bank->bus_width; i++)
1761                                         {
1762                                                 cfi_add_byte(bank, current_word, *buffer++);
1763                                         }
1764
1765                                         retval = cfi_write_word(bank, current_word, write_p);
1766                                         if (retval != ERROR_OK)
1767                                                 return retval;
1768
1769                                         write_p += bank->bus_width;
1770                                         count -= bank->bus_width;
1771                                 }
1772                         }
1773                 }
1774                 else
1775                         return retval;
1776         }
1777
1778         /* return to read array mode, so we can read from flash again for padding */
1779         cfi_command(bank, 0xf0, current_word);
1780         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1781         cfi_command(bank, 0xff, current_word);
1782         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1783
1784         /* handle unaligned tail bytes */
1785         if (count > 0)
1786         {
1787                 LOG_INFO("Fixup %d unaligned tail bytes", count );
1788
1789                 copy_p = write_p;
1790                 for (i = 0; i < bank->bus_width; i++)
1791                         current_word[i] = 0;
1792
1793                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1794                 {
1795                         cfi_add_byte(bank, current_word, *buffer++);
1796                         count--;
1797                 }
1798                 for (; i < bank->bus_width; ++i, ++copy_p)
1799                 {
1800                         u8 byte;
1801                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1802                         cfi_add_byte(bank, current_word, byte);
1803                 }
1804                 retval = cfi_write_word(bank, current_word, write_p);
1805                 if (retval != ERROR_OK)
1806                         return retval;
1807         }
1808
1809         /* return to read array mode */
1810         cfi_command(bank, 0xf0, current_word);
1811         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1812         cfi_command(bank, 0xff, current_word);
1813         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1814
1815         return ERROR_OK;
1816 }
1817
1818 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1819 {
1820         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1821         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1822
1823         pri_ext->_reversed_geometry = 1;
1824 }
1825
1826 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1827 {
1828         int i;
1829         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1830         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1831
1832         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1833         {
1834                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1835
1836                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1837                 {
1838                         int j = (cfi_info->num_erase_regions - 1) - i;
1839                         u32 swap;
1840
1841                         swap = cfi_info->erase_region_info[i];
1842                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1843                         cfi_info->erase_region_info[j] = swap;
1844                 }
1845         }
1846 }
1847
1848 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1849 {
1850         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1851         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1852         cfi_unlock_addresses_t *unlock_addresses = param;
1853
1854         pri_ext->_unlock1 = unlock_addresses->unlock1;
1855         pri_ext->_unlock2 = unlock_addresses->unlock2;
1856 }
1857
1858 int cfi_probe(struct flash_bank_s *bank)
1859 {
1860         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1861         target_t *target = bank->target;
1862         u8 command[8];
1863         int num_sectors = 0;
1864         int i;
1865         int sector = 0;
1866         u32 offset = 0;
1867         u32 unlock1 = 0x555;
1868         u32 unlock2 = 0x2aa;
1869
1870         if (bank->target->state != TARGET_HALTED)
1871         {
1872                 return ERROR_TARGET_NOT_HALTED;
1873         }
1874
1875         cfi_info->probed = 0;
1876
1877         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1878          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1879          */
1880         if (cfi_info->jedec_probe)
1881         {
1882                 unlock1 = 0x5555;
1883                 unlock2 = 0x2aaa;
1884         }
1885
1886         /* switch to read identifier codes mode ("AUTOSELECT") */
1887         cfi_command(bank, 0xaa, command);
1888         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1889         cfi_command(bank, 0x55, command);
1890         target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1891         cfi_command(bank, 0x90, command);
1892         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1893
1894         if (bank->chip_width == 1)
1895         {
1896                 u8 manufacturer, device_id;
1897                 target_read_u8(target, bank->base + 0x0, &manufacturer);
1898                 target_read_u8(target, bank->base + 0x1, &device_id);
1899                 cfi_info->manufacturer = manufacturer;
1900                 cfi_info->device_id = device_id;
1901         }
1902         else if (bank->chip_width == 2)
1903         {
1904                 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1905                 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1906         }
1907
1908         /* switch back to read array mode */
1909         cfi_command(bank, 0xf0, command);
1910         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1911         cfi_command(bank, 0xff, command);
1912         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1913
1914         cfi_fixup(bank, cfi_jedec_fixups);
1915
1916         /* query only if this is a CFI compatible flash,
1917          * otherwise the relevant info has already been filled in
1918          */
1919         if (cfi_info->not_cfi == 0)
1920         {
1921                 /* enter CFI query mode
1922                  * according to JEDEC Standard No. 68.01,
1923                  * a single bus sequence with address = 0x55, data = 0x98 should put
1924                  * the device into CFI query mode.
1925                  *
1926                  * SST flashes clearly violate this, and we will consider them incompatbile for now
1927                  */
1928                 cfi_command(bank, 0x98, command);
1929                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1930
1931                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1932                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1933                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1934
1935                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1936
1937                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1938                 {
1939                         cfi_command(bank, 0xf0, command);
1940                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1941                         cfi_command(bank, 0xff, command);
1942                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1943                         LOG_ERROR("Could not probe bank");
1944                         return ERROR_FLASH_BANK_INVALID;
1945                 }
1946
1947                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1948                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1949                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1950                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1951
1952                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1953
1954                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1955                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1956                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1957                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1958                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1959                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1960                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1961                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1962                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1963                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1964                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1965                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1966
1967                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1968                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1969                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1970                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1971                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1972                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1973                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1974                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1975                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1976                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1977                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1978
1979                 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1980                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1981                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1982                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1983
1984                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1985
1986                 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1987                 {
1988                         LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1989                 }
1990
1991                 if (cfi_info->num_erase_regions)
1992                 {
1993                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1994                         for (i = 0; i < cfi_info->num_erase_regions; i++)
1995                         {
1996                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1997                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1998                         }
1999                 }
2000                 else
2001                 {
2002                         cfi_info->erase_region_info = NULL;
2003                 }
2004
2005                 /* We need to read the primary algorithm extended query table before calculating
2006                  * the sector layout to be able to apply fixups
2007                  */
2008                 switch(cfi_info->pri_id)
2009                 {
2010                         /* Intel command set (standard and extended) */
2011                         case 0x0001:
2012                         case 0x0003:
2013                                 cfi_read_intel_pri_ext(bank);
2014                                 break;
2015                         /* AMD/Spansion, Atmel, ... command set */
2016                         case 0x0002:
2017                                 cfi_read_0002_pri_ext(bank);
2018                                 break;
2019                         default:
2020                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2021                                 break;
2022                 }
2023
2024                 /* return to read array mode
2025                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2026                  */
2027                 cfi_command(bank, 0xf0, command);
2028                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2029                 cfi_command(bank, 0xff, command);
2030                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2031         }
2032
2033         /* apply fixups depending on the primary command set */
2034         switch(cfi_info->pri_id)
2035         {
2036                 /* Intel command set (standard and extended) */
2037                 case 0x0001:
2038                 case 0x0003:
2039                         cfi_fixup(bank, cfi_0001_fixups);
2040                         break;
2041                 /* AMD/Spansion, Atmel, ... command set */
2042                 case 0x0002:
2043                         cfi_fixup(bank, cfi_0002_fixups);
2044                         break;
2045                 default:
2046                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2047                         break;
2048         }
2049
2050         if (cfi_info->num_erase_regions == 0)
2051         {
2052                 /* a device might have only one erase block, spanning the whole device */
2053                 bank->num_sectors = 1;
2054                 bank->sectors = malloc(sizeof(flash_sector_t));
2055
2056                 bank->sectors[sector].offset = 0x0;
2057                 bank->sectors[sector].size = bank->size;
2058                 bank->sectors[sector].is_erased = -1;
2059                 bank->sectors[sector].is_protected = -1;
2060         }
2061         else
2062         {
2063                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2064                 {
2065                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2066                 }
2067
2068                 bank->num_sectors = num_sectors;
2069                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2070
2071                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2072                 {
2073                         int j;
2074                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2075                         {
2076                                 bank->sectors[sector].offset = offset;
2077                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2078                                 offset += bank->sectors[sector].size;
2079                                 bank->sectors[sector].is_erased = -1;
2080                                 bank->sectors[sector].is_protected = -1;
2081                                 sector++;
2082                         }
2083                 }
2084         }
2085
2086         cfi_info->probed = 1;
2087
2088         return ERROR_OK;
2089 }
2090
2091 int cfi_auto_probe(struct flash_bank_s *bank)
2092 {
2093         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2094         if (cfi_info->probed)
2095                 return ERROR_OK;
2096         return cfi_probe(bank);
2097 }
2098
2099
2100 int cfi_intel_protect_check(struct flash_bank_s *bank)
2101 {
2102         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2103         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2104         target_t *target = bank->target;
2105         u8 command[CFI_MAX_BUS_WIDTH];
2106         int i;
2107
2108         /* check if block lock bits are supported on this device */
2109         if (!(pri_ext->blk_status_reg_mask & 0x1))
2110                 return ERROR_FLASH_OPERATION_FAILED;
2111
2112         cfi_command(bank, 0x90, command);
2113         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2114
2115         for (i = 0; i < bank->num_sectors; i++)
2116         {
2117                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2118
2119                 if (block_status & 1)
2120                         bank->sectors[i].is_protected = 1;
2121                 else
2122                         bank->sectors[i].is_protected = 0;
2123         }
2124
2125         cfi_command(bank, 0xff, command);
2126         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2127
2128         return ERROR_OK;
2129 }
2130
2131 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2132 {
2133         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2134         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2135         target_t *target = bank->target;
2136         u8 command[8];
2137         int i;
2138
2139         cfi_command(bank, 0xaa, command);
2140         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2141
2142         cfi_command(bank, 0x55, command);
2143         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2144
2145         cfi_command(bank, 0x90, command);
2146         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2147
2148         for (i = 0; i < bank->num_sectors; i++)
2149         {
2150                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2151
2152                 if (block_status & 1)
2153                         bank->sectors[i].is_protected = 1;
2154                 else
2155                         bank->sectors[i].is_protected = 0;
2156         }
2157
2158         cfi_command(bank, 0xf0, command);
2159         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2160
2161         return ERROR_OK;
2162 }
2163
2164 int cfi_protect_check(struct flash_bank_s *bank)
2165 {
2166         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2167
2168         if (bank->target->state != TARGET_HALTED)
2169         {
2170                 return ERROR_TARGET_NOT_HALTED;
2171         }
2172
2173         if (cfi_info->qry[0] != 'Q')
2174                 return ERROR_FLASH_BANK_NOT_PROBED;
2175
2176         switch(cfi_info->pri_id)
2177         {
2178                 case 1:
2179                 case 3:
2180                         return cfi_intel_protect_check(bank);
2181                         break;
2182                 case 2:
2183                         return cfi_spansion_protect_check(bank);
2184                         break;
2185                 default:
2186                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2187                         break;
2188         }
2189
2190         return ERROR_OK;
2191 }
2192
2193 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2194 {
2195         int printed;
2196         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2197
2198         if (cfi_info->qry[0] == (char)-1)
2199         {
2200                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2201                 return ERROR_OK;
2202         }
2203
2204         if (cfi_info->not_cfi == 0)
2205         printed = snprintf(buf, buf_size, "\ncfi information:\n");
2206         else
2207                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2208         buf += printed;
2209         buf_size -= printed;
2210
2211         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2212                 cfi_info->manufacturer, cfi_info->device_id);
2213         buf += printed;
2214         buf_size -= printed;
2215
2216         if (cfi_info->not_cfi == 0)
2217         {
2218         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2219         buf += printed;
2220         buf_size -= printed;
2221
2222                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2223                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2224         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2225         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2226         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2227         buf += printed;
2228         buf_size -= printed;
2229
2230                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2231                                    1 << cfi_info->word_write_timeout_typ,
2232                                    1 << cfi_info->buf_write_timeout_typ,
2233                                    1 << cfi_info->block_erase_timeout_typ,
2234                                    1 << cfi_info->chip_erase_timeout_typ);
2235         buf += printed;
2236         buf_size -= printed;
2237
2238                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2239                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2240                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2241                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2242                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2243         buf += printed;
2244         buf_size -= printed;
2245
2246                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2247                                    1 << cfi_info->dev_size,
2248                                    cfi_info->interface_desc,
2249                                    cfi_info->max_buf_write_size);
2250         buf += printed;
2251         buf_size -= printed;
2252
2253         switch(cfi_info->pri_id)
2254         {
2255                 case 1:
2256                 case 3:
2257                         cfi_intel_info(bank, buf, buf_size);
2258                         break;
2259                 case 2:
2260                         cfi_spansion_info(bank, buf, buf_size);
2261                         break;
2262                 default:
2263                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2264                         break;
2265         }
2266         }
2267
2268         return ERROR_OK;
2269 }