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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28
  29 #include "flash.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "armv4_5.h"
  33 #include "algorithm.h"
  34 #include "binarybuffer.h"
  35 #include "types.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40
  41 int cfi_register_commands(struct command_context_s *cmd_ctx);
  42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
  44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  46 int cfi_probe(struct flash_bank_s *bank);
  47 int cfi_auto_probe(struct flash_bank_s *bank);
  48 int cfi_protect_check(struct flash_bank_s *bank);
  49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52
  53 #define CFI_MAX_BUS_WIDTH       4
  54 #define CFI_MAX_CHIP_WIDTH      4
  55
  56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  57 #define CFI_MAX_INTEL_CODESIZE 256
  58
  59 flash_driver_t cfi_flash =
  60 {
  61         .name = "cfi",
  62         .register_commands = cfi_register_commands,
  63         .flash_bank_command = cfi_flash_bank_command,
  64         .erase = cfi_erase,
  65         .protect = cfi_protect,
  66         .write = cfi_write,
  67         .probe = cfi_probe,
  68         .auto_probe = cfi_auto_probe,
  69         .erase_check = default_flash_blank_check,
  70         .protect_check = cfi_protect_check,
  71         .info = cfi_info
  72 };
  73
  74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
  75 {
  76         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  77         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  78 };
  79
  80 /* CFI fixups foward declarations */
  81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  84
  85 /* fixup after identifying JEDEC manufactuer and ID */
  86 cfi_fixup_t cfi_jedec_fixups[] = {
  87         {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
  88         {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
  89         {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
  90         {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
  91         {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
  92         {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
  93         {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
  94         {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
  95         {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
  96         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
  97         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_non_cfi, NULL},
  98         {CFI_MFR_MX, 0x225b, cfi_fixup_non_cfi, NULL},
  99         {CFI_MFR_AMD, 0x225b, cfi_fixup_non_cfi, NULL},
 100         {0, 0, NULL, NULL}
 101 };
 102
 103 /* fixup after reading cmdset 0002 primary query table */
 104 cfi_fixup_t cfi_0002_fixups[] = {
 105         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 106         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 107         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 108         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 109         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 110         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
 111         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 112         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
 113         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
 114         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
 115         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 116         {0, 0, NULL, NULL}
 117 };
 118
 119 /* fixup after reading cmdset 0001 primary query table */
 120 cfi_fixup_t cfi_0001_fixups[] = {
 121         {0, 0, NULL, NULL}
 122 };
 123
 124 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 125 {
 126         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 127         cfi_fixup_t *f;
 128
 129         for (f = fixups; f->fixup; f++)
 130         {
 131                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 132                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 133                 {
 134                         f->fixup(bank, f->param);
 135                 }
 136         }
 137 }
 138
 139 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 140 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 141 {
 142         /* while the sector list isn't built, only accesses to sector 0 work */
 143         if (sector == 0)
 144                 return bank->base + offset * bank->bus_width;
 145         else
 146         {
 147                 if (!bank->sectors)
 148                 {
 149                         LOG_ERROR("BUG: sector list not yet built");
 150                         exit(-1);
 151                 }
 152                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 153         }
 154
 155 }
 156
 157 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 158 {
 159         int i;
 160
 161         /* clear whole buffer, to ensure bits that exceed the bus_width
 162          * are set to zero
 163          */
 164         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 165                 cmd_buf[i] = 0;
 166
 167         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 168         {
 169                 for (i = bank->bus_width; i > 0; i--)
 170                 {
 171                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 172                 }
 173         }
 174         else
 175         {
 176                 for (i = 1; i <= bank->bus_width; i++)
 177                 {
 178                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 179                 }
 180         }
 181 }
 182
 183 /* read unsigned 8-bit value from the bank
 184  * flash banks are expected to be made of similar chips
 185  * the query result should be the same for all
 186  */
 187 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 188 {
 189         target_t *target = bank->target;
 190         u8 data[CFI_MAX_BUS_WIDTH];
 191
 192         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 193
 194         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 195                 return data[0];
 196         else
 197                 return data[bank->bus_width - 1];
 198 }
 199
 200 /* read unsigned 8-bit value from the bank
 201  * in case of a bank made of multiple chips,
 202  * the individual values are ORed
 203  */
 204 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 205 {
 206         target_t *target = bank->target;
 207         u8 data[CFI_MAX_BUS_WIDTH];
 208         int i;
 209
 210         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 211
 212         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 213         {
 214                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 215                         data[0] |= data[i];
 216
 217                 return data[0];
 218         }
 219         else
 220         {
 221                 u8 value = 0;
 222                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 223                         value |= data[bank->bus_width - 1 - i];
 224
 225                 return value;
 226         }
 227 }
 228
 229 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 230 {
 231         target_t *target = bank->target;
 232         u8 data[CFI_MAX_BUS_WIDTH * 2];
 233
 234         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 235
 236         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 237                 return data[0] | data[bank->bus_width] << 8;
 238         else
 239                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 240 }
 241
 242 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 243 {
 244         target_t *target = bank->target;
 245         u8 data[CFI_MAX_BUS_WIDTH * 4];
 246
 247         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 248
 249         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 250                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 251         else
 252                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 253                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 254 }
 255
 256 void cfi_intel_clear_status_register(flash_bank_t *bank)
 257 {
 258         target_t *target = bank->target;
 259         u8 command[8];
 260
 261         if (target->state != TARGET_HALTED)
 262         {
 263                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 264                 exit(-1);
 265         }
 266
 267         cfi_command(bank, 0x50, command);
 268         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 269 }
 270
 271 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 272 {
 273         u8 status;
 274
 275         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 276         {
 277                 LOG_DEBUG("status: 0x%x", status);
 278                 alive_sleep(1);
 279         }
 280
 281         /* mask out bit 0 (reserved) */
 282         status = status & 0xfe;
 283
 284         LOG_DEBUG("status: 0x%x", status);
 285
 286         if ((status & 0x80) != 0x80)
 287         {
 288                 LOG_ERROR("timeout while waiting for WSM to become ready");
 289         }
 290         else if (status != 0x80)
 291         {
 292                 LOG_ERROR("status register: 0x%x", status);
 293                 if (status & 0x2)
 294                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 295                 if (status & 0x4)
 296                         LOG_ERROR("Program suspended");
 297                 if (status & 0x8)
 298                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 299                 if (status & 0x10)
 300                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 301                 if (status & 0x20)
 302                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 303                 if (status & 0x40)
 304                         LOG_ERROR("Block Erase Suspended");
 305
 306                 cfi_intel_clear_status_register(bank);
 307         }
 308
 309         return status;
 310 }
 311
 312 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 313 {
 314         u8 status, oldstatus;
 315
 316         oldstatus = cfi_get_u8(bank, 0, 0x0);
 317
 318         do {
 319                 status = cfi_get_u8(bank, 0, 0x0);
 320                 if ((status ^ oldstatus) & 0x40) {
 321                         if (status & 0x20) {
 322                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 323                                 status = cfi_get_u8(bank, 0, 0x0);
 324                                 if ((status ^ oldstatus) & 0x40) {
 325                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 326                                         return(ERROR_FLASH_OPERATION_FAILED);
 327                                 } else {
 328                                         LOG_DEBUG("status: 0x%x", status);
 329                                         return(ERROR_OK);
 330                                 }
 331                         }
 332                 } else {
 333                         LOG_DEBUG("status: 0x%x", status);
 334                         return(ERROR_OK);
 335                 }
 336
 337                 oldstatus = status;
 338                 alive_sleep(1);
 339         } while (timeout-- > 0);
 340
 341         LOG_ERROR("timeout, status: 0x%x", status);
 342
 343         return(ERROR_FLASH_BUSY);
 344 }
 345
 346 int cfi_read_intel_pri_ext(flash_bank_t *bank)
 347 {
 348         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 349         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 350         target_t *target = bank->target;
 351         u8 command[8];
 352
 353         cfi_info->pri_ext = pri_ext;
 354
 355         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 356         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 357         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 358
 359         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 360         {
 361                 cfi_command(bank, 0xf0, command);
 362                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 363                 cfi_command(bank, 0xff, command);
 364                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 365                 LOG_ERROR("Could not read bank flash bank information");
 366                 return ERROR_FLASH_BANK_INVALID;
 367         }
 368
 369         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 370         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 371
 372         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 373
 374         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 375         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 376         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 377
 378         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 379
 380         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 381         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 382
 383         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 384                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 385                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 386
 387         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 388         if (pri_ext->num_protection_fields != 1)
 389         {
 390                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 391         }
 392
 393         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 394         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 395         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 396
 397         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 398
 399         return ERROR_OK;
 400 }
 401
 402 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 403 {
 404         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 405         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 406         target_t *target = bank->target;
 407         u8 command[8];
 408
 409         cfi_info->pri_ext = pri_ext;
 410
 411         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 412         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 413         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 414
 415         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 416         {
 417                 cfi_command(bank, 0xf0, command);
 418                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 419                 LOG_ERROR("Could not read spansion bank information");
 420                 return ERROR_FLASH_BANK_INVALID;
 421         }
 422
 423         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 424         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 425
 426         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 427
 428         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 429         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 430         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 431         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 432         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 433         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 434         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 435         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 436         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 437         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 438         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 439
 440         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 441               pri_ext->EraseSuspend, pri_ext->BlkProt);
 442
 443         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 444               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 445
 446         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 447
 448
 449         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 450                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 451                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 452
 453         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 454
 455         /* default values for implementation specific workarounds */
 456         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 457         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 458         pri_ext->_reversed_geometry = 0;
 459
 460         return ERROR_OK;
 461 }
 462
 463 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 464 {
 465         cfi_atmel_pri_ext_t atmel_pri_ext;
 466         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 467         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 468         target_t *target = bank->target;
 469         u8 command[8];
 470
 471         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 472          * but a different primary extended query table.
 473          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 474          */
 475
 476         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 477
 478         cfi_info->pri_ext = pri_ext;
 479
 480         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 481         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 482         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 483
 484         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 485         {
 486                 cfi_command(bank, 0xf0, command);
 487                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 488                 LOG_ERROR("Could not read atmel bank information");
 489                 return ERROR_FLASH_BANK_INVALID;
 490         }
 491
 492         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 493         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 494         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 495
 496         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 497         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 498
 499         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 500
 501         pri_ext->major_version = atmel_pri_ext.major_version;
 502         pri_ext->minor_version = atmel_pri_ext.minor_version;
 503
 504         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 505         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 506         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 507         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 508
 509         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 510                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 511
 512         if (atmel_pri_ext.features & 0x02)
 513                 pri_ext->EraseSuspend = 2;
 514
 515         if (atmel_pri_ext.bottom_boot)
 516                 pri_ext->TopBottom = 2;
 517         else
 518                 pri_ext->TopBottom = 3;
 519
 520         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 521         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 522
 523         return ERROR_OK;
 524 }
 525
 526 int cfi_read_0002_pri_ext(flash_bank_t *bank)
 527 {
 528         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 529
 530         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 531         {
 532                 return cfi_read_atmel_pri_ext(bank);
 533         }
 534         else
 535         {
 536                 return cfi_read_spansion_pri_ext(bank);
 537         }
 538 }
 539
 540 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 541 {
 542         int printed;
 543         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 544         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 545
 546         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 547         buf += printed;
 548         buf_size -= printed;
 549
 550         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 551                            pri_ext->pri[1], pri_ext->pri[2],
 552                            pri_ext->major_version, pri_ext->minor_version);
 553         buf += printed;
 554         buf_size -= printed;
 555
 556         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 557                            (pri_ext->SiliconRevision) >> 2,
 558                            (pri_ext->SiliconRevision) & 0x03);
 559         buf += printed;
 560         buf_size -= printed;
 561
 562         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 563                            pri_ext->EraseSuspend,
 564                            pri_ext->BlkProt);
 565         buf += printed;
 566         buf_size -= printed;
 567
 568         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 569                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 570                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 571
 572         return ERROR_OK;
 573 }
 574
 575 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 576 {
 577         int printed;
 578         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 579         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 580
 581         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 582         buf += printed;
 583         buf_size -= printed;
 584
 585         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 586         buf += printed;
 587         buf_size -= printed;
 588
 589         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 590         buf += printed;
 591         buf_size -= printed;
 592
 593         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 594                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 595                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 596         buf += printed;
 597         buf_size -= printed;
 598
 599         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 600
 601         return ERROR_OK;
 602 }
 603
 604 int cfi_register_commands(struct command_context_s *cmd_ctx)
 605 {
 606         /*command_t *cfi_cmd = */
 607         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 608         /*
 609         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 610                                          "print part id of cfi flash bank <num>");
 611         */
 612         return ERROR_OK;
 613 }
 614
 615 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 616  */
 617 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 618 {
 619         cfi_flash_bank_t *cfi_info;
 620         int i;
 621
 622         if (argc < 6)
 623         {
 624                 LOG_WARNING("incomplete flash_bank cfi configuration");
 625                 return ERROR_FLASH_BANK_INVALID;
 626         }
 627
 628         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 629                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 630         {
 631                 LOG_ERROR("chip and bus width have to specified in bytes");
 632                 return ERROR_FLASH_BANK_INVALID;
 633         }
 634
 635         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 636         cfi_info->probed = 0;
 637         bank->driver_priv = cfi_info;
 638
 639         cfi_info->write_algorithm = NULL;
 640
 641         cfi_info->x16_as_x8 = 0;
 642         cfi_info->jedec_probe = 0;
 643         cfi_info->not_cfi = 0;
 644
 645         for (i = 6; i < argc; i++)
 646         {
 647                 if (strcmp(args[i], "x16_as_x8") == 0)
 648                 {
 649                         cfi_info->x16_as_x8 = 1;
 650                 }
 651                 else if (strcmp(args[i], "jedec_probe") == 0)
 652                 {
 653                         cfi_info->jedec_probe = 1;
 654                 }
 655         }
 656
 657         cfi_info->write_algorithm = NULL;
 658
 659         /* bank wasn't probed yet */
 660         cfi_info->qry[0] = -1;
 661
 662         return ERROR_OK;
 663 }
 664
 665 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 666 {
 667         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 668         target_t *target = bank->target;
 669         u8 command[8];
 670         int i;
 671
 672         cfi_intel_clear_status_register(bank);
 673
 674         for (i = first; i <= last; i++)
 675         {
 676                 cfi_command(bank, 0x20, command);
 677                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 678
 679                 cfi_command(bank, 0xd0, command);
 680                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 681
 682                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 683                         bank->sectors[i].is_erased = 1;
 684                 else
 685                 {
 686                         cfi_command(bank, 0xff, command);
 687                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 688
 689                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 690                         return ERROR_FLASH_OPERATION_FAILED;
 691                 }
 692         }
 693
 694         cfi_command(bank, 0xff, command);
 695         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 696
 697         return ERROR_OK;
 698 }
 699
 700 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 701 {
 702         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 703         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 704         target_t *target = bank->target;
 705         u8 command[8];
 706         int i;
 707
 708         for (i = first; i <= last; i++)
 709         {
 710                 cfi_command(bank, 0xaa, command);
 711                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 712
 713                 cfi_command(bank, 0x55, command);
 714                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 715
 716                 cfi_command(bank, 0x80, command);
 717                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 718
 719                 cfi_command(bank, 0xaa, command);
 720                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 721
 722                 cfi_command(bank, 0x55, command);
 723                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 724
 725                 cfi_command(bank, 0x30, command);
 726                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 727
 728                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 729                         bank->sectors[i].is_erased = 1;
 730                 else
 731                 {
 732                         cfi_command(bank, 0xf0, command);
 733                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 734
 735                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 736                         return ERROR_FLASH_OPERATION_FAILED;
 737                 }
 738         }
 739
 740         cfi_command(bank, 0xf0, command);
 741         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 742
 743         return ERROR_OK;
 744 }
 745
 746 int cfi_erase(struct flash_bank_s *bank, int first, int last)
 747 {
 748         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 749
 750         if (bank->target->state != TARGET_HALTED)
 751         {
 752                 LOG_ERROR("Target not halted");
 753                 return ERROR_TARGET_NOT_HALTED;
 754         }
 755
 756         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 757         {
 758                 return ERROR_FLASH_SECTOR_INVALID;
 759         }
 760
 761         if (cfi_info->qry[0] != 'Q')
 762                 return ERROR_FLASH_BANK_NOT_PROBED;
 763
 764         switch(cfi_info->pri_id)
 765         {
 766                 case 1:
 767                 case 3:
 768                         return cfi_intel_erase(bank, first, last);
 769                         break;
 770                 case 2:
 771                         return cfi_spansion_erase(bank, first, last);
 772                         break;
 773                 default:
 774                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 775                         break;
 776         }
 777
 778         return ERROR_OK;
 779 }
 780
 781 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 782 {
 783         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 784         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 785         target_t *target = bank->target;
 786         u8 command[8];
 787         int retry = 0;
 788         int i;
 789
 790         /* if the device supports neither legacy lock/unlock (bit 3) nor
 791          * instant individual block locking (bit 5).
 792          */
 793         if (!(pri_ext->feature_support & 0x28))
 794                 return ERROR_FLASH_OPERATION_FAILED;
 795
 796         cfi_intel_clear_status_register(bank);
 797
 798         for (i = first; i <= last; i++)
 799         {
 800                 cfi_command(bank, 0x60, command);
 801                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 802                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 803                 if (set)
 804                 {
 805                         cfi_command(bank, 0x01, command);
 806                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 807                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 808                         bank->sectors[i].is_protected = 1;
 809                 }
 810                 else
 811                 {
 812                         cfi_command(bank, 0xd0, command);
 813                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 814                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 815                         bank->sectors[i].is_protected = 0;
 816                 }
 817
 818                 /* instant individual block locking doesn't require reading of the status register */
 819                 if (!(pri_ext->feature_support & 0x20))
 820                 {
 821                         /* Clear lock bits operation may take up to 1.4s */
 822                         cfi_intel_wait_status_busy(bank, 1400);
 823                 }
 824                 else
 825                 {
 826                         u8 block_status;
 827                         /* read block lock bit, to verify status */
 828                         cfi_command(bank, 0x90, command);
 829                         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 830                         block_status = cfi_get_u8(bank, i, 0x2);
 831
 832                         if ((block_status & 0x1) != set)
 833                         {
 834                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 835                                 cfi_command(bank, 0x70, command);
 836                                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 837                                 cfi_intel_wait_status_busy(bank, 10);
 838
 839                                 if (retry > 10)
 840                                         return ERROR_FLASH_OPERATION_FAILED;
 841                                 else
 842                                 {
 843                                         i--;
 844                                         retry++;
 845                                 }
 846                         }
 847                 }
 848         }
 849
 850         /* if the device doesn't support individual block lock bits set/clear,
 851          * all blocks have been unlocked in parallel, so we set those that should be protected
 852          */
 853         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 854         {
 855                 for (i = 0; i < bank->num_sectors; i++)
 856                 {
 857                         if (bank->sectors[i].is_protected == 1)
 858                         {
 859                                 cfi_intel_clear_status_register(bank);
 860
 861                                 cfi_command(bank, 0x60, command);
 862                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 863
 864                                 cfi_command(bank, 0x01, command);
 865                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 866
 867                                 cfi_intel_wait_status_busy(bank, 100);
 868                         }
 869                 }
 870         }
 871
 872         cfi_command(bank, 0xff, command);
 873         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 874
 875         return ERROR_OK;
 876 }
 877
 878 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 879 {
 880         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 881
 882         if (bank->target->state != TARGET_HALTED)
 883         {
 884                 LOG_ERROR("Target not halted");
 885                 return ERROR_TARGET_NOT_HALTED;
 886         }
 887
 888         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 889         {
 890                 return ERROR_FLASH_SECTOR_INVALID;
 891         }
 892
 893         if (cfi_info->qry[0] != 'Q')
 894                 return ERROR_FLASH_BANK_NOT_PROBED;
 895
 896         switch(cfi_info->pri_id)
 897         {
 898                 case 1:
 899                 case 3:
 900                         cfi_intel_protect(bank, set, first, last);
 901                         break;
 902                 default:
 903                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 904                         break;
 905         }
 906
 907         return ERROR_OK;
 908 }
 909
 910 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 911 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 912 {
 913         /* target_t *target = bank->target; */
 914
 915         int i;
 916
 917         /* NOTE:
 918          * The data to flash must not be changed in endian! We write a bytestrem in
 919          * target byte order already. Only the control and status byte lane of the flash
 920          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 921          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 922          */
 923
 924 #if 0
 925         if (target->endianness == TARGET_LITTLE_ENDIAN)
 926         {
 927 #endif
 928                 /* shift bytes */
 929                 for (i = 0; i < bank->bus_width - 1; i++)
 930                         word[i] = word[i + 1];
 931                 word[bank->bus_width - 1] = byte;
 932 #if 0
 933         }
 934         else
 935         {
 936                 /* shift bytes */
 937                 for (i = bank->bus_width - 1; i > 0; i--)
 938                         word[i] = word[i - 1];
 939                 word[0] = byte;
 940         }
 941 #endif
 942 }
 943
 944 /* Convert code image to target endian */
 945 /* FIXME create general block conversion fcts in target.c?) */
 946 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 947 {
 948         u32 i;
 949         for (i=0; i< count; i++)
 950         {
 951                 target_buffer_set_u32(target, dest, *src);
 952                 dest+=4;
 953                 src++;
 954         }
 955 }
 956
 957 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
 958 {
 959         target_t *target = bank->target;
 960
 961         u8 buf[CFI_MAX_BUS_WIDTH];
 962         cfi_command(bank, cmd, buf);
 963         switch (bank->bus_width)
 964         {
 965         case 1 :
 966                 return buf[0];
 967                 break;
 968         case 2 :
 969                 return target_buffer_get_u16(target, buf);
 970                 break;
 971         case 4 :
 972                 return target_buffer_get_u32(target, buf);
 973                 break;
 974         default :
 975                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
 976                 return 0;
 977         }
 978 }
 979
 980 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
 981 {
 982         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 983         target_t *target = bank->target;
 984         reg_param_t reg_params[7];
 985         armv4_5_algorithm_t armv4_5_info;
 986         working_area_t *source;
 987         u32 buffer_size = 32768;
 988         u32 write_command_val, busy_pattern_val, error_pattern_val;
 989
 990         /* algorithm register usage:
 991          * r0: source address (in RAM)
 992          * r1: target address (in Flash)
 993          * r2: count
 994          * r3: flash write command
 995          * r4: status byte (returned to host)
 996          * r5: busy test pattern
 997          * r6: error test pattern
 998          */
 999
1000         static const u32 word_32_code[] = {
1001                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1002                 0xe5813000,   /*                str r3, [r1] */
1003                 0xe5814000,   /*                str r4, [r1] */
1004                 0xe5914000,   /* busy:  ldr r4, [r1] */
1005                 0xe0047005,   /*                and r7, r4, r5 */
1006                 0xe1570005,   /*                cmp r7, r5 */
1007                 0x1afffffb,   /*                bne busy */
1008                 0xe1140006,   /*                tst r4, r6 */
1009                 0x1a000003,   /*                bne done */
1010                 0xe2522001,   /*                subs r2, r2, #1 */
1011                 0x0a000001,   /*                beq done */
1012                 0xe2811004,   /*                add r1, r1 #4 */
1013                 0xeafffff2,   /*                b loop */
1014                 0xeafffffe    /* done:  b -2 */
1015         };
1016
1017         static const u32 word_16_code[] = {
1018                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1019                 0xe1c130b0,   /*                strh r3, [r1] */
1020                 0xe1c140b0,   /*                strh r4, [r1] */
1021                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1022                 0xe0047005,   /*                and r7, r4, r5 */
1023                 0xe1570005,   /*                cmp r7, r5 */
1024                 0x1afffffb,   /*                bne busy */
1025                 0xe1140006,   /*                tst r4, r6 */
1026                 0x1a000003,   /*                bne done */
1027                 0xe2522001,   /*                subs r2, r2, #1 */
1028                 0x0a000001,   /*                beq done */
1029                 0xe2811002,   /*                add r1, r1 #2 */
1030                 0xeafffff2,   /*                b loop */
1031                 0xeafffffe    /* done:  b -2 */
1032         };
1033
1034         static const u32 word_8_code[] = {
1035                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1036                 0xe5c13000,   /*                strb r3, [r1] */
1037                 0xe5c14000,   /*                strb r4, [r1] */
1038                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1039                 0xe0047005,   /*                and r7, r4, r5 */
1040                 0xe1570005,   /*                cmp r7, r5 */
1041                 0x1afffffb,   /*                bne busy */
1042                 0xe1140006,   /*                tst r4, r6 */
1043                 0x1a000003,   /*                bne done */
1044                 0xe2522001,   /*                subs r2, r2, #1 */
1045                 0x0a000001,   /*                beq done */
1046                 0xe2811001,   /*                add r1, r1 #1 */
1047                 0xeafffff2,   /*                b loop */
1048                 0xeafffffe    /* done:  b -2 */
1049         };
1050         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1051         const u32 *target_code_src;
1052         int target_code_size;
1053         int retval = ERROR_OK;
1054
1055
1056         cfi_intel_clear_status_register(bank);
1057
1058         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1059         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1060         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1061
1062         /* If we are setting up the write_algorith, we need target_code_src */
1063         /* if not we only need target_code_size.                                                                                                                */
1064         /*                                                                                                                                                                                                                                                                      */
1065         /* However, we don't want to create multiple code paths, so we                  */
1066         /* do the unecessary evaluation of target_code_src, which the                   */
1067         /* compiler will probably nicely optimize away if not needed                            */
1068
1069         /* prepare algorithm code for target endian */
1070         switch (bank->bus_width)
1071         {
1072         case 1 :
1073                 target_code_src = word_8_code;
1074                 target_code_size = sizeof(word_8_code);
1075                 break;
1076         case 2 :
1077                 target_code_src = word_16_code;
1078                 target_code_size = sizeof(word_16_code);
1079                 break;
1080         case 4 :
1081                 target_code_src = word_32_code;
1082                 target_code_size = sizeof(word_32_code);
1083                 break;
1084         default:
1085                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1086                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1087         }
1088
1089         /* flash write code */
1090         if (!cfi_info->write_algorithm)
1091         {
1092                 if ( target_code_size > sizeof(target_code) )
1093                 {
1094                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1095                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1096                 }
1097                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1098
1099                 /* Get memory for block write handler */
1100                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1101                 if (retval != ERROR_OK)
1102                 {
1103                         LOG_WARNING("No working area available, can't do block memory writes");
1104                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1105                 };
1106
1107                 /* write algorithm code to working area */
1108                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1109                 if (retval != ERROR_OK)
1110                 {
1111                         LOG_ERROR("Unable to write block write code to target");
1112                         goto cleanup;
1113                 }
1114         }
1115
1116         /* Get a workspace buffer for the data to flash starting with 32k size.
1117            Half size until buffer would be smaller 256 Bytem then fail back */
1118         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1119         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1120         {
1121                 buffer_size /= 2;
1122                 if (buffer_size <= 256)
1123                 {
1124                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1125                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126                         goto cleanup;
1127                 }
1128         };
1129
1130         /* setup algo registers */
1131         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1132         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1133         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1134         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1135         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1136         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1137         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1138
1139         /* prepare command and status register patterns */
1140         write_command_val = cfi_command_val(bank, 0x40);
1141         busy_pattern_val  = cfi_command_val(bank, 0x80);
1142         error_pattern_val = cfi_command_val(bank, 0x7e);
1143
1144         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1145
1146         /* Programming main loop */
1147         while (count > 0)
1148         {
1149                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1150                 u32 wsm_error;
1151
1152                 target_write_buffer(target, source->address, thisrun_count, buffer);
1153
1154                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1155                 buf_set_u32(reg_params[1].value, 0, 32, address);
1156                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1157
1158                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1159                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1160                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1161
1162                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1163
1164                 /* Execute algorithm, assume breakpoint for last instruction */
1165                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1166                         cfi_info->write_algorithm->address,
1167                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1168                         10000, /* 10s should be enough for max. 32k of data */
1169                         &armv4_5_info);
1170
1171                 /* On failure try a fall back to direct word writes */
1172                 if (retval != ERROR_OK)
1173                 {
1174                         cfi_intel_clear_status_register(bank);
1175                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1176                         retval = ERROR_FLASH_OPERATION_FAILED;
1177                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1178                         /* FIXME To allow fall back or recovery, we must save the actual status
1179                            somewhere, so that a higher level code can start recovery. */
1180                         goto cleanup;
1181                 }
1182
1183                 /* Check return value from algo code */
1184                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1185                 if (wsm_error)
1186                 {
1187                         /* read status register (outputs debug inforation) */
1188                         cfi_intel_wait_status_busy(bank, 100);
1189                         cfi_intel_clear_status_register(bank);
1190                         retval = ERROR_FLASH_OPERATION_FAILED;
1191                         goto cleanup;
1192                 }
1193
1194                 buffer += thisrun_count;
1195                 address += thisrun_count;
1196                 count -= thisrun_count;
1197         }
1198
1199         /* free up resources */
1200 cleanup:
1201         if (source)
1202                 target_free_working_area(target, source);
1203
1204         if (cfi_info->write_algorithm)
1205         {
1206                 target_free_working_area(target, cfi_info->write_algorithm);
1207                 cfi_info->write_algorithm = NULL;
1208         }
1209
1210         destroy_reg_param(&reg_params[0]);
1211         destroy_reg_param(&reg_params[1]);
1212         destroy_reg_param(&reg_params[2]);
1213         destroy_reg_param(&reg_params[3]);
1214         destroy_reg_param(&reg_params[4]);
1215         destroy_reg_param(&reg_params[5]);
1216         destroy_reg_param(&reg_params[6]);
1217
1218         return retval;
1219 }
1220
1221 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1222 {
1223         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1224         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1225         target_t *target = bank->target;
1226         reg_param_t reg_params[10];
1227         armv4_5_algorithm_t armv4_5_info;
1228         working_area_t *source;
1229         u32 buffer_size = 32768;
1230         u32 status;
1231         int retval;
1232         int exit_code = ERROR_OK;
1233
1234         /* input parameters - */
1235         /*      R0 = source address */
1236         /*      R1 = destination address */
1237         /*      R2 = number of writes */
1238         /*      R3 = flash write command */
1239         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1240         /* output parameters - */
1241         /*      R5 = 0x80 ok 0x00 bad */
1242         /* temp registers - */
1243         /*      R6 = value read from flash to test status */
1244         /*      R7 = holding register */
1245         /* unlock registers - */
1246         /*  R8 = unlock1_addr */
1247         /*  R9 = unlock1_cmd */
1248         /*  R10 = unlock2_addr */
1249         /*  R11 = unlock2_cmd */
1250
1251         static const u32 word_32_code[] = {
1252                                                 /* 00008100 <sp_32_code>:               */
1253                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1254                 0xe5889000,     /* str  r9, [r8]                                */
1255                 0xe58ab000,     /* str  r11, [r10]                              */
1256                 0xe5883000,     /* str  r3, [r8]                                */
1257                 0xe5815000,     /* str  r5, [r1]                                */
1258                 0xe1a00000,     /* nop                                                  */
1259                                                 /*                                                              */
1260                                                 /* 00008110 <sp_32_busy>:               */
1261                 0xe5916000,     /* ldr  r6, [r1]                                */
1262                 0xe0257006,     /* eor  r7, r5, r6                              */
1263                 0xe0147007,     /* ands r7, r4, r7                              */
1264                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1265                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1266                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1267                 0xe5916000,     /* ldr  r6, [r1]                                */
1268                 0xe0257006,     /* eor  r7, r5, r6                              */
1269                 0xe0147007,     /* ands r7, r4, r7                              */
1270                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1271                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1272                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1273                                                 /*                                                              */
1274                                 /* 00008140 <sp_32_cont>:                               */
1275                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1276                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1277                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1278                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1279                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1280                                                 /*                                                              */
1281                                                 /* 00008154 <sp_32_done>:               */
1282                 0xeafffffe              /* b    8154 <sp_32_done>               */
1283                 };
1284
1285                 static const u32 word_16_code[] = {
1286                                 /* 00008158 <sp_16_code>:              */
1287                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1288                 0xe1c890b0,     /* strh r9, [r8]                                */
1289                 0xe1cab0b0,     /* strh r11, [r10]                              */
1290                 0xe1c830b0,     /* strh r3, [r8]                                */
1291                 0xe1c150b0,     /* strh r5, [r1]                       */
1292                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1293                                 /*                                     */
1294                                 /* 00008168 <sp_16_busy>:              */
1295                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1296                 0xe0257006,     /* eor  r7, r5, r6                     */
1297                 0xe0147007,     /* ands r7, r4, r7                     */
1298                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1299                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1300                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1301                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1302                 0xe0257006,     /* eor  r7, r5, r6                     */
1303                 0xe0147007,     /* ands r7, r4, r7                     */
1304                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1305                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1306                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1307                                 /*                                     */
1308                                 /* 00008198 <sp_16_cont>:              */
1309                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1310                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1311                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1312                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1313                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1314                                 /*                                     */
1315                                 /* 000081ac <sp_16_done>:              */
1316                 0xeafffffe      /* b    81ac <sp_16_done>              */
1317                 };
1318
1319                 static const u32 word_8_code[] = {
1320                                 /* 000081b0 <sp_16_code_end>:          */
1321                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1322                 0xe5c89000,     /* strb r9, [r8]                                */
1323                 0xe5cab000,     /* strb r11, [r10]                              */
1324                 0xe5c83000,     /* strb r3, [r8]                                */
1325                 0xe5c15000,     /* strb r5, [r1]                       */
1326                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1327                                 /*                                     */
1328                                 /* 000081c0 <sp_8_busy>:               */
1329                 0xe5d16000,     /* ldrb r6, [r1]                       */
1330                 0xe0257006,     /* eor  r7, r5, r6                     */
1331                 0xe0147007,     /* ands r7, r4, r7                     */
1332                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1333                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1334                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1335                 0xe5d16000,     /* ldrb r6, [r1]                       */
1336                 0xe0257006,     /* eor  r7, r5, r6                     */
1337                 0xe0147007,     /* ands r7, r4, r7                     */
1338                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1339                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1340                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1341                                 /*                                     */
1342                                 /* 000081f0 <sp_8_cont>:               */
1343                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1344                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1345                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1346                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1347                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1348                                 /*                                     */
1349                                 /* 00008204 <sp_8_done>:               */
1350                 0xeafffffe      /* b    8204 <sp_8_done>               */
1351         };
1352
1353         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1354         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1355         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1356
1357         /* flash write code */
1358         if (!cfi_info->write_algorithm)
1359         {
1360                 u8 *target_code;
1361                 int target_code_size;
1362                 const u32 *src;
1363
1364                 /* convert bus-width dependent algorithm code to correct endiannes */
1365                 switch (bank->bus_width)
1366                 {
1367                 case 1:
1368                         src = word_8_code;
1369                         target_code_size = sizeof(word_8_code);
1370                         break;
1371                 case 2:
1372                         src = word_16_code;
1373                         target_code_size = sizeof(word_16_code);
1374                         break;
1375                 case 4:
1376                         src = word_32_code;
1377                         target_code_size = sizeof(word_32_code);
1378                         break;
1379                 default:
1380                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1381                         return ERROR_FLASH_OPERATION_FAILED;
1382                 }
1383                 target_code = malloc(target_code_size);
1384                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1385
1386                 /* allocate working area */
1387                 retval=target_alloc_working_area(target, target_code_size,
1388                                 &cfi_info->write_algorithm);
1389                 if (retval != ERROR_OK)
1390                         return retval;
1391
1392                 /* write algorithm code to working area */
1393                 target_write_buffer(target, cfi_info->write_algorithm->address,
1394                                     target_code_size, target_code);
1395
1396                 free(target_code);
1397         }
1398         /* the following code still assumes target code is fixed 24*4 bytes */
1399
1400         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1401         {
1402                 buffer_size /= 2;
1403                 if (buffer_size <= 256)
1404                 {
1405                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1406                         if (cfi_info->write_algorithm)
1407                                 target_free_working_area(target, cfi_info->write_algorithm);
1408
1409                         LOG_WARNING("not enough working area available, can't do block memory writes");
1410                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1411                 }
1412         };
1413
1414         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1415         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1416         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1417         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1418         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1419         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1420         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1421         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1422         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1423         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1424
1425         while (count > 0)
1426         {
1427                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1428
1429                 target_write_buffer(target, source->address, thisrun_count, buffer);
1430
1431                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1432                 buf_set_u32(reg_params[1].value, 0, 32, address);
1433                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1434                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1435                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1436                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1437                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1438                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1439                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1440
1441                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1442                                                      cfi_info->write_algorithm->address,
1443                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1444                                                      10000, &armv4_5_info);
1445
1446                 status = buf_get_u32(reg_params[5].value, 0, 32);
1447
1448                 if ((retval != ERROR_OK) || status != 0x80)
1449                 {
1450                         LOG_DEBUG("status: 0x%x", status);
1451                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1452                         break;
1453                 }
1454
1455                 buffer += thisrun_count;
1456                 address += thisrun_count;
1457                 count -= thisrun_count;
1458         }
1459
1460         target_free_working_area(target, source);
1461
1462         destroy_reg_param(&reg_params[0]);
1463         destroy_reg_param(&reg_params[1]);
1464         destroy_reg_param(&reg_params[2]);
1465         destroy_reg_param(&reg_params[3]);
1466         destroy_reg_param(&reg_params[4]);
1467         destroy_reg_param(&reg_params[5]);
1468         destroy_reg_param(&reg_params[6]);
1469         destroy_reg_param(&reg_params[7]);
1470         destroy_reg_param(&reg_params[8]);
1471         destroy_reg_param(&reg_params[9]);
1472
1473         return exit_code;
1474 }
1475
1476 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1477 {
1478         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1479         target_t *target = bank->target;
1480         u8 command[8];
1481
1482         cfi_intel_clear_status_register(bank);
1483         cfi_command(bank, 0x40, command);
1484         target->type->write_memory(target, address, bank->bus_width, 1, command);
1485
1486         target->type->write_memory(target, address, bank->bus_width, 1, word);
1487
1488         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1489         {
1490                 cfi_command(bank, 0xff, command);
1491                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1492
1493                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1494                 return ERROR_FLASH_OPERATION_FAILED;
1495         }
1496
1497         return ERROR_OK;
1498 }
1499
1500 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1501 {
1502         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1503         target_t *target = bank->target;
1504         u8 command[8];
1505
1506         /* Calculate buffer size and boundary mask */
1507         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1508         u32 buffermask = buffersize-1;
1509         u32 bufferwsize;
1510
1511         /* Check for valid range */
1512         if (address & buffermask)
1513         {
1514                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1515                 return ERROR_FLASH_OPERATION_FAILED;
1516         }
1517         switch(bank->chip_width)
1518         {
1519         case 4 : bufferwsize = buffersize / 4; break;
1520         case 2 : bufferwsize = buffersize / 2; break;
1521         case 1 : bufferwsize = buffersize; break;
1522         default:
1523                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1524                 return ERROR_FLASH_OPERATION_FAILED;
1525         }
1526
1527         /* Check for valid size */
1528         if (wordcount > bufferwsize)
1529         {
1530                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1531                 return ERROR_FLASH_OPERATION_FAILED;
1532         }
1533
1534         /* Write to flash buffer */
1535         cfi_intel_clear_status_register(bank);
1536
1537         /* Initiate buffer operation _*/
1538         cfi_command(bank, 0xE8, command);
1539         target->type->write_memory(target, address, bank->bus_width, 1, command);
1540         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1541         {
1542                 cfi_command(bank, 0xff, command);
1543                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1544
1545                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1546                 return ERROR_FLASH_OPERATION_FAILED;
1547         }
1548
1549         /* Write buffer wordcount-1 and data words */
1550         cfi_command(bank, bufferwsize-1, command);
1551         target->type->write_memory(target, address, bank->bus_width, 1, command);
1552
1553         target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1554
1555         /* Commit write operation */
1556         cfi_command(bank, 0xd0, command);
1557         target->type->write_memory(target, address, bank->bus_width, 1, command);
1558         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1559         {
1560                 cfi_command(bank, 0xff, command);
1561                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1562
1563                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1564                 return ERROR_FLASH_OPERATION_FAILED;
1565         }
1566
1567         return ERROR_OK;
1568 }
1569
1570 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1571 {
1572         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1573         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1574         target_t *target = bank->target;
1575         u8 command[8];
1576
1577         cfi_command(bank, 0xaa, command);
1578         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1579
1580         cfi_command(bank, 0x55, command);
1581         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1582
1583         cfi_command(bank, 0xa0, command);
1584         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1585
1586         target->type->write_memory(target, address, bank->bus_width, 1, word);
1587
1588         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1589         {
1590                 cfi_command(bank, 0xf0, command);
1591                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1592
1593                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1594                 return ERROR_FLASH_OPERATION_FAILED;
1595         }
1596
1597         return ERROR_OK;
1598 }
1599
1600 int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1601 {
1602         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1603         target_t *target = bank->target;
1604         u8 command[8];
1605         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1606
1607         /* Calculate buffer size and boundary mask */
1608         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1609         u32 buffermask = buffersize-1;
1610         u32 bufferwsize;
1611
1612         /* Check for valid range */
1613         if (address & buffermask)
1614         {
1615                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1616                 return ERROR_FLASH_OPERATION_FAILED;
1617         }
1618         switch(bank->chip_width)
1619         {
1620         case 4 : bufferwsize = buffersize / 4; break;
1621         case 2 : bufferwsize = buffersize / 2; break;
1622         case 1 : bufferwsize = buffersize; break;
1623         default:
1624                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1625                 return ERROR_FLASH_OPERATION_FAILED;
1626         }
1627
1628         /* Check for valid size */
1629         if (wordcount > bufferwsize)
1630         {
1631                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1632                 return ERROR_FLASH_OPERATION_FAILED;
1633         }
1634
1635         // Unlock
1636         cfi_command(bank, 0xaa, command);
1637         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1638
1639         cfi_command(bank, 0x55, command);
1640         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1641
1642         // Buffer load command
1643         cfi_command(bank, 0x25, command);
1644         target->type->write_memory(target, address, bank->bus_width, 1, command);
1645
1646         /* Write buffer wordcount-1 and data words */
1647         cfi_command(bank, bufferwsize-1, command);
1648         target->type->write_memory(target, address, bank->bus_width, 1, command);
1649
1650         target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1651
1652         /* Commit write operation */
1653         cfi_command(bank, 0x29, command);
1654         target->type->write_memory(target, address, bank->bus_width, 1, command);
1655
1656         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1657         {
1658                 cfi_command(bank, 0xf0, command);
1659                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1660
1661                 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1662                 return ERROR_FLASH_OPERATION_FAILED;
1663         }
1664
1665         return ERROR_OK;
1666 }
1667
1668 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1669 {
1670         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1671
1672         switch(cfi_info->pri_id)
1673         {
1674                 case 1:
1675                 case 3:
1676                         return cfi_intel_write_word(bank, word, address);
1677                         break;
1678                 case 2:
1679                         return cfi_spansion_write_word(bank, word, address);
1680                         break;
1681                 default:
1682                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1683                         break;
1684         }
1685
1686         return ERROR_FLASH_OPERATION_FAILED;
1687 }
1688
1689 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1690 {
1691         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1692
1693         switch(cfi_info->pri_id)
1694         {
1695                 case 1:
1696                 case 3:
1697                         return cfi_intel_write_words(bank, word, wordcount, address);
1698                         break;
1699                 case 2:
1700                         return cfi_spansion_write_words(bank, word, wordcount, address);
1701                         break;
1702                 default:
1703                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1704                         break;
1705         }
1706
1707         return ERROR_FLASH_OPERATION_FAILED;
1708 }
1709
1710 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1711 {
1712         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1713         target_t *target = bank->target;
1714         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1715         u32 write_p, copy_p;
1716         int align;      /* number of unaligned bytes */
1717         int blk_count; /* number of bus_width bytes for block copy */
1718         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1719         int i;
1720         int retval;
1721
1722         if (bank->target->state != TARGET_HALTED)
1723         {
1724                 LOG_ERROR("Target not halted");
1725                 return ERROR_TARGET_NOT_HALTED;
1726         }
1727
1728         if (offset + count > bank->size)
1729                 return ERROR_FLASH_DST_OUT_OF_BANK;
1730
1731         if (cfi_info->qry[0] != 'Q')
1732                 return ERROR_FLASH_BANK_NOT_PROBED;
1733
1734         /* start at the first byte of the first word (bus_width size) */
1735         write_p = address & ~(bank->bus_width - 1);
1736         if ((align = address - write_p) != 0)
1737         {
1738                 LOG_INFO("Fixup %d unaligned head bytes", align );
1739
1740                 for (i = 0; i < bank->bus_width; i++)
1741                         current_word[i] = 0;
1742                 copy_p = write_p;
1743
1744                 /* copy bytes before the first write address */
1745                 for (i = 0; i < align; ++i, ++copy_p)
1746                 {
1747                         u8 byte;
1748                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1749                         cfi_add_byte(bank, current_word, byte);
1750                 }
1751
1752                 /* add bytes from the buffer */
1753                 for (; (i < bank->bus_width) && (count > 0); i++)
1754                 {
1755                         cfi_add_byte(bank, current_word, *buffer++);
1756                         count--;
1757                         copy_p++;
1758                 }
1759
1760                 /* if the buffer is already finished, copy bytes after the last write address */
1761                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1762                 {
1763                         u8 byte;
1764                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1765                         cfi_add_byte(bank, current_word, byte);
1766                 }
1767
1768                 retval = cfi_write_word(bank, current_word, write_p);
1769                 if (retval != ERROR_OK)
1770                         return retval;
1771                 write_p = copy_p;
1772         }
1773
1774         /* handle blocks of bus_size aligned bytes */
1775         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1776         switch(cfi_info->pri_id)
1777         {
1778                 /* try block writes (fails without working area) */
1779                 case 1:
1780                 case 3:
1781                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1782                         break;
1783                 case 2:
1784                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1785                         break;
1786                 default:
1787                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1788                         retval = ERROR_FLASH_OPERATION_FAILED;
1789                         break;
1790         }
1791         if (retval == ERROR_OK)
1792         {
1793                 /* Increment pointers and decrease count on succesful block write */
1794                 buffer += blk_count;
1795                 write_p += blk_count;
1796                 count -= blk_count;
1797         }
1798         else
1799         {
1800                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1801                 {
1802                         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1803                         u32 buffermask = buffersize-1;
1804                         u32 bufferwsize;
1805
1806                         switch(bank->chip_width)
1807                         {
1808                         case 4 : bufferwsize = buffersize / 4; break;
1809                         case 2 : bufferwsize = buffersize / 2; break;
1810                         case 1 : bufferwsize = buffersize; break;
1811                         default:
1812                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1813                                 return ERROR_FLASH_OPERATION_FAILED;
1814                         }
1815
1816                         /* fall back to memory writes */
1817                         while (count >= bank->bus_width)
1818                         {
1819                                 int fallback;
1820                                 if ((write_p & 0xff) == 0)
1821                                 {
1822                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1823                                 }
1824                                 fallback = 1;
1825                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1826                                 {
1827                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1828                                         if (retval == ERROR_OK)
1829                                         {
1830                                                 buffer += buffersize;
1831                                                 write_p += buffersize;
1832                                                 count -= buffersize;
1833                                                 fallback=0;
1834                                         }
1835                                 }
1836                                 /* try the slow way? */
1837                                 if (fallback)
1838                                 {
1839                                         for (i = 0; i < bank->bus_width; i++)
1840                                                 current_word[i] = 0;
1841
1842                                         for (i = 0; i < bank->bus_width; i++)
1843                                         {
1844                                                 cfi_add_byte(bank, current_word, *buffer++);
1845                                         }
1846
1847                                         retval = cfi_write_word(bank, current_word, write_p);
1848                                         if (retval != ERROR_OK)
1849                                                 return retval;
1850
1851                                         write_p += bank->bus_width;
1852                                         count -= bank->bus_width;
1853                                 }
1854                         }
1855                 }
1856                 else
1857                         return retval;
1858         }
1859
1860         /* return to read array mode, so we can read from flash again for padding */
1861         cfi_command(bank, 0xf0, current_word);
1862         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1863         cfi_command(bank, 0xff, current_word);
1864         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1865
1866         /* handle unaligned tail bytes */
1867         if (count > 0)
1868         {
1869                 LOG_INFO("Fixup %d unaligned tail bytes", count );
1870
1871                 copy_p = write_p;
1872                 for (i = 0; i < bank->bus_width; i++)
1873                         current_word[i] = 0;
1874
1875                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1876                 {
1877                         cfi_add_byte(bank, current_word, *buffer++);
1878                         count--;
1879                 }
1880                 for (; i < bank->bus_width; ++i, ++copy_p)
1881                 {
1882                         u8 byte;
1883                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1884                         cfi_add_byte(bank, current_word, byte);
1885                 }
1886                 retval = cfi_write_word(bank, current_word, write_p);
1887                 if (retval != ERROR_OK)
1888                         return retval;
1889         }
1890
1891         /* return to read array mode */
1892         cfi_command(bank, 0xf0, current_word);
1893         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1894         cfi_command(bank, 0xff, current_word);
1895         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1896
1897         return ERROR_OK;
1898 }
1899
1900 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1901 {
1902         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1903         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1904
1905         pri_ext->_reversed_geometry = 1;
1906 }
1907
1908 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1909 {
1910         int i;
1911         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1912         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1913
1914         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1915         {
1916                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1917
1918                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1919                 {
1920                         int j = (cfi_info->num_erase_regions - 1) - i;
1921                         u32 swap;
1922
1923                         swap = cfi_info->erase_region_info[i];
1924                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1925                         cfi_info->erase_region_info[j] = swap;
1926                 }
1927         }
1928 }
1929
1930 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1931 {
1932         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1933         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1934         cfi_unlock_addresses_t *unlock_addresses = param;
1935
1936         pri_ext->_unlock1 = unlock_addresses->unlock1;
1937         pri_ext->_unlock2 = unlock_addresses->unlock2;
1938 }
1939
1940 int cfi_probe(struct flash_bank_s *bank)
1941 {
1942         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1943         target_t *target = bank->target;
1944         u8 command[8];
1945         int num_sectors = 0;
1946         int i;
1947         int sector = 0;
1948         u32 offset = 0;
1949         u32 unlock1 = 0x555;
1950         u32 unlock2 = 0x2aa;
1951
1952         if (bank->target->state != TARGET_HALTED)
1953         {
1954                 LOG_ERROR("Target not halted");
1955                 return ERROR_TARGET_NOT_HALTED;
1956         }
1957
1958         cfi_info->probed = 0;
1959
1960         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1961          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1962          */
1963         if (cfi_info->jedec_probe)
1964         {
1965                 unlock1 = 0x5555;
1966                 unlock2 = 0x2aaa;
1967         }
1968
1969         /* switch to read identifier codes mode ("AUTOSELECT") */
1970         cfi_command(bank, 0xaa, command);
1971         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1972         cfi_command(bank, 0x55, command);
1973         target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1974         cfi_command(bank, 0x90, command);
1975         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1976
1977         if (bank->chip_width == 1)
1978         {
1979                 u8 manufacturer, device_id;
1980                 target_read_u8(target, bank->base + 0x0, &manufacturer);
1981                 target_read_u8(target, bank->base + 0x1, &device_id);
1982                 cfi_info->manufacturer = manufacturer;
1983                 cfi_info->device_id = device_id;
1984         }
1985         else if (bank->chip_width == 2)
1986         {
1987                 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1988                 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1989         }
1990
1991         /* switch back to read array mode */
1992         cfi_command(bank, 0xf0, command);
1993         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1994         cfi_command(bank, 0xff, command);
1995         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1996
1997         cfi_fixup(bank, cfi_jedec_fixups);
1998
1999         /* query only if this is a CFI compatible flash,
2000          * otherwise the relevant info has already been filled in
2001          */
2002         if (cfi_info->not_cfi == 0)
2003         {
2004                 /* enter CFI query mode
2005                  * according to JEDEC Standard No. 68.01,
2006                  * a single bus sequence with address = 0x55, data = 0x98 should put
2007                  * the device into CFI query mode.
2008                  *
2009                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2010                  */
2011                 cfi_command(bank, 0x98, command);
2012                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2013
2014                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2015                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2016                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2017
2018                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2019
2020                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2021                 {
2022                         cfi_command(bank, 0xf0, command);
2023                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2024                         cfi_command(bank, 0xff, command);
2025                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2026                         LOG_ERROR("Could not probe bank");
2027                         return ERROR_FLASH_BANK_INVALID;
2028                 }
2029
2030                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2031                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2032                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2033                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2034
2035                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2036
2037                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2038                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2039                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2040                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2041                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2042                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2043                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2044                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2045                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2046                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2047                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2048                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2049
2050                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2051                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2052                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2053                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2054                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2055                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2056                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2057                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2058                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2059                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2060                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2061
2062                 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
2063                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2064                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2065                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2066
2067                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2068
2069                 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
2070                 {
2071                         LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
2072                 }
2073
2074                 if (cfi_info->num_erase_regions)
2075                 {
2076                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2077                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2078                         {
2079                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2080                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2081                         }
2082                 }
2083                 else
2084                 {
2085                         cfi_info->erase_region_info = NULL;
2086                 }
2087
2088                 /* We need to read the primary algorithm extended query table before calculating
2089                  * the sector layout to be able to apply fixups
2090                  */
2091                 switch(cfi_info->pri_id)
2092                 {
2093                         /* Intel command set (standard and extended) */
2094                         case 0x0001:
2095                         case 0x0003:
2096                                 cfi_read_intel_pri_ext(bank);
2097                                 break;
2098                         /* AMD/Spansion, Atmel, ... command set */
2099                         case 0x0002:
2100                                 cfi_read_0002_pri_ext(bank);
2101                                 break;
2102                         default:
2103                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2104                                 break;
2105                 }
2106
2107                 /* return to read array mode
2108                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2109                  */
2110                 cfi_command(bank, 0xf0, command);
2111                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2112                 cfi_command(bank, 0xff, command);
2113                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2114         }
2115
2116         /* apply fixups depending on the primary command set */
2117         switch(cfi_info->pri_id)
2118         {
2119                 /* Intel command set (standard and extended) */
2120                 case 0x0001:
2121                 case 0x0003:
2122                         cfi_fixup(bank, cfi_0001_fixups);
2123                         break;
2124                 /* AMD/Spansion, Atmel, ... command set */
2125                 case 0x0002:
2126                         cfi_fixup(bank, cfi_0002_fixups);
2127                         break;
2128                 default:
2129                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2130                         break;
2131         }
2132
2133         if (cfi_info->num_erase_regions == 0)
2134         {
2135                 /* a device might have only one erase block, spanning the whole device */
2136                 bank->num_sectors = 1;
2137                 bank->sectors = malloc(sizeof(flash_sector_t));
2138
2139                 bank->sectors[sector].offset = 0x0;
2140                 bank->sectors[sector].size = bank->size;
2141                 bank->sectors[sector].is_erased = -1;
2142                 bank->sectors[sector].is_protected = -1;
2143         }
2144         else
2145         {
2146                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2147                 {
2148                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2149                 }
2150
2151                 bank->num_sectors = num_sectors;
2152                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2153
2154                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2155                 {
2156                         int j;
2157                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2158                         {
2159                                 bank->sectors[sector].offset = offset;
2160                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2161                                 offset += bank->sectors[sector].size;
2162                                 bank->sectors[sector].is_erased = -1;
2163                                 bank->sectors[sector].is_protected = -1;
2164                                 sector++;
2165                         }
2166                 }
2167         }
2168
2169         cfi_info->probed = 1;
2170
2171         return ERROR_OK;
2172 }
2173
2174 int cfi_auto_probe(struct flash_bank_s *bank)
2175 {
2176         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2177         if (cfi_info->probed)
2178                 return ERROR_OK;
2179         return cfi_probe(bank);
2180 }
2181
2182
2183 int cfi_intel_protect_check(struct flash_bank_s *bank)
2184 {
2185         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2186         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2187         target_t *target = bank->target;
2188         u8 command[CFI_MAX_BUS_WIDTH];
2189         int i;
2190
2191         /* check if block lock bits are supported on this device */
2192         if (!(pri_ext->blk_status_reg_mask & 0x1))
2193                 return ERROR_FLASH_OPERATION_FAILED;
2194
2195         cfi_command(bank, 0x90, command);
2196         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2197
2198         for (i = 0; i < bank->num_sectors; i++)
2199         {
2200                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2201
2202                 if (block_status & 1)
2203                         bank->sectors[i].is_protected = 1;
2204                 else
2205                         bank->sectors[i].is_protected = 0;
2206         }
2207
2208         cfi_command(bank, 0xff, command);
2209         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2210
2211         return ERROR_OK;
2212 }
2213
2214 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2215 {
2216         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2217         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2218         target_t *target = bank->target;
2219         u8 command[8];
2220         int i;
2221
2222         cfi_command(bank, 0xaa, command);
2223         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2224
2225         cfi_command(bank, 0x55, command);
2226         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2227
2228         cfi_command(bank, 0x90, command);
2229         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2230
2231         for (i = 0; i < bank->num_sectors; i++)
2232         {
2233                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2234
2235                 if (block_status & 1)
2236                         bank->sectors[i].is_protected = 1;
2237                 else
2238                         bank->sectors[i].is_protected = 0;
2239         }
2240
2241         cfi_command(bank, 0xf0, command);
2242         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2243
2244         return ERROR_OK;
2245 }
2246
2247 int cfi_protect_check(struct flash_bank_s *bank)
2248 {
2249         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2250
2251         if (bank->target->state != TARGET_HALTED)
2252         {
2253                 LOG_ERROR("Target not halted");
2254                 return ERROR_TARGET_NOT_HALTED;
2255         }
2256
2257         if (cfi_info->qry[0] != 'Q')
2258                 return ERROR_FLASH_BANK_NOT_PROBED;
2259
2260         switch(cfi_info->pri_id)
2261         {
2262                 case 1:
2263                 case 3:
2264                         return cfi_intel_protect_check(bank);
2265                         break;
2266                 case 2:
2267                         return cfi_spansion_protect_check(bank);
2268                         break;
2269                 default:
2270                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2271                         break;
2272         }
2273
2274         return ERROR_OK;
2275 }
2276
2277 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2278 {
2279         int printed;
2280         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2281
2282         if (cfi_info->qry[0] == (char)-1)
2283         {
2284                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2285                 return ERROR_OK;
2286         }
2287
2288         if (cfi_info->not_cfi == 0)
2289         printed = snprintf(buf, buf_size, "\ncfi information:\n");
2290         else
2291                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2292         buf += printed;
2293         buf_size -= printed;
2294
2295         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2296                 cfi_info->manufacturer, cfi_info->device_id);
2297         buf += printed;
2298         buf_size -= printed;
2299
2300         if (cfi_info->not_cfi == 0)
2301         {
2302         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2303         buf += printed;
2304         buf_size -= printed;
2305
2306                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2307                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2308         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2309         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2310         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2311         buf += printed;
2312         buf_size -= printed;
2313
2314                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2315                                    1 << cfi_info->word_write_timeout_typ,
2316                                    1 << cfi_info->buf_write_timeout_typ,
2317                                    1 << cfi_info->block_erase_timeout_typ,
2318                                    1 << cfi_info->chip_erase_timeout_typ);
2319         buf += printed;
2320         buf_size -= printed;
2321
2322                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2323                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2324                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2325                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2326                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2327         buf += printed;
2328         buf_size -= printed;
2329
2330                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2331                                    1 << cfi_info->dev_size,
2332                                    cfi_info->interface_desc,
2333                                    1 << cfi_info->max_buf_write_size);
2334         buf += printed;
2335         buf_size -= printed;
2336
2337         switch(cfi_info->pri_id)
2338         {
2339                 case 1:
2340                 case 3:
2341                         cfi_intel_info(bank, buf, buf_size);
2342                         break;
2343                 case 2:
2344                         cfi_spansion_info(bank, buf, buf_size);
2345                         break;
2346                 default:
2347                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2348                         break;
2349         }
2350         }
2351
2352         return ERROR_OK;
2353 }