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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "cfi.h"
  27
  28 #include "flash.h"
  29 #include "target.h"
  30 #include "log.h"
  31 #include "armv4_5.h"
  32 #include "algorithm.h"
  33 #include "binarybuffer.h"
  34 #include "types.h"
  35
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39
  40 int cfi_register_commands(struct command_context_s *cmd_ctx);
  41 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  42 int cfi_erase(struct flash_bank_s *bank, int first, int last);
  43 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  44 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  45 int cfi_probe(struct flash_bank_s *bank);
  46 int cfi_erase_check(struct flash_bank_s *bank);
  47 int cfi_protect_check(struct flash_bank_s *bank);
  48 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  49
  50 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51
  52 #define CFI_MAX_BUS_WIDTH       4
  53 #define CFI_MAX_CHIP_WIDTH      4
  54
  55 flash_driver_t cfi_flash =
  56 {
  57         .name = "cfi",
  58         .register_commands = cfi_register_commands,
  59         .flash_bank_command = cfi_flash_bank_command,
  60         .erase = cfi_erase,
  61         .protect = cfi_protect,
  62         .write = cfi_write,
  63         .probe = cfi_probe,
  64         .erase_check = cfi_erase_check,
  65         .protect_check = cfi_protect_check,
  66         .info = cfi_info
  67 };
  68
  69 cfi_unlock_addresses_t cfi_unlock_addresses[] =
  70 {
  71         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  72         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  73 };
  74
  75 /* CFI fixups foward declarations */
  76 void cfi_fixup_non_cfi(flash_bank_t *flash, void *param);
  77 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  78 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  79 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  80
  81 /* fixup after identifying JEDEC manufactuer and ID */
  82 cfi_fixup_t cfi_jedec_fixups[] = {
  83         {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
  84         {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
  85         {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
  86         {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
  87         {0, 0, NULL, NULL}
  88 };
  89
  90 /* fixup after reading cmdset 0002 primary query table */
  91 cfi_fixup_t cfi_0002_fixups[] = {
  92         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  93         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  94         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  95         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  96         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  97         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  98         {0, 0, NULL, NULL}
  99 };
 100
 101 /* fixup after reading cmdset 0001 primary query table */
 102 cfi_fixup_t cfi_0001_fixups[] = {
 103         {0, 0, NULL, NULL}
 104 };
 105
 106 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 107 {
 108         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 109         cfi_fixup_t *f;
 110
 111         for (f = fixups; f->fixup; f++)
 112         {
 113                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 114                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 115                 {
 116                         f->fixup(bank, f->param);
 117                 }
 118         }
 119 }
 120
 121 inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 122 {
 123         /* while the sector list isn't built, only accesses to sector 0 work */
 124         if (sector == 0)
 125                 return bank->base + offset * bank->bus_width;
 126         else
 127         {
 128                 if (!bank->sectors)
 129                 {
 130                         ERROR("BUG: sector list not yet built");
 131                         exit(-1);
 132                 }
 133                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 134         }
 135
 136 }
 137
 138 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 139 {
 140         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 141         int i;
 142
 143         /* clear whole buffer, to ensure bits that exceed the bus_width
 144          * are set to zero
 145          */
 146         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 147                 cmd_buf[i] = 0;
 148
 149         if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
 150         {
 151                 for (i = bank->bus_width; i > 0; i--)
 152                 {
 153                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 154                 }
 155         }
 156         else
 157         {
 158                 for (i = 1; i <= bank->bus_width; i++)
 159                 {
 160                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 161                 }
 162         }
 163 }
 164
 165 /* read unsigned 8-bit value from the bank
 166  * flash banks are expected to be made of similar chips
 167  * the query result should be the same for all
 168  */
 169 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 170 {
 171         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 172         target_t *target = cfi_info->target;
 173         u8 data[CFI_MAX_BUS_WIDTH];
 174
 175         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 176
 177         if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
 178                 return data[0];
 179         else
 180                 return data[bank->bus_width - 1];
 181 }
 182
 183 /* read unsigned 8-bit value from the bank
 184  * in case of a bank made of multiple chips,
 185  * the individual values are ORed
 186  */
 187 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 188 {
 189         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 190         target_t *target = cfi_info->target;
 191         u8 data[CFI_MAX_BUS_WIDTH];
 192         int i;
 193
 194         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 195
 196         if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
 197         {
 198                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 199                         data[0] |= data[i];
 200
 201                 return data[0];
 202         }
 203         else
 204         {
 205                 u8 value = 0;
 206                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 207                         value |= data[bank->bus_width - 1 - i];
 208
 209                 return value;
 210         }
 211 }
 212
 213 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 214 {
 215         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 216         target_t *target = cfi_info->target;
 217         u8 data[CFI_MAX_BUS_WIDTH * 2];
 218
 219         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 220
 221         if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
 222                 return data[0] | data[bank->bus_width] << 8;
 223         else
 224                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 225 }
 226
 227 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 228 {
 229         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 230         target_t *target = cfi_info->target;
 231         u8 data[CFI_MAX_BUS_WIDTH * 4];
 232
 233         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 234
 235         if (cfi_info->target->endianness == TARGET_LITTLE_ENDIAN)
 236                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 237         else
 238                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 239                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 240 }
 241
 242 void cfi_intel_clear_status_register(flash_bank_t *bank)
 243 {
 244         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 245         target_t *target = cfi_info->target;
 246         u8 command[8];
 247
 248         if (target->state != TARGET_HALTED)
 249         {
 250                 ERROR("BUG: attempted to clear status register while target wasn't halted");
 251                 exit(-1);
 252         }
 253
 254         cfi_command(bank, 0x50, command);
 255         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 256 }
 257
 258 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 259 {
 260         u8 status;
 261
 262         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 263         {
 264                 DEBUG("status: 0x%x", status);
 265                 usleep(1000);
 266         }
 267
 268         /* mask out bit 0 (reserved) */
 269         status = status & 0xfe;
 270
 271         DEBUG("status: 0x%x", status);
 272
 273         if ((status & 0x80) != 0x80)
 274         {
 275                 ERROR("timeout while waiting for WSM to become ready");
 276         }
 277         else if (status != 0x80)
 278         {
 279                 ERROR("status register: 0x%x", status);
 280                 if (status & 0x2)
 281                         ERROR("Block Lock-Bit Detected, Operation Abort");
 282                 if (status & 0x4)
 283                         ERROR("Program suspended");
 284                 if (status & 0x8)
 285                         ERROR("Low Programming Voltage Detected, Operation Aborted");
 286                 if (status & 0x10)
 287                         ERROR("Program Error / Error in Setting Lock-Bit");
 288                 if (status & 0x20)
 289                         ERROR("Error in Block Erasure or Clear Lock-Bits");
 290                 if (status & 0x40)
 291                         ERROR("Block Erase Suspended");
 292
 293                 cfi_intel_clear_status_register(bank);
 294         }
 295
 296         return status;
 297 }
 298
 299 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 300 {
 301         u8 status, oldstatus;
 302
 303         oldstatus = cfi_get_u8(bank, 0, 0x0);
 304
 305         do {
 306                 status = cfi_get_u8(bank, 0, 0x0);
 307                 if ((status ^ oldstatus) & 0x40) {
 308                         if (status & 0x20) {
 309                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 310                                 status = cfi_get_u8(bank, 0, 0x0);
 311                                 if ((status ^ oldstatus) & 0x40) {
 312                                         ERROR("dq5 timeout, status: 0x%x", status);
 313                                         return(ERROR_FLASH_OPERATION_FAILED);
 314                                 } else {
 315                                         DEBUG("status: 0x%x", status);
 316                                         return(ERROR_OK);
 317                                 }
 318                         }
 319                 } else {
 320                         DEBUG("status: 0x%x", status);
 321                         return(ERROR_OK);
 322                 }
 323
 324                 oldstatus = status;
 325                 usleep(1000);
 326         } while (timeout-- > 0);
 327
 328         ERROR("timeout, status: 0x%x", status);
 329
 330         return(ERROR_FLASH_BUSY);
 331 }
 332
 333 int cfi_read_intel_pri_ext(flash_bank_t *bank)
 334 {
 335         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 336         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 337         target_t *target = cfi_info->target;
 338         u8 command[8];
 339
 340         cfi_info->pri_ext = pri_ext;
 341
 342         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 343         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 344         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 345
 346         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 347         {
 348                 cfi_command(bank, 0xf0, command);
 349                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 350                 cfi_command(bank, 0xff, command);
 351                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 352                 return ERROR_FLASH_BANK_INVALID;
 353         }
 354
 355         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 356         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 357
 358         DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 359
 360         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 361         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 362         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 363
 364         DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 365
 366         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 367         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 368
 369         DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 370                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 371                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 372
 373         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 374         if (pri_ext->num_protection_fields != 1)
 375         {
 376                 WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 377         }
 378
 379         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 380         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 381         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 382
 383         DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 384
 385         return ERROR_OK;
 386 }
 387
 388 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 389 {
 390         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 391         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 392         target_t *target = cfi_info->target;
 393         u8 command[8];
 394
 395         cfi_info->pri_ext = pri_ext;
 396
 397         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 398         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 399         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 400
 401         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 402         {
 403                 cfi_command(bank, 0xf0, command);
 404                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 405                 return ERROR_FLASH_BANK_INVALID;
 406         }
 407
 408         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 409         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 410
 411         DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 412
 413         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 414         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 415         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 416         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 417         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 418         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 419         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 420         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 421         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 422         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 423         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 424
 425         DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 426               pri_ext->EraseSuspend, pri_ext->BlkProt);
 427
 428         DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 429               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 430
 431         DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 432
 433
 434         DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 435                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 436                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 437
 438         DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 439
 440         /* default values for implementation specific workarounds */
 441         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 442         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 443         pri_ext->_reversed_geometry = 0;
 444
 445         return ERROR_OK;
 446 }
 447
 448 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 449 {
 450         cfi_atmel_pri_ext_t atmel_pri_ext;
 451         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 452         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 453         target_t *target = cfi_info->target;
 454         u8 command[8];
 455
 456         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 457          * but a different primary extended query table.
 458          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 459          */
 460
 461         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 462
 463         cfi_info->pri_ext = pri_ext;
 464
 465         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 466         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 467         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 468
 469         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 470         {
 471                 cfi_command(bank, 0xf0, command);
 472                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 473                 return ERROR_FLASH_BANK_INVALID;
 474         }
 475
 476         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 477         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 478         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 479
 480         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 481         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 482
 483         DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 484
 485         pri_ext->major_version = atmel_pri_ext.major_version;
 486         pri_ext->minor_version = atmel_pri_ext.minor_version;
 487
 488         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 489         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 490         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 491         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 492
 493         DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 494                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 495
 496         if (atmel_pri_ext.features & 0x02)
 497                 pri_ext->EraseSuspend = 2;
 498
 499         if (atmel_pri_ext.bottom_boot)
 500                 pri_ext->TopBottom = 2;
 501         else
 502                 pri_ext->TopBottom = 3;
 503
 504         return ERROR_OK;
 505 }
 506
 507 int cfi_read_0002_pri_ext(flash_bank_t *bank)
 508 {
 509         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 510
 511         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 512         {
 513                 return cfi_read_atmel_pri_ext(bank);
 514         }
 515         else
 516         {
 517                 return cfi_read_spansion_pri_ext(bank);
 518         }
 519 }
 520
 521 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 522 {
 523         int printed;
 524         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 525         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 526
 527         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 528         buf += printed;
 529         buf_size -= printed;
 530
 531         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 532                            pri_ext->pri[1], pri_ext->pri[2],
 533                            pri_ext->major_version, pri_ext->minor_version);
 534         buf += printed;
 535         buf_size -= printed;
 536
 537         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 538                            (pri_ext->SiliconRevision) >> 2,
 539                            (pri_ext->SiliconRevision) & 0x03);
 540         buf += printed;
 541         buf_size -= printed;
 542
 543         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 544                            pri_ext->EraseSuspend,
 545                            pri_ext->BlkProt);
 546         buf += printed;
 547         buf_size -= printed;
 548
 549         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 550                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 551                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 552
 553         return ERROR_OK;
 554 }
 555
 556 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 557 {
 558         int printed;
 559         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 560         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 561
 562         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 563         buf += printed;
 564         buf_size -= printed;
 565
 566         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 567         buf += printed;
 568         buf_size -= printed;
 569
 570         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 571         buf += printed;
 572         buf_size -= printed;
 573
 574         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 575                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 576                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 577         buf += printed;
 578         buf_size -= printed;
 579
 580         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 581
 582         return ERROR_OK;
 583 }
 584
 585 int cfi_register_commands(struct command_context_s *cmd_ctx)
 586 {
 587         /*command_t *cfi_cmd = */register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, NULL);
 588         /*
 589         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 590                                          "print part id of cfi flash bank <num>");
 591         */
 592         return ERROR_OK;
 593 }
 594
 595 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 596  */
 597 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 598 {
 599         cfi_flash_bank_t *cfi_info;
 600         int i;
 601
 602         if (argc < 6)
 603         {
 604                 WARNING("incomplete flash_bank cfi configuration");
 605                 return ERROR_FLASH_BANK_INVALID;
 606         }
 607
 608         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 609                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 610         {
 611                 ERROR("chip and bus width have to specified in byte");
 612                 return ERROR_FLASH_BANK_INVALID;
 613         }
 614
 615         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 616         bank->driver_priv = cfi_info;
 617
 618         cfi_info->x16_as_x8 = 0;
 619         cfi_info->jedec_probe = 0;
 620         cfi_info->not_cfi = 0;
 621
 622         cfi_info->target = get_target_by_num(strtoul(args[5], NULL, 0));
 623         if (!cfi_info->target)
 624         {
 625                 ERROR("no target '%s' configured", args[5]);
 626                 exit(-1);
 627         }
 628
 629         for (i = 6; i < argc; i++)
 630         {
 631                 if (strcmp(args[i], "x16_as_x8") == 0)
 632                 {
 633                         cfi_info->x16_as_x8 = 1;
 634                 }
 635                 else if (strcmp(args[i], "jedec_probe") == 0)
 636                 {
 637                         cfi_info->jedec_probe = 1;
 638                 }
 639         }
 640
 641         cfi_info->write_algorithm = NULL;
 642
 643         /* bank wasn't probed yet */
 644         cfi_info->qry[0] = -1;
 645
 646         return ERROR_OK;
 647 }
 648
 649 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 650 {
 651         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 652         target_t *target = cfi_info->target;
 653         u8 command[8];
 654         int i;
 655
 656         cfi_intel_clear_status_register(bank);
 657
 658         for (i = first; i <= last; i++)
 659         {
 660                 cfi_command(bank, 0x20, command);
 661                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 662
 663                 cfi_command(bank, 0xd0, command);
 664                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 665
 666                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 667                         bank->sectors[i].is_erased = 1;
 668                 else
 669                 {
 670                         cfi_command(bank, 0xff, command);
 671                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 672
 673                         ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 674                         return ERROR_FLASH_OPERATION_FAILED;
 675                 }
 676         }
 677
 678         cfi_command(bank, 0xff, command);
 679         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 680
 681         return ERROR_OK;
 682 }
 683
 684 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 685 {
 686         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 687         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 688         target_t *target = cfi_info->target;
 689         u8 command[8];
 690         int i;
 691
 692         for (i = first; i <= last; i++)
 693         {
 694                 cfi_command(bank, 0xaa, command);
 695                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 696
 697                 cfi_command(bank, 0x55, command);
 698                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 699
 700                 cfi_command(bank, 0x80, command);
 701                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 702
 703                 cfi_command(bank, 0xaa, command);
 704                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 705
 706                 cfi_command(bank, 0x55, command);
 707                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 708
 709                 cfi_command(bank, 0x30, command);
 710                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 711
 712                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 713                         bank->sectors[i].is_erased = 1;
 714                 else
 715                 {
 716                         cfi_command(bank, 0xf0, command);
 717                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 718
 719                         ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 720                         return ERROR_FLASH_OPERATION_FAILED;
 721                 }
 722         }
 723
 724         cfi_command(bank, 0xf0, command);
 725         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 726
 727         return ERROR_OK;
 728 }
 729
 730 int cfi_erase(struct flash_bank_s *bank, int first, int last)
 731 {
 732         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 733
 734         if (cfi_info->target->state != TARGET_HALTED)
 735         {
 736                 return ERROR_TARGET_NOT_HALTED;
 737         }
 738
 739         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 740         {
 741                 return ERROR_FLASH_SECTOR_INVALID;
 742         }
 743
 744         if (cfi_info->qry[0] != 'Q')
 745                 return ERROR_FLASH_BANK_NOT_PROBED;
 746
 747         switch(cfi_info->pri_id)
 748         {
 749                 case 1:
 750                 case 3:
 751                         return cfi_intel_erase(bank, first, last);
 752                         break;
 753                 case 2:
 754                         return cfi_spansion_erase(bank, first, last);
 755                         break;
 756                 default:
 757                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 758                         break;
 759         }
 760
 761         return ERROR_OK;
 762 }
 763
 764 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 765 {
 766         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 767         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 768         target_t *target = cfi_info->target;
 769         u8 command[8];
 770         int retry = 0;
 771         int i;
 772
 773         /* if the device supports neither legacy lock/unlock (bit 3) nor
 774          * instant individual block locking (bit 5).
 775          */
 776         if (!(pri_ext->feature_support & 0x28))
 777                 return ERROR_FLASH_OPERATION_FAILED;
 778
 779         cfi_intel_clear_status_register(bank);
 780
 781         for (i = first; i <= last; i++)
 782         {
 783                 cfi_command(bank, 0x60, command);
 784                 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 785                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 786                 if (set)
 787                 {
 788                         cfi_command(bank, 0x01, command);
 789                         DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 790                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 791                         bank->sectors[i].is_protected = 1;
 792                 }
 793                 else
 794                 {
 795                         cfi_command(bank, 0xd0, command);
 796                         DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 797                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 798                         bank->sectors[i].is_protected = 0;
 799                 }
 800
 801                 /* instant individual block locking doesn't require reading of the status register */
 802                 if (!(pri_ext->feature_support & 0x20))
 803                 {
 804                         /* Clear lock bits operation may take up to 1.4s */
 805                         cfi_intel_wait_status_busy(bank, 1400);
 806                 }
 807                 else
 808                 {
 809                         u8 block_status;
 810                         /* read block lock bit, to verify status */
 811                         cfi_command(bank, 0x90, command);
 812                         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 813                         block_status = cfi_get_u8(bank, i, 0x2);
 814
 815                         if ((block_status & 0x1) != set)
 816                         {
 817                                 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 818                                 cfi_command(bank, 0x70, command);
 819                                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 820                                 cfi_intel_wait_status_busy(bank, 10);
 821
 822                                 if (retry > 10)
 823                                         return ERROR_FLASH_OPERATION_FAILED;
 824                                 else
 825                                 {
 826                                         i--;
 827                                         retry++;
 828                                 }
 829                         }
 830                 }
 831         }
 832
 833         /* if the device doesn't support individual block lock bits set/clear,
 834          * all blocks have been unlocked in parallel, so we set those that should be protected
 835          */
 836         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 837         {
 838                 for (i = 0; i < bank->num_sectors; i++)
 839                 {
 840                         cfi_intel_clear_status_register(bank);
 841                         cfi_command(bank, 0x60, command);
 842                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 843                         if (bank->sectors[i].is_protected == 1)
 844                         {
 845                                 cfi_command(bank, 0x01, command);
 846                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 847                         }
 848
 849                         cfi_intel_wait_status_busy(bank, 100);
 850                 }
 851         }
 852
 853         cfi_command(bank, 0xff, command);
 854         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 855
 856         return ERROR_OK;
 857 }
 858
 859 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 860 {
 861         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 862
 863         if (cfi_info->target->state != TARGET_HALTED)
 864         {
 865                 return ERROR_TARGET_NOT_HALTED;
 866         }
 867
 868         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 869         {
 870                 return ERROR_FLASH_SECTOR_INVALID;
 871         }
 872
 873         if (cfi_info->qry[0] != 'Q')
 874                 return ERROR_FLASH_BANK_NOT_PROBED;
 875
 876         switch(cfi_info->pri_id)
 877         {
 878                 case 1:
 879                 case 3:
 880                         cfi_intel_protect(bank, set, first, last);
 881                         break;
 882                 default:
 883                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 884                         break;
 885         }
 886
 887         return ERROR_OK;
 888 }
 889
 890 void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 891 {
 892         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 893         target_t *target = cfi_info->target;
 894
 895         int i;
 896
 897         if (target->endianness == TARGET_LITTLE_ENDIAN)
 898         {
 899                 /* shift bytes */
 900                 for (i = 0; i < bank->bus_width - 1; i++)
 901                         word[i] = word[i + 1];
 902                 word[bank->bus_width - 1] = byte;
 903         }
 904         else
 905         {
 906                 /* shift bytes */
 907                 for (i = bank->bus_width - 1; i > 0; i--)
 908                         word[i] = word[i - 1];
 909                 word[0] = byte;
 910         }
 911 }
 912
 913 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
 914 {
 915         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 916         target_t *target = cfi_info->target;
 917         reg_param_t reg_params[7];
 918         armv4_5_algorithm_t armv4_5_info;
 919         working_area_t *source;
 920         u32 buffer_size = 32768;
 921         u8 write_command_buf[CFI_MAX_BUS_WIDTH];
 922         u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH];
 923         u8 error_pattern_buf[CFI_MAX_BUS_WIDTH];
 924         u32 write_command_val, busy_pattern_val, error_pattern_val;
 925         int retval;
 926
 927         /* algorithm register usage:
 928          * r0: source address (in RAM)
 929          * r1: target address (in Flash)
 930          * r2: count
 931          * r3: flash write command
 932          * r4: status byte (returned to host)
 933          * r5: busy test pattern
 934          * r6: error test pattern
 935          */
 936
 937         static const u32 word_32_code[] = {
 938                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
 939                 0xe5813000,   /*                str r3, [r1] */
 940                 0xe5814000,   /*                str r4, [r1] */
 941                 0xe5914000,   /* busy:  ldr r4, [r1] */
 942                 0xe0047005,   /*                and r7, r4, r5 */
 943                 0xe1570005,   /*                cmp r7, r5 */
 944                 0x1afffffb,   /*                bne busy */
 945                 0xe1140006,   /*                tst r4, r6 */
 946                 0x1a000003,   /*                bne done */
 947                 0xe2522001,   /*                subs r2, r2, #1 */
 948                 0x0a000001,   /*                beq done */
 949                 0xe2811004,   /*                add r1, r1 #4 */
 950                 0xeafffff2,   /*                b loop */
 951                 0xeafffffe,   /* done:  b -2 */
 952         };
 953
 954         static const u32 word_16_code[] = {
 955                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
 956                 0xe1c130b0,   /*                strh r3, [r1] */
 957                 0xe1c140b0,   /*                strh r4, [r1] */
 958                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
 959                 0xe0047005,   /*                and r7, r4, r5 */
 960                 0xe1570005,   /*                cmp r7, r5 */
 961                 0x1afffffb,   /*                bne busy */
 962                 0xe1140006,   /*                tst r4, r6 */
 963                 0x1a000003,   /*                bne done */
 964                 0xe2522001,   /*                subs r2, r2, #1 */
 965                 0x0a000001,   /*                beq done */
 966                 0xe2811002,   /*                add r1, r1 #2 */
 967                 0xeafffff2,   /*                b loop */
 968                 0xeafffffe,   /* done:  b -2 */
 969         };
 970
 971         static const u32 word_8_code[] = {
 972                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
 973                 0xe5c13000,   /*                strb r3, [r1] */
 974                 0xe5c14000,   /*                strb r4, [r1] */
 975                 0xe5d14000,   /* busy   ldrb r4, [r1] */
 976                 0xe0047005,   /*                and r7, r4, r5 */
 977                 0xe1570005,   /*                cmp r7, r5 */
 978                 0x1afffffb,   /*                bne busy */
 979                 0xe1140006,   /*                tst r4, r6 */
 980                 0x1a000003,   /*                bne done */
 981                 0xe2522001,   /*                subs r2, r2, #1 */
 982                 0x0a000001,   /*                beq done */
 983                 0xe2811001,   /*                add r1, r1 #1 */
 984                 0xeafffff2,   /*                b loop */
 985                 0xeafffffe,   /* done:  b -2 */
 986         };
 987
 988         cfi_intel_clear_status_register(bank);
 989
 990         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
 991         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
 992         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
 993
 994         /* flash write code */
 995         if (!cfi_info->write_algorithm)
 996         {
 997                 u8 write_code_buf[14 * 4];
 998                 int i;
 999
1000                 if (target_alloc_working_area(target, 4 * 14, &cfi_info->write_algorithm) != ERROR_OK)
1001                 {
1002                         WARNING("no working area available, can't do block memory writes");
1003                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1004                 };
1005
1006                 /* write algorithm code to working area */
1007                 if (bank->bus_width == 1)
1008                 {
1009                         for (i = 0; i < 14; i++)
1010                                 target_buffer_set_u32(target, write_code_buf + (i*4), word_8_code[i]);
1011                 }
1012                 else if (bank->bus_width == 2)
1013                 {
1014                         for (i = 0; i < 14; i++)
1015                                 target_buffer_set_u32(target, write_code_buf + (i*4), word_16_code[i]);
1016                 }
1017                 else if (bank->bus_width == 4)
1018                 {
1019                         for (i = 0; i < 14; i++)
1020                                 target_buffer_set_u32(target, write_code_buf + (i*4), word_32_code[i]);
1021                 }
1022                 else
1023                 {
1024                         return ERROR_FLASH_OPERATION_FAILED;
1025                 }
1026
1027                 target_write_buffer(target, cfi_info->write_algorithm->address, 14 * 4, write_code_buf);
1028         }
1029
1030         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1031         {
1032                 buffer_size /= 2;
1033                 if (buffer_size <= 256)
1034                 {
1035                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1036                         if (cfi_info->write_algorithm)
1037                                 target_free_working_area(target, cfi_info->write_algorithm);
1038
1039                         WARNING("no large enough working area available, can't do block memory writes");
1040                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1041                 }
1042         };
1043
1044         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1045         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1046         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1047         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1048         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1049         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1050         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1051
1052         /* prepare command and status register patterns */
1053         cfi_command(bank, 0x40, write_command_buf);
1054         cfi_command(bank, 0x80, busy_pattern_buf);
1055         cfi_command(bank, 0x7e, error_pattern_buf);
1056
1057         if (bank->bus_width == 1)
1058         {
1059                 write_command_val = write_command_buf[0];
1060                 busy_pattern_val = busy_pattern_buf[0];
1061                 error_pattern_val = error_pattern_buf[0];
1062         }
1063         else if (bank->bus_width == 2)
1064         {
1065                 write_command_val = target_buffer_get_u16(target, write_command_buf);
1066                 busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf);
1067                 error_pattern_val = target_buffer_get_u16(target, error_pattern_buf);
1068         }
1069         else if (bank->bus_width == 4)
1070         {
1071                 write_command_val = target_buffer_get_u32(target, write_command_buf);
1072                 busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf);
1073                 error_pattern_val = target_buffer_get_u32(target, error_pattern_buf);
1074         }
1075
1076         while (count > 0)
1077         {
1078                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1079
1080                 target_write_buffer(target, source->address, thisrun_count, buffer);
1081
1082                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1083                 buf_set_u32(reg_params[1].value, 0, 32, address);
1084                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1085                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1086                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1087                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1088
1089                 if ((retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params, cfi_info->write_algorithm->address, cfi_info->write_algorithm->address + (13 * 4), 10000, &armv4_5_info)) != ERROR_OK)
1090                 {
1091                         cfi_intel_clear_status_register(bank);
1092                         return ERROR_FLASH_OPERATION_FAILED;
1093                 }
1094
1095                 if (buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val)
1096                 {
1097                         /* read status register (outputs debug inforation) */
1098                         cfi_intel_wait_status_busy(bank, 100);
1099                         cfi_intel_clear_status_register(bank);
1100                         return ERROR_FLASH_OPERATION_FAILED;
1101                 }
1102
1103                 buffer += thisrun_count;
1104                 address += thisrun_count;
1105                 count -= thisrun_count;
1106         }
1107
1108         target_free_working_area(target, source);
1109
1110         destroy_reg_param(&reg_params[0]);
1111         destroy_reg_param(&reg_params[1]);
1112         destroy_reg_param(&reg_params[2]);
1113         destroy_reg_param(&reg_params[3]);
1114         destroy_reg_param(&reg_params[4]);
1115         destroy_reg_param(&reg_params[5]);
1116         destroy_reg_param(&reg_params[6]);
1117
1118         return ERROR_OK;
1119 }
1120
1121 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1122 {
1123         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1124         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1125         target_t *target = cfi_info->target;
1126         reg_param_t reg_params[10];
1127         armv4_5_algorithm_t armv4_5_info;
1128         working_area_t *source;
1129         u32 buffer_size = 32768;
1130         u8 write_command[CFI_MAX_BUS_WIDTH];
1131         u32 status;
1132         int i;
1133         int retval;
1134         int exit_code = ERROR_OK;
1135
1136         /* input parameters - */
1137         /*      R0 = source address */
1138         /*      R1 = destination address */
1139         /*      R2 = number of writes */
1140         /*      R3 = flash write command */
1141         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1142         /* output parameters - */
1143         /*      R5 = 0x80 ok 0x00 bad */
1144         /* temp registers - */
1145         /*      R6 = value read from flash to test status */
1146         /*      R7 = holding register */
1147         /* unlock registers - */
1148         /*  R8 = unlock1_addr */
1149         /*  R9 = unlock1_cmd */
1150         /*  R10 = unlock2_addr */
1151         /*  R11 = unlock2_cmd */
1152
1153         u32 word_32_code[] = {
1154                                                 /* 00008100 <sp_32_code>:               */
1155                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1156                 0xe5889000,     /* str  r9, [r8]                                */
1157                 0xe58ab000,     /* str  r11, [r10]                              */
1158                 0xe5883000,     /* str  r3, [r8]                                */
1159                 0xe5815000,     /* str  r5, [r1]                                */
1160                 0xe1a00000,     /* nop                                                  */
1161                                                 /*                                                              */
1162                                                 /* 00008110 <sp_32_busy>:               */
1163                 0xe5916000,     /* ldr  r6, [r1]                                */
1164                 0xe0257006,     /* eor  r7, r5, r6                              */
1165                 0xe0147007,     /* ands r7, r4, r7                              */
1166                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1167                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1168                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1169                 0xe5916000,     /* ldr  r6, [r1]                                */
1170                 0xe0257006,     /* eor  r7, r5, r6                              */
1171                 0xe0147007,     /* ands r7, r4, r7                              */
1172                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1173                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1174                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1175                                                 /*                                                              */
1176                                 /* 00008140 <sp_32_cont>:                               */
1177                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1178                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1179                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1180                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1181                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1182                                                 /*                                                              */
1183                                                 /* 00008154 <sp_32_done>:               */
1184                 0xeafffffe              /* b    8154 <sp_32_done>               */
1185         };
1186
1187         u32 word_16_code[] = {
1188                                 /* 00008158 <sp_16_code>:              */
1189                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1190                 0xe1c890b0,     /* strh r9, [r8]                                */
1191                 0xe1cab0b0,     /* strh r11, [r10]                              */
1192                 0xe1c830b0,     /* strh r3, [r8]                                */
1193                 0xe1c150b0,     /* strh r5, [r1]                       */
1194                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1195                                 /*                                     */
1196                                 /* 00008168 <sp_16_busy>:              */
1197                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1198                 0xe0257006,     /* eor  r7, r5, r6                     */
1199                 0xe0147007,     /* ands r7, r4, r7                     */
1200                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1201                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1202                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1203                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1204                 0xe0257006,     /* eor  r7, r5, r6                     */
1205                 0xe0147007,     /* ands r7, r4, r7                     */
1206                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1207                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1208                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1209                                 /*                                     */
1210                                 /* 00008198 <sp_16_cont>:              */
1211                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1212                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1213                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1214                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1215                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1216                                 /*                                     */
1217                                 /* 000081ac <sp_16_done>:              */
1218                 0xeafffffe      /* b    81ac <sp_16_done>              */
1219         };
1220
1221         u32 word_8_code[] = {
1222                                 /* 000081b0 <sp_16_code_end>:          */
1223                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1224                 0xe5c89000,     /* strb r9, [r8]                                */
1225                 0xe5cab000,     /* strb r11, [r10]                              */
1226                 0xe5c83000,     /* strb r3, [r8]                                */
1227                 0xe5c15000,     /* strb r5, [r1]                       */
1228                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1229                                 /*                                     */
1230                                 /* 000081c0 <sp_8_busy>:               */
1231                 0xe5d16000,     /* ldrb r6, [r1]                       */
1232                 0xe0257006,     /* eor  r7, r5, r6                     */
1233                 0xe0147007,     /* ands r7, r4, r7                     */
1234                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1235                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1236                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1237                 0xe5d16000,     /* ldrb r6, [r1]                       */
1238                 0xe0257006,     /* eor  r7, r5, r6                     */
1239                 0xe0147007,     /* ands r7, r4, r7                     */
1240                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1241                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1242                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1243                                 /*                                     */
1244                                 /* 000081f0 <sp_8_cont>:               */
1245                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1246                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1247                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1248                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1249                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1250                                 /*                                     */
1251                                 /* 00008204 <sp_8_done>:               */
1252                 0xeafffffe      /* b    8204 <sp_8_done>               */
1253         };
1254
1255         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1256         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1257         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1258
1259         /* flash write code */
1260         if (!cfi_info->write_algorithm)
1261         {
1262                 u8 *code_p;
1263
1264                 /* convert bus-width dependent algorithm code to correct endiannes */
1265                 if (bank->bus_width == 1)
1266                 {
1267                         code_p = malloc(24 * 4);
1268
1269                         for (i = 0; i < 24; i++)
1270                                 target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]);
1271                 }
1272                 else if (bank->bus_width == 2)
1273                 {
1274                         code_p = malloc(24 * 4);
1275
1276                         for (i = 0; i < 24; i++)
1277                                 target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]);
1278                 }
1279                 else if (bank->bus_width == 4)
1280                 {
1281                         code_p = malloc(24 * 4);
1282
1283                         for (i = 0; i < 24; i++)
1284                                 target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]);
1285                 }
1286                 else
1287                 {
1288                         return ERROR_FLASH_OPERATION_FAILED;
1289                 }
1290
1291                 /* allocate working area */
1292                 if (target_alloc_working_area(target, 24 * 4,
1293                         &cfi_info->write_algorithm) != ERROR_OK)
1294                 {
1295                         WARNING("no working area available, can't do block memory writes");
1296                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1297                 }
1298
1299                 /* write algorithm code to working area */
1300                 target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p);
1301
1302                 free(code_p);
1303         }
1304
1305         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1306         {
1307                 buffer_size /= 2;
1308                 if (buffer_size <= 256)
1309                 {
1310                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1311                         if (cfi_info->write_algorithm)
1312                                 target_free_working_area(target, cfi_info->write_algorithm);
1313
1314                         WARNING("not enough working area available, can't do block memory writes");
1315                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1316                 }
1317         };
1318
1319         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1320         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1321         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1322         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1323         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1324         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1325         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1326         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1327         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1328         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1329
1330         while (count > 0)
1331         {
1332                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1333
1334                 target_write_buffer(target, source->address, thisrun_count, buffer);
1335
1336                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1337                 buf_set_u32(reg_params[1].value, 0, 32, address);
1338                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1339                 cfi_command(bank, 0xA0, write_command);
1340                 buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32));
1341                 cfi_command(bank, 0x80, write_command);
1342                 buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32));
1343                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1344                 buf_set_u32(reg_params[7].value, 0, 32, 0xaa);
1345                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1346                 buf_set_u32(reg_params[9].value, 0, 32, 0x55);
1347
1348                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1349                                                      cfi_info->write_algorithm->address,
1350                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1351                                                      10000, &armv4_5_info);
1352
1353                 status = buf_get_u32(reg_params[5].value, 0, 32);
1354
1355                 if ((retval != ERROR_OK) || status != 0x80)
1356                 {
1357                         DEBUG("status: 0x%x", status);
1358                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1359                         break;
1360                 }
1361
1362                 buffer += thisrun_count;
1363                 address += thisrun_count;
1364                 count -= thisrun_count;
1365         }
1366
1367         target_free_working_area(target, source);
1368
1369         destroy_reg_param(&reg_params[0]);
1370         destroy_reg_param(&reg_params[1]);
1371         destroy_reg_param(&reg_params[2]);
1372         destroy_reg_param(&reg_params[3]);
1373         destroy_reg_param(&reg_params[4]);
1374         destroy_reg_param(&reg_params[5]);
1375         destroy_reg_param(&reg_params[6]);
1376         destroy_reg_param(&reg_params[7]);
1377         destroy_reg_param(&reg_params[8]);
1378         destroy_reg_param(&reg_params[9]);
1379
1380         return exit_code;
1381 }
1382
1383 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1384 {
1385         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1386         target_t *target = cfi_info->target;
1387         u8 command[8];
1388
1389         cfi_intel_clear_status_register(bank);
1390         cfi_command(bank, 0x40, command);
1391         target->type->write_memory(target, address, bank->bus_width, 1, command);
1392
1393         target->type->write_memory(target, address, bank->bus_width, 1, word);
1394
1395         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1396         {
1397                 cfi_command(bank, 0xff, command);
1398                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1399
1400                 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1401                 return ERROR_FLASH_OPERATION_FAILED;
1402         }
1403
1404         return ERROR_OK;
1405 }
1406
1407 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1408 {
1409         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1410         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1411         target_t *target = cfi_info->target;
1412         u8 command[8];
1413
1414         cfi_command(bank, 0xaa, command);
1415         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1416
1417         cfi_command(bank, 0x55, command);
1418         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1419
1420         cfi_command(bank, 0xa0, command);
1421         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1422
1423         target->type->write_memory(target, address, bank->bus_width, 1, word);
1424
1425         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1426         {
1427                 cfi_command(bank, 0xf0, command);
1428                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1429
1430                 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1431                 return ERROR_FLASH_OPERATION_FAILED;
1432         }
1433
1434         return ERROR_OK;
1435 }
1436
1437 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1438 {
1439         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1440
1441         switch(cfi_info->pri_id)
1442         {
1443                 case 1:
1444                 case 3:
1445                         return cfi_intel_write_word(bank, word, address);
1446                         break;
1447                 case 2:
1448                         return cfi_spansion_write_word(bank, word, address);
1449                         break;
1450                 default:
1451                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1452                         break;
1453         }
1454
1455         return ERROR_FLASH_OPERATION_FAILED;
1456 }
1457
1458 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1459 {
1460         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1461         target_t *target = cfi_info->target;
1462         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1463         u32 write_p, copy_p;
1464         int align;      /* number of unaligned bytes */
1465         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1466         int i;
1467         int retval;
1468
1469         if (cfi_info->target->state != TARGET_HALTED)
1470         {
1471                 return ERROR_TARGET_NOT_HALTED;
1472         }
1473
1474         if (offset + count > bank->size)
1475                 return ERROR_FLASH_DST_OUT_OF_BANK;
1476
1477         if (cfi_info->qry[0] != 'Q')
1478                 return ERROR_FLASH_BANK_NOT_PROBED;
1479
1480         /* start at the first byte of the first word (bus_width size) */
1481         write_p = address & ~(bank->bus_width - 1);
1482         if ((align = address - write_p) != 0)
1483         {
1484                 for (i = 0; i < bank->bus_width; i++)
1485                         current_word[i] = 0;
1486                 copy_p = write_p;
1487
1488                 /* copy bytes before the first write address */
1489                 for (i = 0; i < align; ++i, ++copy_p)
1490                 {
1491                         u8 byte;
1492                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1493                         cfi_add_byte(bank, current_word, byte);
1494                 }
1495
1496                 /* add bytes from the buffer */
1497                 for (; (i < bank->bus_width) && (count > 0); i++)
1498                 {
1499                         cfi_add_byte(bank, current_word, *buffer++);
1500                         count--;
1501                         copy_p++;
1502                 }
1503
1504                 /* if the buffer is already finished, copy bytes after the last write address */
1505                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1506                 {
1507                         u8 byte;
1508                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1509                         cfi_add_byte(bank, current_word, byte);
1510                 }
1511
1512                 retval = cfi_write_word(bank, current_word, write_p);
1513                 if (retval != ERROR_OK)
1514                         return retval;
1515                 write_p = copy_p;
1516         }
1517
1518         /* handle blocks of bus_size aligned bytes */
1519         switch(cfi_info->pri_id)
1520         {
1521                 /* try block writes (fails without working area) */
1522                 case 1:
1523                 case 3:
1524                         retval = cfi_intel_write_block(bank, buffer, write_p, count);
1525                         break;
1526                 case 2:
1527                         retval = cfi_spansion_write_block(bank, buffer, write_p, count);
1528                         break;
1529                 default:
1530                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1531       retval = ERROR_FLASH_OPERATION_FAILED;
1532                         break;
1533         }
1534         if (retval != ERROR_OK)
1535         {
1536                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1537                 {
1538                         /* fall back to memory writes */
1539                         while (count > bank->bus_width)
1540                         {
1541                                 for (i = 0; i < bank->bus_width; i++)
1542                                         current_word[i] = 0;
1543
1544                                 for (i = 0; i < bank->bus_width; i++)
1545                                 {
1546                                         cfi_add_byte(bank, current_word, *buffer++);
1547                                 }
1548
1549                                 retval = cfi_write_word(bank, current_word, write_p);
1550                                 if (retval != ERROR_OK)
1551                                         return retval;
1552                                 write_p += bank->bus_width;
1553                                 count -= bank->bus_width;
1554                         }
1555                 }
1556                 else
1557                         return retval;
1558         }
1559
1560         /* handle unaligned tail bytes */
1561         if (count > 0)
1562         {
1563                 copy_p = write_p;
1564                 for (i = 0; i < bank->bus_width; i++)
1565                         current_word[i] = 0;
1566
1567                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1568                 {
1569                         cfi_add_byte(bank, current_word, *buffer++);
1570                         count--;
1571                 }
1572                 for (; i < bank->bus_width; ++i, ++copy_p)
1573                 {
1574                         u8 byte;
1575                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1576                         cfi_add_byte(bank, current_word, byte);
1577                 }
1578                 retval = cfi_write_word(bank, current_word, write_p);
1579                 if (retval != ERROR_OK)
1580                         return retval;
1581         }
1582
1583         /* return to read array mode */
1584         cfi_command(bank, 0xf0, current_word);
1585         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1586         cfi_command(bank, 0xff, current_word);
1587         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1588
1589         return ERROR_OK;
1590 }
1591
1592 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1593 {
1594         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1595         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1596
1597         pri_ext->_reversed_geometry = 1;
1598 }
1599
1600 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1601 {
1602         int i;
1603         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1604         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1605
1606         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1607         {
1608                 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1609
1610                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1611                 {
1612                         int j = (cfi_info->num_erase_regions - 1) - i;
1613                         u32 swap;
1614
1615                         swap = cfi_info->erase_region_info[i];
1616                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1617                         cfi_info->erase_region_info[j] = swap;
1618                 }
1619         }
1620 }
1621
1622 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1623 {
1624         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1625         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1626         cfi_unlock_addresses_t *unlock_addresses = param;
1627
1628         pri_ext->_unlock1 = unlock_addresses->unlock1;
1629         pri_ext->_unlock2 = unlock_addresses->unlock2;
1630 }
1631
1632 int cfi_probe(struct flash_bank_s *bank)
1633 {
1634         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1635         target_t *target = cfi_info->target;
1636         u8 command[8];
1637         int num_sectors = 0;
1638         int i;
1639         int sector = 0;
1640         u32 offset = 0;
1641         u32 unlock1 = 0x555;
1642         u32 unlock2 = 0x2aa;
1643
1644         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1645          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1646          */
1647         if (cfi_info->jedec_probe)
1648         {
1649                 unlock1 = 0x5555;
1650                 unlock2 = 0x2aaa;
1651         }
1652
1653         /* switch to read identifier codes mode ("AUTOSELECT") */
1654         cfi_command(bank, 0xaa, command);
1655         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1656         cfi_command(bank, 0x55, command);
1657         target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1658         cfi_command(bank, 0x90, command);
1659         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1660
1661         if (bank->chip_width == 1)
1662         {
1663                 u8 manufacturer, device_id;
1664                 target_read_u8(target, bank->base + 0x0, &manufacturer);
1665                 target_read_u8(target, bank->base + 0x1, &device_id);
1666                 cfi_info->manufacturer = manufacturer;
1667                 cfi_info->device_id = device_id;
1668         }
1669         else if (bank->chip_width == 2)
1670         {
1671                 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1672                 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1673         }
1674
1675         /* switch back to read array mode */
1676         cfi_command(bank, 0xf0, command);
1677         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1678         cfi_command(bank, 0xff, command);
1679         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1680
1681         cfi_fixup(bank, cfi_jedec_fixups);
1682
1683         /* query only if this is a CFI compatible flash,
1684          * otherwise the relevant info has already been filled in
1685          */
1686         if (cfi_info->not_cfi == 0)
1687         {
1688                 /* enter CFI query mode
1689                  * according to JEDEC Standard No. 68.01,
1690                  * a single bus sequence with address = 0x55, data = 0x98 should put
1691                  * the device into CFI query mode.
1692                  *
1693                  * SST flashes clearly violate this, and we will consider them incompatbile for now
1694                  */
1695                 cfi_command(bank, 0x98, command);
1696                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1697
1698                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1699                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1700                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1701
1702                 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1703
1704                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1705                 {
1706                         cfi_command(bank, 0xf0, command);
1707                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1708                         cfi_command(bank, 0xff, command);
1709                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1710                         return ERROR_FLASH_BANK_INVALID;
1711                 }
1712
1713                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1714                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1715                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1716                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1717
1718                 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1719
1720                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1721                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1722                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1723                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1724                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1725                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1726                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1727                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1728                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1729                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1730                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1731                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1732
1733                 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1734                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1735                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1736                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1737                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1738                 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1739                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1740                 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1741                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1742                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1743                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1744
1745                 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1746                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1747                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1748                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1749
1750                 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1751
1752                 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1753                 {
1754                         WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1755                 }
1756
1757                 if (cfi_info->num_erase_regions)
1758                 {
1759                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1760                         for (i = 0; i < cfi_info->num_erase_regions; i++)
1761                         {
1762                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1763                                 DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1764                         }
1765                 }
1766                 else
1767                 {
1768                         cfi_info->erase_region_info = NULL;
1769                 }
1770
1771                 /* We need to read the primary algorithm extended query table before calculating
1772                  * the sector layout to be able to apply fixups
1773                  */
1774                 switch(cfi_info->pri_id)
1775                 {
1776                         /* Intel command set (standard and extended) */
1777                         case 0x0001:
1778                         case 0x0003:
1779                                 cfi_read_intel_pri_ext(bank);
1780                                 break;
1781                         /* AMD/Spansion, Atmel, ... command set */
1782                         case 0x0002:
1783                                 cfi_read_0002_pri_ext(bank);
1784                                 break;
1785                         default:
1786                                 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1787                                 break;
1788                 }
1789
1790                 /* return to read array mode
1791                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
1792                  */
1793                 cfi_command(bank, 0xf0, command);
1794                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1795                 cfi_command(bank, 0xff, command);
1796                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1797         }
1798
1799         /* apply fixups depending on the primary command set */
1800         switch(cfi_info->pri_id)
1801         {
1802                 /* Intel command set (standard and extended) */
1803                 case 0x0001:
1804                 case 0x0003:
1805                         cfi_fixup(bank, cfi_0001_fixups);
1806                         break;
1807                 /* AMD/Spansion, Atmel, ... command set */
1808                 case 0x0002:
1809                         cfi_fixup(bank, cfi_0002_fixups);
1810                         break;
1811                 default:
1812                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1813                         break;
1814         }
1815
1816         if (cfi_info->num_erase_regions == 0)
1817         {
1818                 /* a device might have only one erase block, spanning the whole device */
1819                 bank->num_sectors = 1;
1820                 bank->sectors = malloc(sizeof(flash_sector_t));
1821
1822                 bank->sectors[sector].offset = 0x0;
1823                 bank->sectors[sector].size = bank->size;
1824                 bank->sectors[sector].is_erased = -1;
1825                 bank->sectors[sector].is_protected = -1;
1826         }
1827         else
1828         {
1829                 for (i = 0; i < cfi_info->num_erase_regions; i++)
1830                 {
1831                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
1832                 }
1833
1834                 bank->num_sectors = num_sectors;
1835                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
1836
1837                 for (i = 0; i < cfi_info->num_erase_regions; i++)
1838                 {
1839                         int j;
1840                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
1841                         {
1842                                 bank->sectors[sector].offset = offset;
1843                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
1844                                 offset += bank->sectors[sector].size;
1845                                 bank->sectors[sector].is_erased = -1;
1846                                 bank->sectors[sector].is_protected = -1;
1847                                 sector++;
1848                         }
1849                 }
1850         }
1851
1852         return ERROR_OK;
1853 }
1854
1855 int cfi_erase_check(struct flash_bank_s *bank)
1856 {
1857         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1858         target_t *target = cfi_info->target;
1859         int i;
1860         int retval;
1861
1862         if (!cfi_info->erase_check_algorithm)
1863         {
1864                 u32 erase_check_code[] =
1865                 {
1866                         0xe4d03001,     /* ldrb r3, [r0], #1    */
1867                         0xe0022003, /* and r2, r2, r3           */
1868                         0xe2511001, /* subs r1, r1, #1          */
1869                         0x1afffffb,     /* b -4                                 */
1870                         0xeafffffe      /* b 0                                  */
1871                 };
1872
1873                 /* make sure we have a working area */
1874                 if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
1875                 {
1876                         WARNING("no working area available, falling back to slow memory reads");
1877                 }
1878                 else
1879                 {
1880                         u8 erase_check_code_buf[5 * 4];
1881
1882                         for (i = 0; i < 5; i++)
1883                                 target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
1884
1885                         /* write algorithm code to working area */
1886                         target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
1887                 }
1888         }
1889
1890         if (!cfi_info->erase_check_algorithm)
1891         {
1892                 u32 *buffer = malloc(4096);
1893
1894                 for (i = 0; i < bank->num_sectors; i++)
1895                 {
1896                         u32 address = bank->base + bank->sectors[i].offset;
1897                         u32 size = bank->sectors[i].size;
1898                         u32 check = 0xffffffffU;
1899                         int erased = 1;
1900
1901                         while (size > 0)
1902                         {
1903                                 u32 thisrun_size = (size > 4096) ? 4096 : size;
1904                                 int j;
1905
1906                                 target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
1907
1908                                 for (j = 0; j < thisrun_size / 4; j++)
1909                                         check &= buffer[j];
1910
1911                                 if (check != 0xffffffff)
1912                                 {
1913                                         erased = 0;
1914                                         break;
1915                                 }
1916
1917                                 size -= thisrun_size;
1918                                 address += thisrun_size;
1919                         }
1920
1921                         bank->sectors[i].is_erased = erased;
1922                 }
1923
1924                 free(buffer);
1925         }
1926         else
1927         {
1928                 for (i = 0; i < bank->num_sectors; i++)
1929                 {
1930                         u32 address = bank->base + bank->sectors[i].offset;
1931                         u32 size = bank->sectors[i].size;
1932
1933                         reg_param_t reg_params[3];
1934                         armv4_5_algorithm_t armv4_5_info;
1935
1936                         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1937                         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1938                         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1939
1940                         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1941                         buf_set_u32(reg_params[0].value, 0, 32, address);
1942
1943                         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1944                         buf_set_u32(reg_params[1].value, 0, 32, size);
1945
1946                         init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1947                         buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1948
1949                         if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
1950                                 return ERROR_FLASH_OPERATION_FAILED;
1951
1952                         if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
1953                                 bank->sectors[i].is_erased = 1;
1954                         else
1955                                 bank->sectors[i].is_erased = 0;
1956
1957                         destroy_reg_param(&reg_params[0]);
1958                         destroy_reg_param(&reg_params[1]);
1959                         destroy_reg_param(&reg_params[2]);
1960                 }
1961         }
1962
1963         return ERROR_OK;
1964 }
1965
1966 int cfi_intel_protect_check(struct flash_bank_s *bank)
1967 {
1968         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1969         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
1970         target_t *target = cfi_info->target;
1971         u8 command[CFI_MAX_BUS_WIDTH];
1972         int i;
1973
1974         /* check if block lock bits are supported on this device */
1975         if (!(pri_ext->blk_status_reg_mask & 0x1))
1976                 return ERROR_FLASH_OPERATION_FAILED;
1977
1978         cfi_command(bank, 0x90, command);
1979         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1980
1981         for (i = 0; i < bank->num_sectors; i++)
1982         {
1983                 u8 block_status = cfi_get_u8(bank, i, 0x2);
1984
1985                 if (block_status & 1)
1986                         bank->sectors[i].is_protected = 1;
1987                 else
1988                         bank->sectors[i].is_protected = 0;
1989         }
1990
1991         cfi_command(bank, 0xff, command);
1992         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1993
1994         return ERROR_OK;
1995 }
1996
1997 int cfi_spansion_protect_check(struct flash_bank_s *bank)
1998 {
1999         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2000         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2001         target_t *target = cfi_info->target;
2002         u8 command[8];
2003         int i;
2004
2005         cfi_command(bank, 0xaa, command);
2006         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2007
2008         cfi_command(bank, 0x55, command);
2009         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2010
2011         cfi_command(bank, 0x90, command);
2012         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2013
2014         for (i = 0; i < bank->num_sectors; i++)
2015         {
2016                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2017
2018                 if (block_status & 1)
2019                         bank->sectors[i].is_protected = 1;
2020                 else
2021                         bank->sectors[i].is_protected = 0;
2022         }
2023
2024         cfi_command(bank, 0xf0, command);
2025         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2026
2027         return ERROR_OK;
2028 }
2029
2030 int cfi_protect_check(struct flash_bank_s *bank)
2031 {
2032         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2033
2034         if (cfi_info->qry[0] != 'Q')
2035                 return ERROR_FLASH_BANK_NOT_PROBED;
2036
2037         switch(cfi_info->pri_id)
2038         {
2039                 case 1:
2040                 case 3:
2041                         return cfi_intel_protect_check(bank);
2042                         break;
2043                 case 2:
2044                         return cfi_spansion_protect_check(bank);
2045                         break;
2046                 default:
2047                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2048                         break;
2049         }
2050
2051         return ERROR_OK;
2052 }
2053
2054 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2055 {
2056         int printed;
2057         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2058
2059         if (cfi_info->qry[0] == -1)
2060         {
2061                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2062                 return ERROR_OK;
2063         }
2064
2065         printed = snprintf(buf, buf_size, "\ncfi information:\n");
2066         buf += printed;
2067         buf_size -= printed;
2068
2069         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2070                 cfi_info->manufacturer, cfi_info->device_id);
2071         buf += printed;
2072         buf_size -= printed;
2073
2074         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2075         buf += printed;
2076         buf_size -= printed;
2077
2078         printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2079         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2080         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2081         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2082         buf += printed;
2083         buf_size -= printed;
2084
2085         printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2086                   1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2087         buf += printed;
2088         buf_size -= printed;
2089
2090         printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2091                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2092                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2093                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2094         buf += printed;
2095         buf_size -= printed;
2096
2097         printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size);
2098         buf += printed;
2099         buf_size -= printed;
2100
2101         switch(cfi_info->pri_id)
2102         {
2103                 case 1:
2104                 case 3:
2105                         cfi_intel_info(bank, buf, buf_size);
2106                         break;
2107                 case 2:
2108                         cfi_spansion_info(bank, buf, buf_size);
2109                         break;
2110                 default:
2111                         ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2112                         break;
2113         }
2114
2115         return ERROR_OK;
2116 }