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   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28 #include "armv4_5.h"
  29 #include "binarybuffer.h"
  30
  31
  32 #define CFI_MAX_BUS_WIDTH       4
  33 #define CFI_MAX_CHIP_WIDTH      4
  34
  35 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  36 #define CFI_MAX_INTEL_CODESIZE 256
  37
  38 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
  39 {
  40         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  41         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  42 };
  43
  44 /* CFI fixups foward declarations */
  45 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  46 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  47 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  48
  49 /* fixup after reading cmdset 0002 primary query table */
  50 static const struct cfi_fixup cfi_0002_fixups[] = {
  51         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  52         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  53         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  54         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  55         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  56         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  57         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  58         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  59         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  60         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  61         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  62         {0, 0, NULL, NULL}
  63 };
  64
  65 /* fixup after reading cmdset 0001 primary query table */
  66 static const struct cfi_fixup cfi_0001_fixups[] = {
  67         {0, 0, NULL, NULL}
  68 };
  69
  70 static void cfi_fixup(flash_bank_t *bank, const struct cfi_fixup *fixups)
  71 {
  72         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  73         const struct cfi_fixup *f;
  74
  75         for (f = fixups; f->fixup; f++)
  76         {
  77                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
  78                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
  79                 {
  80                         f->fixup(bank, f->param);
  81                 }
  82         }
  83 }
  84
  85 /* inline uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset) */
  86 static __inline__ uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset)
  87 {
  88         struct cfi_flash_bank *cfi_info = bank->driver_priv;
  89
  90         if (cfi_info->x16_as_x8) offset *= 2;
  91
  92         /* while the sector list isn't built, only accesses to sector 0 work */
  93         if (sector == 0)
  94                 return bank->base + offset * bank->bus_width;
  95         else
  96         {
  97                 if (!bank->sectors)
  98                 {
  99                         LOG_ERROR("BUG: sector list not yet built");
 100                         exit(-1);
 101                 }
 102                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 103         }
 104
 105 }
 106
 107 static void cfi_command(flash_bank_t *bank, uint8_t cmd, uint8_t *cmd_buf)
 108 {
 109         int i;
 110
 111         /* clear whole buffer, to ensure bits that exceed the bus_width
 112          * are set to zero
 113          */
 114         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 115                 cmd_buf[i] = 0;
 116
 117         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 118         {
 119                 for (i = bank->bus_width; i > 0; i--)
 120                 {
 121                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 122                 }
 123         }
 124         else
 125         {
 126                 for (i = 1; i <= bank->bus_width; i++)
 127                 {
 128                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 129                 }
 130         }
 131 }
 132
 133 /* read unsigned 8-bit value from the bank
 134  * flash banks are expected to be made of similar chips
 135  * the query result should be the same for all
 136  */
 137 static uint8_t cfi_query_u8(flash_bank_t *bank, int sector, uint32_t offset)
 138 {
 139         struct target *target = bank->target;
 140         uint8_t data[CFI_MAX_BUS_WIDTH];
 141
 142         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 143
 144         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 145                 return data[0];
 146         else
 147                 return data[bank->bus_width - 1];
 148 }
 149
 150 /* read unsigned 8-bit value from the bank
 151  * in case of a bank made of multiple chips,
 152  * the individual values are ORed
 153  */
 154 static uint8_t cfi_get_u8(flash_bank_t *bank, int sector, uint32_t offset)
 155 {
 156         struct target *target = bank->target;
 157         uint8_t data[CFI_MAX_BUS_WIDTH];
 158         int i;
 159
 160         target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 161
 162         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 163         {
 164                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 165                         data[0] |= data[i];
 166
 167                 return data[0];
 168         }
 169         else
 170         {
 171                 uint8_t value = 0;
 172                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 173                         value |= data[bank->bus_width - 1 - i];
 174
 175                 return value;
 176         }
 177 }
 178
 179 static uint16_t cfi_query_u16(flash_bank_t *bank, int sector, uint32_t offset)
 180 {
 181         struct target *target = bank->target;
 182         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 183         uint8_t data[CFI_MAX_BUS_WIDTH * 2];
 184
 185         if (cfi_info->x16_as_x8)
 186         {
 187                 uint8_t i;
 188                 for (i = 0;i < 2;i++)
 189                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 190                                 &data[i*bank->bus_width]);
 191         }
 192         else
 193                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 194
 195         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 196                 return data[0] | data[bank->bus_width] << 8;
 197         else
 198                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 199 }
 200
 201 static uint32_t cfi_query_u32(flash_bank_t *bank, int sector, uint32_t offset)
 202 {
 203         struct target *target = bank->target;
 204         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 205         uint8_t data[CFI_MAX_BUS_WIDTH * 4];
 206
 207         if (cfi_info->x16_as_x8)
 208         {
 209                 uint8_t i;
 210                 for (i = 0;i < 4;i++)
 211                         target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
 212                                 &data[i*bank->bus_width]);
 213         }
 214         else
 215                 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 216
 217         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 218                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 219         else
 220                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 221                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 222 }
 223
 224 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 225 {
 226         struct target *target = bank->target;
 227         uint8_t command[8];
 228
 229         if (target->state != TARGET_HALTED)
 230         {
 231                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 232                 exit(-1);
 233         }
 234
 235         cfi_command(bank, 0x50, command);
 236         target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 237 }
 238
 239 uint8_t cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 240 {
 241         uint8_t status;
 242
 243         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 244         {
 245                 LOG_DEBUG("status: 0x%x", status);
 246                 alive_sleep(1);
 247         }
 248
 249         /* mask out bit 0 (reserved) */
 250         status = status & 0xfe;
 251
 252         LOG_DEBUG("status: 0x%x", status);
 253
 254         if ((status & 0x80) != 0x80)
 255         {
 256                 LOG_ERROR("timeout while waiting for WSM to become ready");
 257         }
 258         else if (status != 0x80)
 259         {
 260                 LOG_ERROR("status register: 0x%x", status);
 261                 if (status & 0x2)
 262                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 263                 if (status & 0x4)
 264                         LOG_ERROR("Program suspended");
 265                 if (status & 0x8)
 266                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 267                 if (status & 0x10)
 268                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 269                 if (status & 0x20)
 270                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 271                 if (status & 0x40)
 272                         LOG_ERROR("Block Erase Suspended");
 273
 274                 cfi_intel_clear_status_register(bank);
 275         }
 276
 277         return status;
 278 }
 279
 280 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 281 {
 282         uint8_t status, oldstatus;
 283         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 284
 285         oldstatus = cfi_get_u8(bank, 0, 0x0);
 286
 287         do {
 288                 status = cfi_get_u8(bank, 0, 0x0);
 289                 if ((status ^ oldstatus) & 0x40) {
 290                         if (status & cfi_info->status_poll_mask & 0x20) {
 291                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 292                                 status = cfi_get_u8(bank, 0, 0x0);
 293                                 if ((status ^ oldstatus) & 0x40) {
 294                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 295                                         return(ERROR_FLASH_OPERATION_FAILED);
 296                                 } else {
 297                                         LOG_DEBUG("status: 0x%x", status);
 298                                         return(ERROR_OK);
 299                                 }
 300                         }
 301                 } else { /* no toggle: finished, OK */
 302                         LOG_DEBUG("status: 0x%x", status);
 303                         return(ERROR_OK);
 304                 }
 305
 306                 oldstatus = status;
 307                 alive_sleep(1);
 308         } while (timeout-- > 0);
 309
 310         LOG_ERROR("timeout, status: 0x%x", status);
 311
 312         return(ERROR_FLASH_BUSY);
 313 }
 314
 315 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 316 {
 317         int retval;
 318         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 319         struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 320         struct target *target = bank->target;
 321         uint8_t command[8];
 322
 323         cfi_info->pri_ext = pri_ext;
 324
 325         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 326         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 327         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 328
 329         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 330         {
 331                 cfi_command(bank, 0xf0, command);
 332                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 333                 {
 334                         return retval;
 335                 }
 336                 cfi_command(bank, 0xff, command);
 337                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 338                 {
 339                         return retval;
 340                 }
 341                 LOG_ERROR("Could not read bank flash bank information");
 342                 return ERROR_FLASH_BANK_INVALID;
 343         }
 344
 345         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 346         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 347
 348         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 349
 350         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 351         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 352         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 353
 354         LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
 355                   pri_ext->feature_support,
 356                   pri_ext->suspend_cmd_support,
 357                   pri_ext->blk_status_reg_mask);
 358
 359         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 360         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 361
 362         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 363                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 364                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 365
 366         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 367         if (pri_ext->num_protection_fields != 1)
 368         {
 369                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 370         }
 371
 372         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 373         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 374         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 375
 376         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 382 {
 383         int retval;
 384         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 385         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 386         struct target *target = bank->target;
 387         uint8_t command[8];
 388
 389         cfi_info->pri_ext = pri_ext;
 390
 391         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 392         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 393         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 394
 395         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 396         {
 397                 cfi_command(bank, 0xf0, command);
 398                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 399                 {
 400                         return retval;
 401                 }
 402                 LOG_ERROR("Could not read spansion bank information");
 403                 return ERROR_FLASH_BANK_INVALID;
 404         }
 405
 406         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 407         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 408
 409         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 410
 411         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 412         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 413         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 414         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 415         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 416         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 417         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 418         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 419         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 420         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 421         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 422
 423         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 424               pri_ext->EraseSuspend, pri_ext->BlkProt);
 425
 426         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 427               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 428
 429         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 430
 431
 432         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 433                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 434                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 435
 436         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 437
 438         /* default values for implementation specific workarounds */
 439         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 440         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 441         pri_ext->_reversed_geometry = 0;
 442
 443         return ERROR_OK;
 444 }
 445
 446 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 447 {
 448         int retval;
 449         struct cfi_atmel_pri_ext atmel_pri_ext;
 450         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 451         struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 452         struct target *target = bank->target;
 453         uint8_t command[8];
 454
 455         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 456          * but a different primary extended query table.
 457          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 458          */
 459
 460         memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
 461
 462         cfi_info->pri_ext = pri_ext;
 463
 464         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 465         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 466         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 467
 468         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 469         {
 470                 cfi_command(bank, 0xf0, command);
 471                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 472                 {
 473                         return retval;
 474                 }
 475                 LOG_ERROR("Could not read atmel bank information");
 476                 return ERROR_FLASH_BANK_INVALID;
 477         }
 478
 479         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 480         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 481         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 482
 483         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 484         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 485
 486         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 487
 488         pri_ext->major_version = atmel_pri_ext.major_version;
 489         pri_ext->minor_version = atmel_pri_ext.minor_version;
 490
 491         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 492         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 493         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 494         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 495
 496         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 497                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 498
 499         if (atmel_pri_ext.features & 0x02)
 500                 pri_ext->EraseSuspend = 2;
 501
 502         if (atmel_pri_ext.bottom_boot)
 503                 pri_ext->TopBottom = 2;
 504         else
 505                 pri_ext->TopBottom = 3;
 506
 507         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 508         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 509
 510         return ERROR_OK;
 511 }
 512
 513 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 514 {
 515         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 516
 517         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 518         {
 519                 return cfi_read_atmel_pri_ext(bank);
 520         }
 521         else
 522         {
 523                 return cfi_read_spansion_pri_ext(bank);
 524         }
 525 }
 526
 527 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 528 {
 529         int printed;
 530         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 531         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 532
 533         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 534         buf += printed;
 535         buf_size -= printed;
 536
 537         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 538                            pri_ext->pri[1], pri_ext->pri[2],
 539                            pri_ext->major_version, pri_ext->minor_version);
 540         buf += printed;
 541         buf_size -= printed;
 542
 543         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 544                            (pri_ext->SiliconRevision) >> 2,
 545                            (pri_ext->SiliconRevision) & 0x03);
 546         buf += printed;
 547         buf_size -= printed;
 548
 549         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 550                            pri_ext->EraseSuspend,
 551                            pri_ext->BlkProt);
 552         buf += printed;
 553         buf_size -= printed;
 554
 555         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 556                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 557                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 558
 559         return ERROR_OK;
 560 }
 561
 562 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 563 {
 564         int printed;
 565         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 566         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 567
 568         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 569         buf += printed;
 570         buf_size -= printed;
 571
 572         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 573         buf += printed;
 574         buf_size -= printed;
 575
 576         printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 577         buf += printed;
 578         buf_size -= printed;
 579
 580         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 581                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 582                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 583         buf += printed;
 584         buf_size -= printed;
 585
 586         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 587
 588         return ERROR_OK;
 589 }
 590
 591 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 592 {
 593         /*command_t *cfi_cmd = */
 594         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 595         /*
 596         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 597                                          "print part id of cfi flash bank <num>");
 598         */
 599         return ERROR_OK;
 600 }
 601
 602 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 603  */
 604 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
 605 {
 606         struct cfi_flash_bank *cfi_info;
 607
 608         if (argc < 6)
 609         {
 610                 LOG_WARNING("incomplete flash_bank cfi configuration");
 611                 return ERROR_FLASH_BANK_INVALID;
 612         }
 613
 614         uint16_t chip_width, bus_width;
 615         COMMAND_PARSE_NUMBER(u16, args[3], bus_width);
 616         COMMAND_PARSE_NUMBER(u16, args[4], chip_width);
 617
 618         if ((chip_width > CFI_MAX_CHIP_WIDTH)
 619                         || (bus_width > CFI_MAX_BUS_WIDTH))
 620         {
 621                 LOG_ERROR("chip and bus width have to specified in bytes");
 622                 return ERROR_FLASH_BANK_INVALID;
 623         }
 624
 625         cfi_info = malloc(sizeof(struct cfi_flash_bank));
 626         cfi_info->probed = 0;
 627         bank->driver_priv = cfi_info;
 628
 629         cfi_info->write_algorithm = NULL;
 630
 631         cfi_info->x16_as_x8 = 0;
 632         cfi_info->jedec_probe = 0;
 633         cfi_info->not_cfi = 0;
 634
 635         for (unsigned i = 6; i < argc; i++)
 636         {
 637                 if (strcmp(args[i], "x16_as_x8") == 0)
 638                 {
 639                         cfi_info->x16_as_x8 = 1;
 640                 }
 641                 else if (strcmp(args[i], "jedec_probe") == 0)
 642                 {
 643                         cfi_info->jedec_probe = 1;
 644                 }
 645         }
 646
 647         cfi_info->write_algorithm = NULL;
 648
 649         /* bank wasn't probed yet */
 650         cfi_info->qry[0] = -1;
 651
 652         return ERROR_OK;
 653 }
 654
 655 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 656 {
 657         int retval;
 658         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 659         struct target *target = bank->target;
 660         uint8_t command[8];
 661         int i;
 662
 663         cfi_intel_clear_status_register(bank);
 664
 665         for (i = first; i <= last; i++)
 666         {
 667                 cfi_command(bank, 0x20, command);
 668                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 669                 {
 670                         return retval;
 671                 }
 672
 673                 cfi_command(bank, 0xd0, command);
 674                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 675                 {
 676                         return retval;
 677                 }
 678
 679                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 680                         bank->sectors[i].is_erased = 1;
 681                 else
 682                 {
 683                         cfi_command(bank, 0xff, command);
 684                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 685                         {
 686                                 return retval;
 687                         }
 688
 689                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
 690                         return ERROR_FLASH_OPERATION_FAILED;
 691                 }
 692         }
 693
 694         cfi_command(bank, 0xff, command);
 695         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 696
 697 }
 698
 699 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 700 {
 701         int retval;
 702         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 703         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 704         struct target *target = bank->target;
 705         uint8_t command[8];
 706         int i;
 707
 708         for (i = first; i <= last; i++)
 709         {
 710                 cfi_command(bank, 0xaa, command);
 711                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 712                 {
 713                         return retval;
 714                 }
 715
 716                 cfi_command(bank, 0x55, command);
 717                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 718                 {
 719                         return retval;
 720                 }
 721
 722                 cfi_command(bank, 0x80, command);
 723                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 724                 {
 725                         return retval;
 726                 }
 727
 728                 cfi_command(bank, 0xaa, command);
 729                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 730                 {
 731                         return retval;
 732                 }
 733
 734                 cfi_command(bank, 0x55, command);
 735                 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 736                 {
 737                         return retval;
 738                 }
 739
 740                 cfi_command(bank, 0x30, command);
 741                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 742                 {
 743                         return retval;
 744                 }
 745
 746                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 747                         bank->sectors[i].is_erased = 1;
 748                 else
 749                 {
 750                         cfi_command(bank, 0xf0, command);
 751                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 752                         {
 753                                 return retval;
 754                         }
 755
 756                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
 757                         return ERROR_FLASH_OPERATION_FAILED;
 758                 }
 759         }
 760
 761         cfi_command(bank, 0xf0, command);
 762         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 763 }
 764
 765 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 766 {
 767         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 768
 769         if (bank->target->state != TARGET_HALTED)
 770         {
 771                 LOG_ERROR("Target not halted");
 772                 return ERROR_TARGET_NOT_HALTED;
 773         }
 774
 775         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 776         {
 777                 return ERROR_FLASH_SECTOR_INVALID;
 778         }
 779
 780         if (cfi_info->qry[0] != 'Q')
 781                 return ERROR_FLASH_BANK_NOT_PROBED;
 782
 783         switch (cfi_info->pri_id)
 784         {
 785                 case 1:
 786                 case 3:
 787                         return cfi_intel_erase(bank, first, last);
 788                         break;
 789                 case 2:
 790                         return cfi_spansion_erase(bank, first, last);
 791                         break;
 792                 default:
 793                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 794                         break;
 795         }
 796
 797         return ERROR_OK;
 798 }
 799
 800 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 801 {
 802         int retval;
 803         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 804         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
 805         struct target *target = bank->target;
 806         uint8_t command[8];
 807         int retry = 0;
 808         int i;
 809
 810         /* if the device supports neither legacy lock/unlock (bit 3) nor
 811          * instant individual block locking (bit 5).
 812          */
 813         if (!(pri_ext->feature_support & 0x28))
 814                 return ERROR_FLASH_OPERATION_FAILED;
 815
 816         cfi_intel_clear_status_register(bank);
 817
 818         for (i = first; i <= last; i++)
 819         {
 820                 cfi_command(bank, 0x60, command);
 821                 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 822                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 823                 {
 824                         return retval;
 825                 }
 826                 if (set)
 827                 {
 828                         cfi_command(bank, 0x01, command);
 829                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 830                         if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 831                         {
 832                                 return retval;
 833                         }
 834                         bank->sectors[i].is_protected = 1;
 835                 }
 836                 else
 837                 {
 838                         cfi_command(bank, 0xd0, command);
 839                         LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 840                         if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 841                         {
 842                                 return retval;
 843                         }
 844                         bank->sectors[i].is_protected = 0;
 845                 }
 846
 847                 /* instant individual block locking doesn't require reading of the status register */
 848                 if (!(pri_ext->feature_support & 0x20))
 849                 {
 850                         /* Clear lock bits operation may take up to 1.4s */
 851                         cfi_intel_wait_status_busy(bank, 1400);
 852                 }
 853                 else
 854                 {
 855                         uint8_t block_status;
 856                         /* read block lock bit, to verify status */
 857                         cfi_command(bank, 0x90, command);
 858                         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 859                         {
 860                                 return retval;
 861                         }
 862                         block_status = cfi_get_u8(bank, i, 0x2);
 863
 864                         if ((block_status & 0x1) != set)
 865                         {
 866                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 867                                 cfi_command(bank, 0x70, command);
 868                                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 869                                 {
 870                                         return retval;
 871                                 }
 872                                 cfi_intel_wait_status_busy(bank, 10);
 873
 874                                 if (retry > 10)
 875                                         return ERROR_FLASH_OPERATION_FAILED;
 876                                 else
 877                                 {
 878                                         i--;
 879                                         retry++;
 880                                 }
 881                         }
 882                 }
 883         }
 884
 885         /* if the device doesn't support individual block lock bits set/clear,
 886          * all blocks have been unlocked in parallel, so we set those that should be protected
 887          */
 888         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 889         {
 890                 for (i = 0; i < bank->num_sectors; i++)
 891                 {
 892                         if (bank->sectors[i].is_protected == 1)
 893                         {
 894                                 cfi_intel_clear_status_register(bank);
 895
 896                                 cfi_command(bank, 0x60, command);
 897                                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 898                                 {
 899                                         return retval;
 900                                 }
 901
 902                                 cfi_command(bank, 0x01, command);
 903                                 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 904                                 {
 905                                         return retval;
 906                                 }
 907
 908                                 cfi_intel_wait_status_busy(bank, 100);
 909                         }
 910                 }
 911         }
 912
 913         cfi_command(bank, 0xff, command);
 914         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 915 }
 916
 917 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 918 {
 919         struct cfi_flash_bank *cfi_info = bank->driver_priv;
 920
 921         if (bank->target->state != TARGET_HALTED)
 922         {
 923                 LOG_ERROR("Target not halted");
 924                 return ERROR_TARGET_NOT_HALTED;
 925         }
 926
 927         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 928         {
 929                 return ERROR_FLASH_SECTOR_INVALID;
 930         }
 931
 932         if (cfi_info->qry[0] != 'Q')
 933                 return ERROR_FLASH_BANK_NOT_PROBED;
 934
 935         switch (cfi_info->pri_id)
 936         {
 937                 case 1:
 938                 case 3:
 939                         cfi_intel_protect(bank, set, first, last);
 940                         break;
 941                 default:
 942                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 943                         break;
 944         }
 945
 946         return ERROR_OK;
 947 }
 948
 949 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 950 static void cfi_add_byte(struct flash_bank_s *bank, uint8_t *word, uint8_t byte)
 951 {
 952         /* struct target *target = bank->target; */
 953
 954         int i;
 955
 956         /* NOTE:
 957          * The data to flash must not be changed in endian! We write a bytestrem in
 958          * target byte order already. Only the control and status byte lane of the flash
 959          * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
 960          * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
 961          */
 962
 963 #if 0
 964         if (target->endianness == TARGET_LITTLE_ENDIAN)
 965         {
 966 #endif
 967                 /* shift bytes */
 968                 for (i = 0; i < bank->bus_width - 1; i++)
 969                         word[i] = word[i + 1];
 970                 word[bank->bus_width - 1] = byte;
 971 #if 0
 972         }
 973         else
 974         {
 975                 /* shift bytes */
 976                 for (i = bank->bus_width - 1; i > 0; i--)
 977                         word[i] = word[i - 1];
 978                 word[0] = byte;
 979         }
 980 #endif
 981 }
 982
 983 /* Convert code image to target endian */
 984 /* FIXME create general block conversion fcts in target.c?) */
 985 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
 986 {
 987         uint32_t i;
 988         for (i = 0; i< count; i++)
 989         {
 990                 target_buffer_set_u32(target, dest, *src);
 991                 dest += 4;
 992                 src++;
 993         }
 994 }
 995
 996 static uint32_t cfi_command_val(flash_bank_t *bank, uint8_t cmd)
 997 {
 998         struct target *target = bank->target;
 999
1000         uint8_t buf[CFI_MAX_BUS_WIDTH];
1001         cfi_command(bank, cmd, buf);
1002         switch (bank->bus_width)
1003         {
1004         case 1 :
1005                 return buf[0];
1006                 break;
1007         case 2 :
1008                 return target_buffer_get_u16(target, buf);
1009                 break;
1010         case 4 :
1011                 return target_buffer_get_u32(target, buf);
1012                 break;
1013         default :
1014                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1015                 return 0;
1016         }
1017 }
1018
1019 static int cfi_intel_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1020 {
1021         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1022         struct target *target = bank->target;
1023         struct reg_param reg_params[7];
1024         struct armv4_5_algorithm armv4_5_info;
1025         struct working_area *source;
1026         uint32_t buffer_size = 32768;
1027         uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1028
1029         /* algorithm register usage:
1030          * r0: source address (in RAM)
1031          * r1: target address (in Flash)
1032          * r2: count
1033          * r3: flash write command
1034          * r4: status byte (returned to host)
1035          * r5: busy test pattern
1036          * r6: error test pattern
1037          */
1038
1039         static const uint32_t word_32_code[] = {
1040                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1041                 0xe5813000,   /*                str r3, [r1] */
1042                 0xe5814000,   /*                str r4, [r1] */
1043                 0xe5914000,   /* busy:  ldr r4, [r1] */
1044                 0xe0047005,   /*                and r7, r4, r5 */
1045                 0xe1570005,   /*                cmp r7, r5 */
1046                 0x1afffffb,   /*                bne busy */
1047                 0xe1140006,   /*                tst r4, r6 */
1048                 0x1a000003,   /*                bne done */
1049                 0xe2522001,   /*                subs r2, r2, #1 */
1050                 0x0a000001,   /*                beq done */
1051                 0xe2811004,   /*                add r1, r1 #4 */
1052                 0xeafffff2,   /*                b loop */
1053                 0xeafffffe    /* done:  b -2 */
1054         };
1055
1056         static const uint32_t word_16_code[] = {
1057                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1058                 0xe1c130b0,   /*                strh r3, [r1] */
1059                 0xe1c140b0,   /*                strh r4, [r1] */
1060                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1061                 0xe0047005,   /*                and r7, r4, r5 */
1062                 0xe1570005,   /*                cmp r7, r5 */
1063                 0x1afffffb,   /*                bne busy */
1064                 0xe1140006,   /*                tst r4, r6 */
1065                 0x1a000003,   /*                bne done */
1066                 0xe2522001,   /*                subs r2, r2, #1 */
1067                 0x0a000001,   /*                beq done */
1068                 0xe2811002,   /*                add r1, r1 #2 */
1069                 0xeafffff2,   /*                b loop */
1070                 0xeafffffe    /* done:  b -2 */
1071         };
1072
1073         static const uint32_t word_8_code[] = {
1074                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1075                 0xe5c13000,   /*                strb r3, [r1] */
1076                 0xe5c14000,   /*                strb r4, [r1] */
1077                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1078                 0xe0047005,   /*                and r7, r4, r5 */
1079                 0xe1570005,   /*                cmp r7, r5 */
1080                 0x1afffffb,   /*                bne busy */
1081                 0xe1140006,   /*                tst r4, r6 */
1082                 0x1a000003,   /*                bne done */
1083                 0xe2522001,   /*                subs r2, r2, #1 */
1084                 0x0a000001,   /*                beq done */
1085                 0xe2811001,   /*                add r1, r1 #1 */
1086                 0xeafffff2,   /*                b loop */
1087                 0xeafffffe    /* done:  b -2 */
1088         };
1089         uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1090         const uint32_t *target_code_src;
1091         uint32_t target_code_size;
1092         int retval = ERROR_OK;
1093
1094
1095         cfi_intel_clear_status_register(bank);
1096
1097         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1098         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1099         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1100
1101         /* If we are setting up the write_algorith, we need target_code_src */
1102         /* if not we only need target_code_size. */
1103
1104         /* However, we don't want to create multiple code paths, so we */
1105         /* do the unecessary evaluation of target_code_src, which the */
1106         /* compiler will probably nicely optimize away if not needed */
1107
1108         /* prepare algorithm code for target endian */
1109         switch (bank->bus_width)
1110         {
1111         case 1 :
1112                 target_code_src = word_8_code;
1113                 target_code_size = sizeof(word_8_code);
1114                 break;
1115         case 2 :
1116                 target_code_src = word_16_code;
1117                 target_code_size = sizeof(word_16_code);
1118                 break;
1119         case 4 :
1120                 target_code_src = word_32_code;
1121                 target_code_size = sizeof(word_32_code);
1122                 break;
1123         default:
1124                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1125                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126         }
1127
1128         /* flash write code */
1129         if (!cfi_info->write_algorithm)
1130         {
1131                 if (target_code_size > sizeof(target_code))
1132                 {
1133                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1134                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1135                 }
1136                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1137
1138                 /* Get memory for block write handler */
1139                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1140                 if (retval != ERROR_OK)
1141                 {
1142                         LOG_WARNING("No working area available, can't do block memory writes");
1143                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1144                 };
1145
1146                 /* write algorithm code to working area */
1147                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1148                 if (retval != ERROR_OK)
1149                 {
1150                         LOG_ERROR("Unable to write block write code to target");
1151                         goto cleanup;
1152                 }
1153         }
1154
1155         /* Get a workspace buffer for the data to flash starting with 32k size.
1156            Half size until buffer would be smaller 256 Bytem then fail back */
1157         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1158         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1159         {
1160                 buffer_size /= 2;
1161                 if (buffer_size <= 256)
1162                 {
1163                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1164                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1165                         goto cleanup;
1166                 }
1167         };
1168
1169         /* setup algo registers */
1170         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1171         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1172         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1173         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1174         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1175         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1176         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1177
1178         /* prepare command and status register patterns */
1179         write_command_val = cfi_command_val(bank, 0x40);
1180         busy_pattern_val  = cfi_command_val(bank, 0x80);
1181         error_pattern_val = cfi_command_val(bank, 0x7e);
1182
1183         LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1184
1185         /* Programming main loop */
1186         while (count > 0)
1187         {
1188                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1189                 uint32_t wsm_error;
1190
1191                 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1192                 {
1193                         goto cleanup;
1194                 }
1195
1196                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1197                 buf_set_u32(reg_params[1].value, 0, 32, address);
1198                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1199
1200                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1201                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1202                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1203
1204                 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1205
1206                 /* Execute algorithm, assume breakpoint for last instruction */
1207                 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1208                         cfi_info->write_algorithm->address,
1209                         cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1210                         10000, /* 10s should be enough for max. 32k of data */
1211                         &armv4_5_info);
1212
1213                 /* On failure try a fall back to direct word writes */
1214                 if (retval != ERROR_OK)
1215                 {
1216                         cfi_intel_clear_status_register(bank);
1217                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1218                         retval = ERROR_FLASH_OPERATION_FAILED;
1219                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1220                         /* FIXME To allow fall back or recovery, we must save the actual status
1221                            somewhere, so that a higher level code can start recovery. */
1222                         goto cleanup;
1223                 }
1224
1225                 /* Check return value from algo code */
1226                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1227                 if (wsm_error)
1228                 {
1229                         /* read status register (outputs debug inforation) */
1230                         cfi_intel_wait_status_busy(bank, 100);
1231                         cfi_intel_clear_status_register(bank);
1232                         retval = ERROR_FLASH_OPERATION_FAILED;
1233                         goto cleanup;
1234                 }
1235
1236                 buffer += thisrun_count;
1237                 address += thisrun_count;
1238                 count -= thisrun_count;
1239         }
1240
1241         /* free up resources */
1242 cleanup:
1243         if (source)
1244                 target_free_working_area(target, source);
1245
1246         if (cfi_info->write_algorithm)
1247         {
1248                 target_free_working_area(target, cfi_info->write_algorithm);
1249                 cfi_info->write_algorithm = NULL;
1250         }
1251
1252         destroy_reg_param(&reg_params[0]);
1253         destroy_reg_param(&reg_params[1]);
1254         destroy_reg_param(&reg_params[2]);
1255         destroy_reg_param(&reg_params[3]);
1256         destroy_reg_param(&reg_params[4]);
1257         destroy_reg_param(&reg_params[5]);
1258         destroy_reg_param(&reg_params[6]);
1259
1260         return retval;
1261 }
1262
1263 static int cfi_spansion_write_block(struct flash_bank_s *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1264 {
1265         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1266         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1267         struct target *target = bank->target;
1268         struct reg_param reg_params[10];
1269         struct armv4_5_algorithm armv4_5_info;
1270         struct working_area *source;
1271         uint32_t buffer_size = 32768;
1272         uint32_t status;
1273         int retval, retvaltemp;
1274         int exit_code = ERROR_OK;
1275
1276         /* input parameters - */
1277         /*      R0 = source address */
1278         /*      R1 = destination address */
1279         /*      R2 = number of writes */
1280         /*      R3 = flash write command */
1281         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1282         /* output parameters - */
1283         /*      R5 = 0x80 ok 0x00 bad */
1284         /* temp registers - */
1285         /*      R6 = value read from flash to test status */
1286         /*      R7 = holding register */
1287         /* unlock registers - */
1288         /*  R8 = unlock1_addr */
1289         /*  R9 = unlock1_cmd */
1290         /*  R10 = unlock2_addr */
1291         /*  R11 = unlock2_cmd */
1292
1293         static const uint32_t word_32_code[] = {
1294                                                 /* 00008100 <sp_32_code>:               */
1295                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1296                 0xe5889000,     /* str  r9, [r8]                                */
1297                 0xe58ab000,     /* str  r11, [r10]                              */
1298                 0xe5883000,     /* str  r3, [r8]                                */
1299                 0xe5815000,     /* str  r5, [r1]                                */
1300                 0xe1a00000,     /* nop                                                  */
1301                                                 /*                                                              */
1302                                                 /* 00008110 <sp_32_busy>:               */
1303                 0xe5916000,     /* ldr  r6, [r1]                                */
1304                 0xe0257006,     /* eor  r7, r5, r6                              */
1305                 0xe0147007,     /* ands r7, r4, r7                              */
1306                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1307                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1308                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1309                 0xe5916000,     /* ldr  r6, [r1]                                */
1310                 0xe0257006,     /* eor  r7, r5, r6                              */
1311                 0xe0147007,     /* ands r7, r4, r7                              */
1312                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1313                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1314                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1315                                                 /*                                                              */
1316                                 /* 00008140 <sp_32_cont>:                               */
1317                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1318                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1319                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1320                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1321                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1322                                                 /*                                                              */
1323                                                 /* 00008154 <sp_32_done>:               */
1324                 0xeafffffe              /* b    8154 <sp_32_done>               */
1325                 };
1326
1327                 static const uint32_t word_16_code[] = {
1328                                 /* 00008158 <sp_16_code>:              */
1329                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1330                 0xe1c890b0,     /* strh r9, [r8]                                */
1331                 0xe1cab0b0,     /* strh r11, [r10]                              */
1332                 0xe1c830b0,     /* strh r3, [r8]                                */
1333                 0xe1c150b0,     /* strh r5, [r1]                       */
1334                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1335                                 /*                                     */
1336                                 /* 00008168 <sp_16_busy>:              */
1337                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1338                 0xe0257006,     /* eor  r7, r5, r6                     */
1339                 0xe0147007,     /* ands r7, r4, r7                     */
1340                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1341                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1342                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1343                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1344                 0xe0257006,     /* eor  r7, r5, r6                     */
1345                 0xe0147007,     /* ands r7, r4, r7                     */
1346                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1347                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1348                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1349                                 /*                                     */
1350                                 /* 00008198 <sp_16_cont>:              */
1351                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1352                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1353                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1354                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1355                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1356                                 /*                                     */
1357                                 /* 000081ac <sp_16_done>:              */
1358                 0xeafffffe      /* b    81ac <sp_16_done>              */
1359                 };
1360
1361                 static const uint32_t word_16_code_dq7only[] = {
1362                                 /* <sp_16_code>:                       */
1363                 0xe0d050b2,     /* ldrh r5, [r0], #2                   */
1364                 0xe1c890b0,     /* strh r9, [r8]                       */
1365                 0xe1cab0b0,     /* strh r11, [r10]                              */
1366                 0xe1c830b0,     /* strh r3, [r8]                                */
1367                 0xe1c150b0,     /* strh r5, [r1]                       */
1368                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1369                                 /*                                     */
1370                                 /* <sp_16_busy>:                       */
1371                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1372                 0xe0257006,     /* eor  r7, r5, r6                     */
1373                 0xe2177080,     /* ands r7, #0x80                      */
1374                 0x1afffffb,     /* bne  8168 <sp_16_busy>              */
1375                                 /*                                     */
1376                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1377                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1378                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1379                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1380                 0xeafffff0,     /* b    8158 <sp_16_code>              */
1381                                 /*                                     */
1382                                 /* 000081ac <sp_16_done>:              */
1383                 0xeafffffe      /* b    81ac <sp_16_done>              */
1384                 };
1385
1386                 static const uint32_t word_8_code[] = {
1387                                 /* 000081b0 <sp_16_code_end>:          */
1388                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1389                 0xe5c89000,     /* strb r9, [r8]                                */
1390                 0xe5cab000,     /* strb r11, [r10]                              */
1391                 0xe5c83000,     /* strb r3, [r8]                                */
1392                 0xe5c15000,     /* strb r5, [r1]                       */
1393                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1394                                 /*                                     */
1395                                 /* 000081c0 <sp_8_busy>:               */
1396                 0xe5d16000,     /* ldrb r6, [r1]                       */
1397                 0xe0257006,     /* eor  r7, r5, r6                     */
1398                 0xe0147007,     /* ands r7, r4, r7                     */
1399                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1400                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1401                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1402                 0xe5d16000,     /* ldrb r6, [r1]                       */
1403                 0xe0257006,     /* eor  r7, r5, r6                     */
1404                 0xe0147007,     /* ands r7, r4, r7                     */
1405                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1406                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1407                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1408                                 /*                                     */
1409                                 /* 000081f0 <sp_8_cont>:               */
1410                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1411                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1412                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1413                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1414                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1415                                 /*                                     */
1416                                 /* 00008204 <sp_8_done>:               */
1417                 0xeafffffe      /* b    8204 <sp_8_done>               */
1418         };
1419
1420         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1421         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1422         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1423
1424         int target_code_size;
1425         const uint32_t *target_code_src;
1426
1427         switch (bank->bus_width)
1428         {
1429         case 1 :
1430                 target_code_src = word_8_code;
1431                 target_code_size = sizeof(word_8_code);
1432                 break;
1433         case 2 :
1434                 /* Check for DQ5 support */
1435                 if( cfi_info->status_poll_mask & (1 << 5) )
1436                 {
1437                         target_code_src = word_16_code;
1438                         target_code_size = sizeof(word_16_code);
1439                 }
1440                 else
1441                 {
1442                         /* No DQ5 support. Use DQ7 DATA# polling only. */
1443                         target_code_src = word_16_code_dq7only;
1444                         target_code_size = sizeof(word_16_code_dq7only);
1445                 }
1446                 break;
1447         case 4 :
1448                 target_code_src = word_32_code;
1449                 target_code_size = sizeof(word_32_code);
1450                 break;
1451         default:
1452                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1453                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1454         }
1455
1456         /* flash write code */
1457         if (!cfi_info->write_algorithm)
1458         {
1459                 uint8_t *target_code;
1460
1461                 /* convert bus-width dependent algorithm code to correct endiannes */
1462                 target_code = malloc(target_code_size);
1463                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1464
1465                 /* allocate working area */
1466                 retval = target_alloc_working_area(target, target_code_size,
1467                                 &cfi_info->write_algorithm);
1468                 if (retval != ERROR_OK)
1469                 {
1470                         free(target_code);
1471                         return retval;
1472                 }
1473
1474                 /* write algorithm code to working area */
1475                 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1476                                     target_code_size, target_code)) != ERROR_OK)
1477                 {
1478                         free(target_code);
1479                         return retval;
1480                 }
1481
1482                 free(target_code);
1483         }
1484         /* the following code still assumes target code is fixed 24*4 bytes */
1485
1486         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1487         {
1488                 buffer_size /= 2;
1489                 if (buffer_size <= 256)
1490                 {
1491                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1492                         if (cfi_info->write_algorithm)
1493                                 target_free_working_area(target, cfi_info->write_algorithm);
1494
1495                         LOG_WARNING("not enough working area available, can't do block memory writes");
1496                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1497                 }
1498         };
1499
1500         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1501         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1502         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1503         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1504         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1505         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1506         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1507         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1508         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1509         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1510
1511         while (count > 0)
1512         {
1513                 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1514
1515                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1516
1517                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1518                 buf_set_u32(reg_params[1].value, 0, 32, address);
1519                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1520                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1521                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1522                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1523                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1524                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1525                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1526
1527                 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1528                                                      cfi_info->write_algorithm->address,
1529                                                      cfi_info->write_algorithm->address + ((target_code_size) - 4),
1530                                                      10000, &armv4_5_info);
1531
1532                 status = buf_get_u32(reg_params[5].value, 0, 32);
1533
1534                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1535                 {
1536                         LOG_DEBUG("status: 0x%" PRIx32 , status);
1537                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1538                         break;
1539                 }
1540
1541                 buffer += thisrun_count;
1542                 address += thisrun_count;
1543                 count -= thisrun_count;
1544         }
1545
1546         target_free_all_working_areas(target);
1547
1548         destroy_reg_param(&reg_params[0]);
1549         destroy_reg_param(&reg_params[1]);
1550         destroy_reg_param(&reg_params[2]);
1551         destroy_reg_param(&reg_params[3]);
1552         destroy_reg_param(&reg_params[4]);
1553         destroy_reg_param(&reg_params[5]);
1554         destroy_reg_param(&reg_params[6]);
1555         destroy_reg_param(&reg_params[7]);
1556         destroy_reg_param(&reg_params[8]);
1557         destroy_reg_param(&reg_params[9]);
1558
1559         return exit_code;
1560 }
1561
1562 static int cfi_intel_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1563 {
1564         int retval;
1565         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1566         struct target *target = bank->target;
1567         uint8_t command[8];
1568
1569         cfi_intel_clear_status_register(bank);
1570         cfi_command(bank, 0x40, command);
1571         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1572         {
1573                 return retval;
1574         }
1575
1576         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1577         {
1578                 return retval;
1579         }
1580
1581         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1582         {
1583                 cfi_command(bank, 0xff, command);
1584                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1585                 {
1586                         return retval;
1587                 }
1588
1589                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1590                 return ERROR_FLASH_OPERATION_FAILED;
1591         }
1592
1593         return ERROR_OK;
1594 }
1595
1596 static int cfi_intel_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1597 {
1598         int retval;
1599         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1600         struct target *target = bank->target;
1601         uint8_t command[8];
1602
1603         /* Calculate buffer size and boundary mask */
1604         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1605         uint32_t buffermask = buffersize-1;
1606         uint32_t bufferwsize;
1607
1608         /* Check for valid range */
1609         if (address & buffermask)
1610         {
1611                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1612                           bank->base, address, cfi_info->max_buf_write_size);
1613                 return ERROR_FLASH_OPERATION_FAILED;
1614         }
1615         switch (bank->chip_width)
1616         {
1617         case 4 : bufferwsize = buffersize / 4; break;
1618         case 2 : bufferwsize = buffersize / 2; break;
1619         case 1 : bufferwsize = buffersize; break;
1620         default:
1621                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1622                 return ERROR_FLASH_OPERATION_FAILED;
1623         }
1624
1625         bufferwsize/=(bank->bus_width / bank->chip_width);
1626
1627
1628         /* Check for valid size */
1629         if (wordcount > bufferwsize)
1630         {
1631                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1632                 return ERROR_FLASH_OPERATION_FAILED;
1633         }
1634
1635         /* Write to flash buffer */
1636         cfi_intel_clear_status_register(bank);
1637
1638         /* Initiate buffer operation _*/
1639         cfi_command(bank, 0xE8, command);
1640         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1641         {
1642                 return retval;
1643         }
1644         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1645         {
1646                 cfi_command(bank, 0xff, command);
1647                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1648                 {
1649                         return retval;
1650                 }
1651
1652                 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1653                 return ERROR_FLASH_OPERATION_FAILED;
1654         }
1655
1656         /* Write buffer wordcount-1 and data words */
1657         cfi_command(bank, bufferwsize-1, command);
1658         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1659         {
1660                 return retval;
1661         }
1662
1663         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1664         {
1665                 return retval;
1666         }
1667
1668         /* Commit write operation */
1669         cfi_command(bank, 0xd0, command);
1670         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1671         {
1672                 return retval;
1673         }
1674         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1675         {
1676                 cfi_command(bank, 0xff, command);
1677                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1678                 {
1679                         return retval;
1680                 }
1681
1682                 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1683                 return ERROR_FLASH_OPERATION_FAILED;
1684         }
1685
1686         return ERROR_OK;
1687 }
1688
1689 static int cfi_spansion_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1690 {
1691         int retval;
1692         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1693         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1694         struct target *target = bank->target;
1695         uint8_t command[8];
1696
1697         cfi_command(bank, 0xaa, command);
1698         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1699         {
1700                 return retval;
1701         }
1702
1703         cfi_command(bank, 0x55, command);
1704         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1705         {
1706                 return retval;
1707         }
1708
1709         cfi_command(bank, 0xa0, command);
1710         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1711         {
1712                 return retval;
1713         }
1714
1715         if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1716         {
1717                 return retval;
1718         }
1719
1720         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1721         {
1722                 cfi_command(bank, 0xf0, command);
1723                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1724                 {
1725                         return retval;
1726                 }
1727
1728                 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1729                 return ERROR_FLASH_OPERATION_FAILED;
1730         }
1731
1732         return ERROR_OK;
1733 }
1734
1735 static int cfi_spansion_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1736 {
1737         int retval;
1738         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1739         struct target *target = bank->target;
1740         uint8_t command[8];
1741         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1742
1743         /* Calculate buffer size and boundary mask */
1744         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1745         uint32_t buffermask = buffersize-1;
1746         uint32_t bufferwsize;
1747
1748         /* Check for valid range */
1749         if (address & buffermask)
1750         {
1751                 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1752                 return ERROR_FLASH_OPERATION_FAILED;
1753         }
1754         switch (bank->chip_width)
1755         {
1756         case 4 : bufferwsize = buffersize / 4; break;
1757         case 2 : bufferwsize = buffersize / 2; break;
1758         case 1 : bufferwsize = buffersize; break;
1759         default:
1760                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1761                 return ERROR_FLASH_OPERATION_FAILED;
1762         }
1763
1764         bufferwsize/=(bank->bus_width / bank->chip_width);
1765
1766         /* Check for valid size */
1767         if (wordcount > bufferwsize)
1768         {
1769                 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1770                 return ERROR_FLASH_OPERATION_FAILED;
1771         }
1772
1773         // Unlock
1774         cfi_command(bank, 0xaa, command);
1775         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1776         {
1777                 return retval;
1778         }
1779
1780         cfi_command(bank, 0x55, command);
1781         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1782         {
1783                 return retval;
1784         }
1785
1786         // Buffer load command
1787         cfi_command(bank, 0x25, command);
1788         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1789         {
1790                 return retval;
1791         }
1792
1793         /* Write buffer wordcount-1 and data words */
1794         cfi_command(bank, bufferwsize-1, command);
1795         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1796         {
1797                 return retval;
1798         }
1799
1800         if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1801         {
1802                 return retval;
1803         }
1804
1805         /* Commit write operation */
1806         cfi_command(bank, 0x29, command);
1807         if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1808         {
1809                 return retval;
1810         }
1811
1812         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1813         {
1814                 cfi_command(bank, 0xf0, command);
1815                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1816                 {
1817                         return retval;
1818                 }
1819
1820                 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1821                 return ERROR_FLASH_OPERATION_FAILED;
1822         }
1823
1824         return ERROR_OK;
1825 }
1826
1827 static int cfi_write_word(struct flash_bank_s *bank, uint8_t *word, uint32_t address)
1828 {
1829         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1830
1831         switch (cfi_info->pri_id)
1832         {
1833                 case 1:
1834                 case 3:
1835                         return cfi_intel_write_word(bank, word, address);
1836                         break;
1837                 case 2:
1838                         return cfi_spansion_write_word(bank, word, address);
1839                         break;
1840                 default:
1841                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1842                         break;
1843         }
1844
1845         return ERROR_FLASH_OPERATION_FAILED;
1846 }
1847
1848 static int cfi_write_words(struct flash_bank_s *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1849 {
1850         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1851
1852         switch (cfi_info->pri_id)
1853         {
1854                 case 1:
1855                 case 3:
1856                         return cfi_intel_write_words(bank, word, wordcount, address);
1857                         break;
1858                 case 2:
1859                         return cfi_spansion_write_words(bank, word, wordcount, address);
1860                         break;
1861                 default:
1862                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1863                         break;
1864         }
1865
1866         return ERROR_FLASH_OPERATION_FAILED;
1867 }
1868
1869 int cfi_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1870 {
1871         struct cfi_flash_bank *cfi_info = bank->driver_priv;
1872         struct target *target = bank->target;
1873         uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1874         uint32_t write_p, copy_p;
1875         int align;      /* number of unaligned bytes */
1876         int blk_count; /* number of bus_width bytes for block copy */
1877         uint8_t current_word[CFI_MAX_BUS_WIDTH * 4];    /* word (bus_width size) currently being programmed */
1878         int i;
1879         int retval;
1880
1881         if (bank->target->state != TARGET_HALTED)
1882         {
1883                 LOG_ERROR("Target not halted");
1884                 return ERROR_TARGET_NOT_HALTED;
1885         }
1886
1887         if (offset + count > bank->size)
1888                 return ERROR_FLASH_DST_OUT_OF_BANK;
1889
1890         if (cfi_info->qry[0] != 'Q')
1891                 return ERROR_FLASH_BANK_NOT_PROBED;
1892
1893         /* start at the first byte of the first word (bus_width size) */
1894         write_p = address & ~(bank->bus_width - 1);
1895         if ((align = address - write_p) != 0)
1896         {
1897                 LOG_INFO("Fixup %d unaligned head bytes", align);
1898
1899                 for (i = 0; i < bank->bus_width; i++)
1900                         current_word[i] = 0;
1901                 copy_p = write_p;
1902
1903                 /* copy bytes before the first write address */
1904                 for (i = 0; i < align; ++i, ++copy_p)
1905                 {
1906                         uint8_t byte;
1907                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1908                         {
1909                                 return retval;
1910                         }
1911                         cfi_add_byte(bank, current_word, byte);
1912                 }
1913
1914                 /* add bytes from the buffer */
1915                 for (; (i < bank->bus_width) && (count > 0); i++)
1916                 {
1917                         cfi_add_byte(bank, current_word, *buffer++);
1918                         count--;
1919                         copy_p++;
1920                 }
1921
1922                 /* if the buffer is already finished, copy bytes after the last write address */
1923                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1924                 {
1925                         uint8_t byte;
1926                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1927                         {
1928                                 return retval;
1929                         }
1930                         cfi_add_byte(bank, current_word, byte);
1931                 }
1932
1933                 retval = cfi_write_word(bank, current_word, write_p);
1934                 if (retval != ERROR_OK)
1935                         return retval;
1936                 write_p = copy_p;
1937         }
1938
1939         /* handle blocks of bus_size aligned bytes */
1940         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1941         switch (cfi_info->pri_id)
1942         {
1943                 /* try block writes (fails without working area) */
1944                 case 1:
1945                 case 3:
1946                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1947                         break;
1948                 case 2:
1949                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1950                         break;
1951                 default:
1952                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1953                         retval = ERROR_FLASH_OPERATION_FAILED;
1954                         break;
1955         }
1956         if (retval == ERROR_OK)
1957         {
1958                 /* Increment pointers and decrease count on succesful block write */
1959                 buffer += blk_count;
1960                 write_p += blk_count;
1961                 count -= blk_count;
1962         }
1963         else
1964         {
1965                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1966                 {
1967                         //adjust buffersize for chip width
1968                         uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1969                         uint32_t buffermask = buffersize-1;
1970                         uint32_t bufferwsize;
1971
1972                         switch (bank->chip_width)
1973                         {
1974                         case 4 : bufferwsize = buffersize / 4; break;
1975                         case 2 : bufferwsize = buffersize / 2; break;
1976                         case 1 : bufferwsize = buffersize; break;
1977                         default:
1978                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1979                                 return ERROR_FLASH_OPERATION_FAILED;
1980                         }
1981
1982                         bufferwsize/=(bank->bus_width / bank->chip_width);
1983
1984                         /* fall back to memory writes */
1985                         while (count >= (uint32_t)bank->bus_width)
1986                         {
1987                                 int fallback;
1988                                 if ((write_p & 0xff) == 0)
1989                                 {
1990                                         LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1991                                 }
1992                                 fallback = 1;
1993                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1994                                 {
1995                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1996                                         if (retval == ERROR_OK)
1997                                         {
1998                                                 buffer += buffersize;
1999                                                 write_p += buffersize;
2000                                                 count -= buffersize;
2001                                                 fallback = 0;
2002                                         }
2003                                 }
2004                                 /* try the slow way? */
2005                                 if (fallback)
2006                                 {
2007                                         for (i = 0; i < bank->bus_width; i++)
2008                                                 current_word[i] = 0;
2009
2010                                         for (i = 0; i < bank->bus_width; i++)
2011                                         {
2012                                                 cfi_add_byte(bank, current_word, *buffer++);
2013                                         }
2014
2015                                         retval = cfi_write_word(bank, current_word, write_p);
2016                                         if (retval != ERROR_OK)
2017                                                 return retval;
2018
2019                                         write_p += bank->bus_width;
2020                                         count -= bank->bus_width;
2021                                 }
2022                         }
2023                 }
2024                 else
2025                         return retval;
2026         }
2027
2028         /* return to read array mode, so we can read from flash again for padding */
2029         cfi_command(bank, 0xf0, current_word);
2030         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2031         {
2032                 return retval;
2033         }
2034         cfi_command(bank, 0xff, current_word);
2035         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2036         {
2037                 return retval;
2038         }
2039
2040         /* handle unaligned tail bytes */
2041         if (count > 0)
2042         {
2043                 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2044
2045                 copy_p = write_p;
2046                 for (i = 0; i < bank->bus_width; i++)
2047                         current_word[i] = 0;
2048
2049                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2050                 {
2051                         cfi_add_byte(bank, current_word, *buffer++);
2052                         count--;
2053                 }
2054                 for (; i < bank->bus_width; ++i, ++copy_p)
2055                 {
2056                         uint8_t byte;
2057                         if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2058                         {
2059                                 return retval;
2060                         }
2061                         cfi_add_byte(bank, current_word, byte);
2062                 }
2063                 retval = cfi_write_word(bank, current_word, write_p);
2064                 if (retval != ERROR_OK)
2065                         return retval;
2066         }
2067
2068         /* return to read array mode */
2069         cfi_command(bank, 0xf0, current_word);
2070         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2071         {
2072                 return retval;
2073         }
2074         cfi_command(bank, 0xff, current_word);
2075         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2076 }
2077
2078 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2079 {
2080         (void) param;
2081         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2082         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2083
2084         pri_ext->_reversed_geometry = 1;
2085 }
2086
2087 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2088 {
2089         int i;
2090         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2091         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2092         (void) param;
2093
2094         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2095         {
2096                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2097
2098                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2099                 {
2100                         int j = (cfi_info->num_erase_regions - 1) - i;
2101                         uint32_t swap;
2102
2103                         swap = cfi_info->erase_region_info[i];
2104                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2105                         cfi_info->erase_region_info[j] = swap;
2106                 }
2107         }
2108 }
2109
2110 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2111 {
2112         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2113         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2114         struct cfi_unlock_addresses *unlock_addresses = param;
2115
2116         pri_ext->_unlock1 = unlock_addresses->unlock1;
2117         pri_ext->_unlock2 = unlock_addresses->unlock2;
2118 }
2119
2120
2121 static int cfi_query_string(struct flash_bank_s *bank, int address)
2122 {
2123         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2124         struct target *target = bank->target;
2125         int retval;
2126         uint8_t command[8];
2127
2128         cfi_command(bank, 0x98, command);
2129         if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2130         {
2131                 return retval;
2132         }
2133
2134         cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2135         cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2136         cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2137
2138         LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2139
2140         if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2141         {
2142                 cfi_command(bank, 0xf0, command);
2143                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2144                 {
2145                         return retval;
2146                 }
2147                 cfi_command(bank, 0xff, command);
2148                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2149                 {
2150                         return retval;
2151                 }
2152                 LOG_ERROR("Could not probe bank: no QRY");
2153                 return ERROR_FLASH_BANK_INVALID;
2154         }
2155
2156         return ERROR_OK;
2157 }
2158
2159 static int cfi_probe(struct flash_bank_s *bank)
2160 {
2161         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2162         struct target *target = bank->target;
2163         uint8_t command[8];
2164         int num_sectors = 0;
2165         int i;
2166         int sector = 0;
2167         uint32_t unlock1 = 0x555;
2168         uint32_t unlock2 = 0x2aa;
2169         int retval;
2170
2171         if (bank->target->state != TARGET_HALTED)
2172         {
2173                 LOG_ERROR("Target not halted");
2174                 return ERROR_TARGET_NOT_HALTED;
2175         }
2176
2177         cfi_info->probed = 0;
2178
2179         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2180          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2181          */
2182         if (cfi_info->jedec_probe)
2183         {
2184                 unlock1 = 0x5555;
2185                 unlock2 = 0x2aaa;
2186         }
2187
2188         /* switch to read identifier codes mode ("AUTOSELECT") */
2189         cfi_command(bank, 0xaa, command);
2190         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2191         {
2192                 return retval;
2193         }
2194         cfi_command(bank, 0x55, command);
2195         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2196         {
2197                 return retval;
2198         }
2199         cfi_command(bank, 0x90, command);
2200         if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2201         {
2202                 return retval;
2203         }
2204
2205         if (bank->chip_width == 1)
2206         {
2207                 uint8_t manufacturer, device_id;
2208                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2209                 {
2210                         return retval;
2211                 }
2212                 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2213                 {
2214                         return retval;
2215                 }
2216                 cfi_info->manufacturer = manufacturer;
2217                 cfi_info->device_id = device_id;
2218         }
2219         else if (bank->chip_width == 2)
2220         {
2221                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2222                 {
2223                         return retval;
2224                 }
2225                 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2226                 {
2227                         return retval;
2228                 }
2229         }
2230
2231         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2232         /* switch back to read array mode */
2233         cfi_command(bank, 0xf0, command);
2234         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2235         {
2236                 return retval;
2237         }
2238         cfi_command(bank, 0xff, command);
2239         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2240         {
2241                 return retval;
2242         }
2243
2244         /* check device/manufacturer ID for known non-CFI flashes. */
2245         cfi_fixup_non_cfi(bank);
2246
2247         /* query only if this is a CFI compatible flash,
2248          * otherwise the relevant info has already been filled in
2249          */
2250         if (cfi_info->not_cfi == 0)
2251         {
2252                 int retval;
2253
2254                 /* enter CFI query mode
2255                  * according to JEDEC Standard No. 68.01,
2256                  * a single bus sequence with address = 0x55, data = 0x98 should put
2257                  * the device into CFI query mode.
2258                  *
2259                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2260                  */
2261
2262                 retval = cfi_query_string(bank, 0x55);
2263                 if (retval != ERROR_OK)
2264                 {
2265                         /*
2266                          * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2267                          * be harmless enough:
2268                          *
2269                          * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2270                          */
2271                         LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2272                         retval = cfi_query_string(bank, 0x555);
2273                 }
2274                 if (retval != ERROR_OK)
2275                         return retval;
2276
2277                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2278                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2279                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2280                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2281
2282                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2283
2284                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2285                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2286                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2287                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2288                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2289                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2290                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2291                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2292                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2293                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2294                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2295                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2296
2297                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2298                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2299                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2300                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2301                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2302                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2303                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2304                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2305                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2306                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2307                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2308
2309                 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2310                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2311                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2312                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2313
2314                 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2315
2316                 if (cfi_info->num_erase_regions)
2317                 {
2318                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2319                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2320                         {
2321                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2322                                 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2323                                           i,
2324                                           (cfi_info->erase_region_info[i] & 0xffff) + 1,
2325                                           (cfi_info->erase_region_info[i] >> 16) * 256);
2326                         }
2327                 }
2328                 else
2329                 {
2330                         cfi_info->erase_region_info = NULL;
2331                 }
2332
2333                 /* We need to read the primary algorithm extended query table before calculating
2334                  * the sector layout to be able to apply fixups
2335                  */
2336                 switch (cfi_info->pri_id)
2337                 {
2338                         /* Intel command set (standard and extended) */
2339                         case 0x0001:
2340                         case 0x0003:
2341                                 cfi_read_intel_pri_ext(bank);
2342                                 break;
2343                         /* AMD/Spansion, Atmel, ... command set */
2344                         case 0x0002:
2345                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2346                                 cfi_read_0002_pri_ext(bank);
2347                                 break;
2348                         default:
2349                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2350                                 break;
2351                 }
2352
2353                 /* return to read array mode
2354                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2355                  */
2356                 cfi_command(bank, 0xf0, command);
2357                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2358                 {
2359                         return retval;
2360                 }
2361                 cfi_command(bank, 0xff, command);
2362                 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2363                 {
2364                         return retval;
2365                 }
2366         } /* end CFI case */
2367
2368         /* apply fixups depending on the primary command set */
2369         switch (cfi_info->pri_id)
2370         {
2371                 /* Intel command set (standard and extended) */
2372                 case 0x0001:
2373                 case 0x0003:
2374                         cfi_fixup(bank, cfi_0001_fixups);
2375                         break;
2376                 /* AMD/Spansion, Atmel, ... command set */
2377                 case 0x0002:
2378                         cfi_fixup(bank, cfi_0002_fixups);
2379                         break;
2380                 default:
2381                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2382                         break;
2383         }
2384
2385         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2386         {
2387                 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2388         }
2389
2390         if (cfi_info->num_erase_regions == 0)
2391         {
2392                 /* a device might have only one erase block, spanning the whole device */
2393                 bank->num_sectors = 1;
2394                 bank->sectors = malloc(sizeof(struct flash_sector));
2395
2396                 bank->sectors[sector].offset = 0x0;
2397                 bank->sectors[sector].size = bank->size;
2398                 bank->sectors[sector].is_erased = -1;
2399                 bank->sectors[sector].is_protected = -1;
2400         }
2401         else
2402         {
2403                 uint32_t offset = 0;
2404
2405                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2406                 {
2407                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2408                 }
2409
2410                 bank->num_sectors = num_sectors;
2411                 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2412
2413                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2414                 {
2415                         uint32_t j;
2416                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2417                         {
2418                                 bank->sectors[sector].offset = offset;
2419                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2420                                 offset += bank->sectors[sector].size;
2421                                 bank->sectors[sector].is_erased = -1;
2422                                 bank->sectors[sector].is_protected = -1;
2423                                 sector++;
2424                         }
2425                 }
2426                 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2427                 {
2428                         LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2429                                 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2430                 }
2431         }
2432
2433         cfi_info->probed = 1;
2434
2435         return ERROR_OK;
2436 }
2437
2438 static int cfi_auto_probe(struct flash_bank_s *bank)
2439 {
2440         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2441         if (cfi_info->probed)
2442                 return ERROR_OK;
2443         return cfi_probe(bank);
2444 }
2445
2446
2447 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2448 {
2449         int retval;
2450         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2451         struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2452         struct target *target = bank->target;
2453         uint8_t command[CFI_MAX_BUS_WIDTH];
2454         int i;
2455
2456         /* check if block lock bits are supported on this device */
2457         if (!(pri_ext->blk_status_reg_mask & 0x1))
2458                 return ERROR_FLASH_OPERATION_FAILED;
2459
2460         cfi_command(bank, 0x90, command);
2461         if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2462         {
2463                 return retval;
2464         }
2465
2466         for (i = 0; i < bank->num_sectors; i++)
2467         {
2468                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2469
2470                 if (block_status & 1)
2471                         bank->sectors[i].is_protected = 1;
2472                 else
2473                         bank->sectors[i].is_protected = 0;
2474         }
2475
2476         cfi_command(bank, 0xff, command);
2477         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2478 }
2479
2480 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2481 {
2482         int retval;
2483         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2484         struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2485         struct target *target = bank->target;
2486         uint8_t command[8];
2487         int i;
2488
2489         cfi_command(bank, 0xaa, command);
2490         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2491         {
2492                 return retval;
2493         }
2494
2495         cfi_command(bank, 0x55, command);
2496         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2497         {
2498                 return retval;
2499         }
2500
2501         cfi_command(bank, 0x90, command);
2502         if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2503         {
2504                 return retval;
2505         }
2506
2507         for (i = 0; i < bank->num_sectors; i++)
2508         {
2509                 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2510
2511                 if (block_status & 1)
2512                         bank->sectors[i].is_protected = 1;
2513                 else
2514                         bank->sectors[i].is_protected = 0;
2515         }
2516
2517         cfi_command(bank, 0xf0, command);
2518         return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2519 }
2520
2521 static int cfi_protect_check(struct flash_bank_s *bank)
2522 {
2523         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2524
2525         if (bank->target->state != TARGET_HALTED)
2526         {
2527                 LOG_ERROR("Target not halted");
2528                 return ERROR_TARGET_NOT_HALTED;
2529         }
2530
2531         if (cfi_info->qry[0] != 'Q')
2532                 return ERROR_FLASH_BANK_NOT_PROBED;
2533
2534         switch (cfi_info->pri_id)
2535         {
2536                 case 1:
2537                 case 3:
2538                         return cfi_intel_protect_check(bank);
2539                         break;
2540                 case 2:
2541                         return cfi_spansion_protect_check(bank);
2542                         break;
2543                 default:
2544                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2545                         break;
2546         }
2547
2548         return ERROR_OK;
2549 }
2550
2551 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2552 {
2553         int printed;
2554         struct cfi_flash_bank *cfi_info = bank->driver_priv;
2555
2556         if (cfi_info->qry[0] == (char)-1)
2557         {
2558                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2559                 return ERROR_OK;
2560         }
2561
2562         if (cfi_info->not_cfi == 0)
2563                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2564         else
2565                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2566         buf += printed;
2567         buf_size -= printed;
2568
2569         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2570                 cfi_info->manufacturer, cfi_info->device_id);
2571         buf += printed;
2572         buf_size -= printed;
2573
2574         if (cfi_info->not_cfi == 0)
2575         {
2576         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2577         buf += printed;
2578         buf_size -= printed;
2579
2580                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2581                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2582         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2583         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2584         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2585         buf += printed;
2586         buf_size -= printed;
2587
2588                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2589                                    1 << cfi_info->word_write_timeout_typ,
2590                                    1 << cfi_info->buf_write_timeout_typ,
2591                                    1 << cfi_info->block_erase_timeout_typ,
2592                                    1 << cfi_info->chip_erase_timeout_typ);
2593         buf += printed;
2594         buf_size -= printed;
2595
2596                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2597                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2598                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2599                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2600                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2601         buf += printed;
2602         buf_size -= printed;
2603
2604                 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2605                                    cfi_info->dev_size,
2606                                    cfi_info->interface_desc,
2607                                    1 << cfi_info->max_buf_write_size);
2608         buf += printed;
2609         buf_size -= printed;
2610
2611         switch (cfi_info->pri_id)
2612         {
2613                 case 1:
2614                 case 3:
2615                         cfi_intel_info(bank, buf, buf_size);
2616                         break;
2617                 case 2:
2618                         cfi_spansion_info(bank, buf, buf_size);
2619                         break;
2620                 default:
2621                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2622                         break;
2623         }
2624         }
2625
2626         return ERROR_OK;
2627 }
2628
2629 struct flash_driver cfi_flash = {
2630                 .name = "cfi",
2631                 .register_commands = &cfi_register_commands,
2632                 .flash_bank_command = &cfi_flash_bank_command,
2633                 .erase = &cfi_erase,
2634                 .protect = &cfi_protect,
2635                 .write = &cfi_write,
2636                 .probe = &cfi_probe,
2637                 .auto_probe = &cfi_auto_probe,
2638                 .erase_check = &default_flash_blank_check,
2639                 .protect_check = &cfi_protect_check,
2640                 .info = &cfi_info,
2641         };