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   1 /***************************************************************************\r
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *\r
   3  *   lundin@mlu.mine.nu                                                    *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 \r
  21 /***************************************************************************\r
  22 There are some things to notice\r
  23 \r
  24 * AT91SAM7S64 is tested\r
  25 * All AT91SAM7Sxx  and  AT91SAM7Xxx should work but is not tested\r
  26 * All parameters are identified from onchip configuartion registers \r
  27 *\r
  28 * The flash controller handles erases automatically on a page (128/265 byte) basis\r
  29 * Only an EraseAll command is supported by the controller\r
  30 * Partial erases can be implemented in software by writing one 0xFFFFFFFF word to \r
  31 * some location in every page in the region to be erased\r
  32 *  \r
  33 * Lock regions (sectors) are 32 or 64 pages\r
  34 *\r
  35  ***************************************************************************/\r
  36 #ifdef HAVE_CONFIG_H\r
  37 #include "config.h"\r
  38 #endif\r
  39 \r
  40 #include "replacements.h"\r
  41 \r
  42 #include "at91sam7.h"\r
  43 \r
  44 #include "flash.h"\r
  45 #include "target.h"\r
  46 #include "log.h"\r
  47 #include "binarybuffer.h"\r
  48 #include "types.h"\r
  49 \r
  50 #include <stdlib.h>\r
  51 #include <string.h>\r
  52 #include <unistd.h>\r
  53 \r
  54 int at91sam7_register_commands(struct command_context_s *cmd_ctx);\r
  55 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);\r
  56 int at91sam7_erase(struct flash_bank_s *bank, int first, int last);\r
  57 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);\r
  58 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);\r
  59 int at91sam7_probe(struct flash_bank_s *bank);\r
  60 int at91sam7_auto_probe(struct flash_bank_s *bank);\r
  61 int at91sam7_erase_check(struct flash_bank_s *bank);\r
  62 int at91sam7_protect_check(struct flash_bank_s *bank);\r
  63 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);\r
  64 \r
  65 u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane);\r
  66 void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode);\r
  67 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout);\r
  68 int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen); \r
  69 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  70 \r
  71 flash_driver_t at91sam7_flash =\r
  72 {\r
  73         .name = "at91sam7",\r
  74         .register_commands = at91sam7_register_commands,\r
  75         .flash_bank_command = at91sam7_flash_bank_command,\r
  76         .erase = at91sam7_erase,\r
  77         .protect = at91sam7_protect,\r
  78         .write = at91sam7_write,\r
  79         .probe = at91sam7_probe,\r
  80         .auto_probe = at91sam7_auto_probe,\r
  81         .erase_check = at91sam7_erase_check,\r
  82         .protect_check = at91sam7_protect_check,\r
  83         .info = at91sam7_info\r
  84 };\r
  85 \r
  86 u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };\r
  87 u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };\r
  88 u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };\r
  89 \r
  90 char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};\r
  91 long NVPSIZ[16] = {\r
  92    0,\r
  93    0x2000, /*  8K */\r
  94    0x4000, /* 16K */ \r
  95    0x8000, /* 32K */\r
  96    -1,\r
  97    0x10000, /* 64K */\r
  98    -1,\r
  99    0x20000, /* 128K */\r
 100    -1,\r
 101    0x40000, /* 256K */\r
 102    0x80000, /* 512K */\r
 103    -1,\r
 104    0x100000, /* 1024K */\r
 105    -1,\r
 106    0x200000, /* 2048K */\r
 107    -1\r
 108 };\r
 109 \r
 110 long SRAMSIZ[16] = {\r
 111    -1,\r
 112    0x0400, /*  1K */\r
 113    0x0800, /*  2K */ \r
 114    -1, \r
 115    0x1c000,  /* 112K */\r
 116    0x1000,  /*   4K */\r
 117    0x14000, /*  80K */\r
 118    0x28000, /* 160K */\r
 119    0x2000,  /*   8K */\r
 120    0x4000,  /*  16K */\r
 121    0x8000,  /*  32K */\r
 122    0x10000, /*  64K */\r
 123    0x20000, /* 128K */\r
 124    0x40000, /* 256K */\r
 125    0x18000, /* 96K */\r
 126    0x80000, /* 512K */\r
 127 };\r
 128 \r
 129 int at91sam7_register_commands(struct command_context_s *cmd_ctx)\r
 130 {\r
 131         command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);\r
 132         register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,\r
 133                         "at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");\r
 134 \r
 135         return ERROR_OK;\r
 136 }\r
 137 \r
 138 u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane)\r
 139 {\r
 140         target_t *target = bank->target;\r
 141         u32 fsr;\r
 142         \r
 143         target_read_u32(target, MC_FSR[flashplane], &fsr);\r
 144         \r
 145         return fsr;\r
 146 }\r
 147 \r
 148 /** Read clock configuration and set at91sam7_info->usec_clocks*/ \r
 149 void at91sam7_read_clock_info(flash_bank_t *bank)\r
 150 {\r
 151         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 152         target_t *target = bank->target;\r
 153         u32 mckr, mcfr, pllr;\r
 154         unsigned long tmp = 0, mainfreq;\r
 155         int flashplane;\r
 156 \r
 157         /* Read main clock freqency register */\r
 158         target_read_u32(target, CKGR_MCFR, &mcfr);\r
 159         /* Read master clock register */\r
 160         target_read_u32(target, PMC_MCKR, &mckr);\r
 161         /* Read Clock Generator PLL Register  */\r
 162         target_read_u32(target, CKGR_PLLR, &pllr);\r
 163 \r
 164         at91sam7_info->mck_valid = 0;\r
 165         switch (mckr & PMC_MCKR_CSS) \r
 166         {\r
 167                 case 0:                 /* Slow Clock */\r
 168                         at91sam7_info->mck_valid = 1;\r
 169                         mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);\r
 170                         tmp = mainfreq;\r
 171                         break;\r
 172                 case 1:                 /* Main Clock */\r
 173                         if (mcfr & CKGR_MCFR_MAINRDY) \r
 174                         {\r
 175                                 at91sam7_info->mck_valid = 1;\r
 176                                 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);\r
 177                                 tmp = mainfreq;\r
 178                         }\r
 179                         break;\r
 180 \r
 181                 case 2:                 /* Reserved */\r
 182                         break;\r
 183                 case 3:         /* PLL Clock */\r
 184                         if (mcfr & CKGR_MCFR_MAINRDY) \r
 185                         {\r
 186                                 target_read_u32(target, CKGR_PLLR, &pllr);\r
 187                                 if (!(pllr & CKGR_PLLR_DIV))\r
 188                                         break; /* 0 Hz */\r
 189                                 at91sam7_info->mck_valid = 1;\r
 190                                 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);\r
 191                                 /* Integer arithmetic should have sufficient precision\r
 192                                    as long as PLL is properly configured. */\r
 193                                 tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *\r
 194                                   (((pllr & CKGR_PLLR_MUL) >> 16) + 1);\r
 195                         }\r
 196                         break;\r
 197         }\r
 198         \r
 199         /* Prescaler adjust */\r
 200         if (((mckr & PMC_MCKR_PRES) >> 2) == 7)\r
 201                 at91sam7_info->mck_valid = 0;\r
 202         else\r
 203                 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);\r
 204 \r
 205         /* Forget old flash timing */\r
 206         for (flashplane = 0; flashplane<at91sam7_info->num_planes; flashplane++)\r
 207         {\r
 208                 at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE);\r
 209         }\r
 210 }\r
 211 \r
 212 /* Setup the timimg registers for nvbits or normal flash */\r
 213 void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode)\r
 214 {\r
 215         u32 fmr, fmcn = 0, fws = 0;\r
 216         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 217         target_t *target = bank->target;\r
 218         \r
 219         if (mode && (mode != at91sam7_info->flashmode[flashplane]))\r
 220         {\r
 221                 /* Always round up (ceil) */\r
 222                 if (mode==FMR_TIMING_NVBITS)\r
 223                 {\r
 224                         if (at91sam7_info->cidr_arch == 0x60)\r
 225                         {\r
 226                                 /* AT91SAM7A3 uses master clocks in 100 ns */\r
 227                                 fmcn = (at91sam7_info->mck_freq/10000000ul)+1;\r
 228                         }\r
 229                         else\r
 230                         {\r
 231                                 /* master clocks in 1uS for ARCH 0x7 types */\r
 232                                 fmcn = (at91sam7_info->mck_freq/1000000ul)+1;\r
 233                         }\r
 234                 }\r
 235                 else if (mode==FMR_TIMING_FLASH)\r
 236                         /* main clocks in 1.5uS */\r
 237                         fmcn = (at91sam7_info->mck_freq/666666ul)+1;\r
 238 \r
 239                 /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */\r
 240                 if (at91sam7_info->mck_freq <= 33333ul)\r
 241                         fmcn = 0;\r
 242                 /* Only allow fws=0 if clock frequency is < 30 MHz. */\r
 243                 if (at91sam7_info->mck_freq > 30000000ul)\r
 244                         fws = 1;\r
 245 \r
 246                 DEBUG("fmcn[%i]: %i", flashplane, fmcn); \r
 247                 fmr = fmcn << 16 | fws << 8;\r
 248                 target_write_u32(target, MC_FMR[flashplane], fmr);\r
 249         }\r
 250         \r
 251         at91sam7_info->flashmode[flashplane] = mode;            \r
 252 }\r
 253 \r
 254 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout)\r
 255 {\r
 256         u32 status;\r
 257         \r
 258         while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0))\r
 259         {\r
 260                 DEBUG("status[%i]: 0x%x", flashplane, status);\r
 261                 usleep(1000);\r
 262         }\r
 263         \r
 264         DEBUG("status[%i]: 0x%x", flashplane, status);\r
 265 \r
 266         if (status & 0x0C)\r
 267         {\r
 268                 ERROR("status register: 0x%x", status);\r
 269                 if (status & 0x4)\r
 270                         ERROR("Lock Error Bit Detected, Operation Abort");\r
 271                 if (status & 0x8)\r
 272                         ERROR("Invalid command and/or bad keyword, Operation Abort");\r
 273                 if (status & 0x10)\r
 274                         ERROR("Security Bit Set, Operation Abort");\r
 275         }\r
 276         \r
 277         return status;\r
 278 }\r
 279 \r
 280 \r
 281 /* Send one command to the AT91SAM flash controller */\r
 282 int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen) \r
 283 {\r
 284         u32 fcr;\r
 285         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 286         target_t *target = bank->target;\r
 287 \r
 288         fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; \r
 289         target_write_u32(target, MC_FCR[flashplane], fcr);\r
 290         DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen);\r
 291 \r
 292         if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))\r
 293         {\r
 294                 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */\r
 295                 if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C) \r
 296                 {\r
 297                         return ERROR_FLASH_OPERATION_FAILED;\r
 298                 }\r
 299                 return ERROR_OK;\r
 300         }\r
 301 \r
 302         if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C) \r
 303         {\r
 304                 return ERROR_FLASH_OPERATION_FAILED;\r
 305         }\r
 306         return ERROR_OK;\r
 307 }\r
 308 \r
 309 /* Read device id register, main clock frequency register and fill in driver info structure */\r
 310 int at91sam7_read_part_info(struct flash_bank_s *bank)\r
 311 {\r
 312         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 313         target_t *target = bank->target;\r
 314         u32 cidr, status;\r
 315         int sectornum;\r
 316         \r
 317         if (bank->target->state != TARGET_HALTED)\r
 318         {\r
 319                 return ERROR_TARGET_NOT_HALTED;\r
 320         }\r
 321         \r
 322         /* Read and parse chip identification register */\r
 323         target_read_u32(target, DBGU_CIDR, &cidr);\r
 324         \r
 325         if (cidr == 0)\r
 326         {\r
 327                 WARNING("Cannot identify target as an AT91SAM");\r
 328                 return ERROR_FLASH_OPERATION_FAILED;\r
 329         }\r
 330         \r
 331         at91sam7_info->cidr = cidr;\r
 332         at91sam7_info->cidr_ext = (cidr>>31)&0x0001;\r
 333         at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;\r
 334         at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;\r
 335         at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;\r
 336         at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;\r
 337         at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;\r
 338         at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;\r
 339         at91sam7_info->cidr_version = cidr&0x001F;\r
 340         bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz];\r
 341         at91sam7_info->target_name = "Unknown";\r
 342 \r
 343         /* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */\r
 344         if (NVPSIZ[at91sam7_info->cidr_nvpsiz]<0x80000)  /* Flash size less than 512K, one flash plane */\r
 345         {\r
 346                 bank->num_sectors = 1;\r
 347                 bank->sectors = malloc(sizeof(flash_sector_t));\r
 348                 bank->sectors[0].offset = 0;\r
 349                 bank->sectors[0].size = bank->size;\r
 350                 bank->sectors[0].is_erased = -1;\r
 351                 bank->sectors[0].is_protected = -1;\r
 352         }\r
 353         else    /* Flash size 512K or larger, several flash planes */\r
 354         {\r
 355                 bank->num_sectors = NVPSIZ[at91sam7_info->cidr_nvpsiz]/0x40000;\r
 356                 bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t));\r
 357                 for (sectornum=0; sectornum<bank->num_sectors; sectornum++)\r
 358                 {\r
 359                         bank->sectors[sectornum].offset = sectornum*0x40000;\r
 360                         bank->sectors[sectornum].size = 0x40000;\r
 361                         bank->sectors[sectornum].is_erased = -1;\r
 362                         bank->sectors[sectornum].is_protected = -1;\r
 363                 }\r
 364         }\r
 365                 \r
 366         \r
 367 \r
 368         DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );\r
 369 \r
 370         /* Read main and master clock freqency register */\r
 371         at91sam7_read_clock_info(bank);\r
 372         \r
 373         at91sam7_info->num_planes = 1;\r
 374         status = at91sam7_get_flash_status(bank, 0);\r
 375         at91sam7_info->securitybit = (status>>4)&0x01;\r
 376         at91sam7_protect_check(bank);   /* TODO Check the protect check */\r
 377         \r
 378         if (at91sam7_info->cidr_arch == 0x70 )\r
 379         {\r
 380                 at91sam7_info->num_nvmbits = 2;\r
 381                 at91sam7_info->nvmbits = (status>>8)&0x03;\r
 382                 bank->base = 0x100000;\r
 383                 bank->bus_width = 4;\r
 384                 if (bank->size==0x80000)  /* AT91SAM7S512 */\r
 385                 {\r
 386                         at91sam7_info->target_name = "AT91SAM7S512";\r
 387                         at91sam7_info->num_planes = 2;\r
 388                         if (at91sam7_info->num_planes != bank->num_sectors)\r
 389                                 WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;\r
 390                         at91sam7_info->num_lockbits = 2*16;\r
 391                         at91sam7_info->pagesize = 256;\r
 392                         at91sam7_info->pages_in_lockregion = 64;\r
 393                         at91sam7_info->num_pages = 2*16*64;\r
 394                 }\r
 395                 if (bank->size==0x40000)  /* AT91SAM7S256 */\r
 396                 {\r
 397                         at91sam7_info->target_name = "AT91SAM7S256";\r
 398                         at91sam7_info->num_lockbits = 16;\r
 399                         at91sam7_info->pagesize = 256;\r
 400                         at91sam7_info->pages_in_lockregion = 64;\r
 401                         at91sam7_info->num_pages = 16*64;\r
 402                 }\r
 403                 if (bank->size==0x20000)  /* AT91SAM7S128 */\r
 404                 {\r
 405                         at91sam7_info->target_name = "AT91SAM7S128";\r
 406                         at91sam7_info->num_lockbits = 8;\r
 407                         at91sam7_info->pagesize = 256;\r
 408                         at91sam7_info->pages_in_lockregion = 64;\r
 409                         at91sam7_info->num_pages = 8*64;\r
 410                 }\r
 411                 if (bank->size==0x10000)  /* AT91SAM7S64 */\r
 412                 {\r
 413                         at91sam7_info->target_name = "AT91SAM7S64";\r
 414                         at91sam7_info->num_lockbits = 16;\r
 415                         at91sam7_info->pagesize = 128;\r
 416                         at91sam7_info->pages_in_lockregion = 32;\r
 417                         at91sam7_info->num_pages = 16*32;\r
 418                 }\r
 419                 if (bank->size==0x08000)  /* AT91SAM7S321/32 */\r
 420                 {\r
 421                         at91sam7_info->target_name = "AT91SAM7S321/32";\r
 422                         at91sam7_info->num_lockbits = 8;\r
 423                         at91sam7_info->pagesize = 128;\r
 424                         at91sam7_info->pages_in_lockregion = 32;\r
 425                         at91sam7_info->num_pages = 8*32;\r
 426                 }\r
 427                 \r
 428                 return ERROR_OK;\r
 429         }\r
 430 \r
 431         if (at91sam7_info->cidr_arch == 0x71 )\r
 432         {\r
 433                 at91sam7_info->num_nvmbits = 3;\r
 434                 at91sam7_info->nvmbits = (status>>8)&0x07;\r
 435                 bank->base = 0x100000;\r
 436                 bank->bus_width = 4;\r
 437                 if (bank->size==0x80000)  /* AT91SAM7XC512 */\r
 438                 {\r
 439                         at91sam7_info->target_name = "AT91SAM7XC512";\r
 440                         at91sam7_info->num_planes = 2;\r
 441                         if (at91sam7_info->num_planes != bank->num_sectors)\r
 442                                 WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;\r
 443                         at91sam7_info->num_lockbits = 2*16;\r
 444                         at91sam7_info->pagesize = 256;\r
 445                         at91sam7_info->pages_in_lockregion = 64;\r
 446                         at91sam7_info->num_pages = 2*16*64;\r
 447                 }\r
 448                 if (bank->size==0x40000)  /* AT91SAM7XC256 */\r
 449                 {\r
 450                         at91sam7_info->target_name = "AT91SAM7XC256";\r
 451                         at91sam7_info->num_lockbits = 16;\r
 452                         at91sam7_info->pagesize = 256;\r
 453                         at91sam7_info->pages_in_lockregion = 64;\r
 454                         at91sam7_info->num_pages = 16*64;\r
 455                 }\r
 456                 if (bank->size==0x20000)  /* AT91SAM7XC128 */\r
 457                 {\r
 458                         at91sam7_info->target_name = "AT91SAM7XC128";\r
 459                         at91sam7_info->num_lockbits = 8;\r
 460                         at91sam7_info->pagesize = 256;\r
 461                         at91sam7_info->pages_in_lockregion = 64;\r
 462                         at91sam7_info->num_pages = 8*64;\r
 463                 }\r
 464                 \r
 465                 return ERROR_OK;\r
 466         }\r
 467         \r
 468         if (at91sam7_info->cidr_arch == 0x72 )\r
 469         {\r
 470                 at91sam7_info->num_nvmbits = 3;\r
 471                 at91sam7_info->nvmbits = (status>>8)&0x07;\r
 472                 bank->base = 0x100000;\r
 473                 bank->bus_width = 4;\r
 474                 if (bank->size==0x80000) /* AT91SAM7SE512 */\r
 475                 {\r
 476                         at91sam7_info->target_name = "AT91SAM7SE512";\r
 477                         at91sam7_info->num_planes = 2;\r
 478                         if (at91sam7_info->num_planes != bank->num_sectors)\r
 479                                 WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;\r
 480                         at91sam7_info->num_lockbits = 32;\r
 481                         at91sam7_info->pagesize = 256;\r
 482                         at91sam7_info->pages_in_lockregion = 64;\r
 483                         at91sam7_info->num_pages = 32*64;\r
 484                 }\r
 485                 if (bank->size==0x40000)\r
 486                 {\r
 487                         at91sam7_info->target_name = "AT91SAM7SE256";\r
 488                         at91sam7_info->num_lockbits = 16;\r
 489                         at91sam7_info->pagesize = 256;\r
 490                         at91sam7_info->pages_in_lockregion = 64;\r
 491                         at91sam7_info->num_pages = 16*64;\r
 492                 }\r
 493                 if (bank->size==0x08000)\r
 494                 {\r
 495                         at91sam7_info->target_name = "AT91SAM7SE32";\r
 496                         at91sam7_info->num_lockbits = 8;\r
 497                         at91sam7_info->pagesize = 128;\r
 498                         at91sam7_info->pages_in_lockregion = 32;\r
 499                         at91sam7_info->num_pages = 8*32;\r
 500                 }\r
 501                 \r
 502                 return ERROR_OK;\r
 503         }\r
 504         \r
 505         if (at91sam7_info->cidr_arch == 0x75 )\r
 506         {\r
 507                 at91sam7_info->num_nvmbits = 3;\r
 508                 at91sam7_info->nvmbits = (status>>8)&0x07;\r
 509                 bank->base = 0x100000;\r
 510                 bank->bus_width = 4;\r
 511                 if (bank->size==0x80000)  /* AT91SAM7X512 */\r
 512                 {\r
 513                         at91sam7_info->target_name = "AT91SAM7X512";\r
 514                         at91sam7_info->num_planes = 2;\r
 515                         if (at91sam7_info->num_planes != bank->num_sectors)\r
 516                                 WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");;\r
 517                         at91sam7_info->num_lockbits = 32;\r
 518                         at91sam7_info->pagesize = 256;\r
 519                         at91sam7_info->pages_in_lockregion = 64;\r
 520                         at91sam7_info->num_pages = 2*16*64;\r
 521                         DEBUG("Support for AT91SAM7X512 is experimental in this version!");\r
 522                 }\r
 523                 if (bank->size==0x40000)  /* AT91SAM7X256 */\r
 524                 {\r
 525                         at91sam7_info->target_name = "AT91SAM7X256";\r
 526                         at91sam7_info->num_lockbits = 16;\r
 527                         at91sam7_info->pagesize = 256;\r
 528                         at91sam7_info->pages_in_lockregion = 64;\r
 529                         at91sam7_info->num_pages = 16*64;\r
 530                 }\r
 531                 if (bank->size==0x20000)  /* AT91SAM7X128 */\r
 532                 {\r
 533                         at91sam7_info->target_name = "AT91SAM7X128";\r
 534                         at91sam7_info->num_lockbits = 8;\r
 535                         at91sam7_info->pagesize = 256;\r
 536                         at91sam7_info->pages_in_lockregion = 64;\r
 537                         at91sam7_info->num_pages = 8*64;\r
 538                 }\r
 539         \r
 540                 return ERROR_OK;\r
 541         }\r
 542         \r
 543         if (at91sam7_info->cidr_arch == 0x60 )\r
 544         {\r
 545                 at91sam7_info->num_nvmbits = 3;\r
 546                 at91sam7_info->nvmbits = (status>>8)&0x07;\r
 547                 bank->base = 0x100000;\r
 548                 bank->bus_width = 4;\r
 549                 \r
 550                 if (bank->size == 0x40000)  /* AT91SAM7A3 */\r
 551                 {\r
 552                         at91sam7_info->target_name = "AT91SAM7A3";\r
 553                         at91sam7_info->num_lockbits = 16;\r
 554                         at91sam7_info->pagesize = 256;\r
 555                         at91sam7_info->pages_in_lockregion = 16;\r
 556                         at91sam7_info->num_pages = 16*64;\r
 557                 }\r
 558                 return ERROR_OK;\r
 559         }\r
 560         \r
 561    WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");\r
 562         \r
 563    return ERROR_OK;\r
 564 }\r
 565 \r
 566 int at91sam7_erase_check(struct flash_bank_s *bank)\r
 567 {\r
 568         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 569         \r
 570         if (!at91sam7_info->working_area_size)\r
 571         {\r
 572         }\r
 573         else\r
 574         {       \r
 575         }\r
 576         \r
 577         return ERROR_OK;\r
 578 }\r
 579 \r
 580 int at91sam7_protect_check(struct flash_bank_s *bank)\r
 581 {\r
 582         u32 status;\r
 583         int flashplane;\r
 584         \r
 585         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 586 \r
 587         if (at91sam7_info->cidr == 0)\r
 588         {\r
 589                 at91sam7_read_part_info(bank);\r
 590         }\r
 591 \r
 592         if (at91sam7_info->cidr == 0)\r
 593         {\r
 594                 WARNING("Cannot identify target as an AT91SAM");\r
 595                 return ERROR_FLASH_OPERATION_FAILED;\r
 596         }\r
 597 \r
 598         for (flashplane=0;flashplane<at91sam7_info->num_planes;flashplane++)\r
 599         {\r
 600                 status = at91sam7_get_flash_status(bank, flashplane);\r
 601                 at91sam7_info->lockbits[flashplane] = (status >> 16);\r
 602         }\r
 603         \r
 604         return ERROR_OK;\r
 605 }\r
 606 \r
 607 /* flash_bank at91sam7 0 0 0 0 <target#>\r
 608  */\r
 609 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)\r
 610 {\r
 611         at91sam7_flash_bank_t *at91sam7_info;\r
 612         int i;\r
 613         \r
 614         if (argc < 6)\r
 615         {\r
 616                 WARNING("incomplete flash_bank at91sam7 configuration");\r
 617                 return ERROR_FLASH_BANK_INVALID;\r
 618         }\r
 619         \r
 620         at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));\r
 621         bank->driver_priv = at91sam7_info;\r
 622         at91sam7_info->probed = 0;\r
 623         \r
 624         /* part wasn't probed for info yet */\r
 625         at91sam7_info->cidr = 0;\r
 626         for (i=0;i<4;i++)\r
 627                 at91sam7_info->flashmode[i]=0;\r
 628         \r
 629         return ERROR_OK;\r
 630 }\r
 631 \r
 632 int at91sam7_erase(struct flash_bank_s *bank, int first, int last)\r
 633 {\r
 634         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 635         u8 flashplane;\r
 636 \r
 637         if (bank->target->state != TARGET_HALTED)\r
 638         {\r
 639                 return ERROR_TARGET_NOT_HALTED;\r
 640         }\r
 641         \r
 642         if (at91sam7_info->cidr == 0)\r
 643         {\r
 644                 at91sam7_read_part_info(bank);\r
 645         }\r
 646 \r
 647         if (at91sam7_info->cidr == 0)\r
 648         {\r
 649                 WARNING("Cannot identify target as an AT91SAM");\r
 650                 return ERROR_FLASH_OPERATION_FAILED;\r
 651         }       \r
 652         \r
 653         if ((first < 0) || (last < first) || (last >= bank->num_sectors))\r
 654         {\r
 655                 if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))\r
 656                 {\r
 657                         WARNING("Sector numbers based on lockbit count, probably a deprecated script");\r
 658                         last = bank->num_sectors-1;\r
 659                 }\r
 660                 else return ERROR_FLASH_SECTOR_INVALID;\r
 661         }\r
 662 \r
 663         /* Configure the flash controller timing */\r
 664         at91sam7_read_clock_info(bank); \r
 665         for (flashplane = first; flashplane<=last; flashplane++)\r
 666         {\r
 667                 /* Configure the flash controller timing */\r
 668                 at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);\r
 669                 if (at91sam7_flash_command(bank, flashplane, EA, 0) != ERROR_OK) \r
 670                 {\r
 671                         return ERROR_FLASH_OPERATION_FAILED;\r
 672                 }       \r
 673         }\r
 674         return ERROR_OK;\r
 675 \r
 676 }\r
 677 \r
 678 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)\r
 679 {\r
 680         u32 cmd, pagen;\r
 681         u8 flashplane;\r
 682         int lockregion;\r
 683         \r
 684         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 685         \r
 686         if (bank->target->state != TARGET_HALTED)\r
 687         {\r
 688                 return ERROR_TARGET_NOT_HALTED;\r
 689         }\r
 690         \r
 691         if ((first < 0) || (last < first) || (last >= at91sam7_info->num_lockbits))\r
 692         {\r
 693                 return ERROR_FLASH_SECTOR_INVALID;\r
 694         }\r
 695         \r
 696         if (at91sam7_info->cidr == 0)\r
 697         {\r
 698                 at91sam7_read_part_info(bank);\r
 699         }\r
 700 \r
 701         if (at91sam7_info->cidr == 0)\r
 702         {\r
 703                 WARNING("Cannot identify target as an AT91SAM");\r
 704                 return ERROR_FLASH_OPERATION_FAILED;\r
 705         }\r
 706         \r
 707         at91sam7_read_clock_info(bank); \r
 708         \r
 709         for (lockregion=first;lockregion<=last;lockregion++) \r
 710         {\r
 711                 pagen = lockregion*at91sam7_info->pages_in_lockregion;\r
 712                 flashplane = (pagen>>10)&0x03;\r
 713                 /* Configure the flash controller timing */\r
 714                 at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NVBITS);\r
 715                 \r
 716                 if (set)\r
 717                          cmd = SLB; \r
 718                 else\r
 719                          cmd = CLB;             \r
 720 \r
 721                 if (at91sam7_flash_command(bank, flashplane, cmd, pagen) != ERROR_OK) \r
 722                 {\r
 723                         return ERROR_FLASH_OPERATION_FAILED;\r
 724                 }       \r
 725         }\r
 726         \r
 727         at91sam7_protect_check(bank);\r
 728                 \r
 729         return ERROR_OK;\r
 730 }\r
 731 \r
 732 \r
 733 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)\r
 734 {\r
 735         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 736         target_t *target = bank->target;\r
 737         u32 dst_min_alignment, wcount, bytes_remaining = count;\r
 738         u32 first_page, last_page, pagen, buffer_pos;\r
 739         u8 flashplane;\r
 740         \r
 741         if (at91sam7_info->cidr == 0)\r
 742         {\r
 743                 at91sam7_read_part_info(bank);\r
 744         }\r
 745 \r
 746         if (at91sam7_info->cidr == 0)\r
 747         {\r
 748                 WARNING("Cannot identify target as an AT91SAM");\r
 749                 return ERROR_FLASH_OPERATION_FAILED;\r
 750         }\r
 751         \r
 752         if (offset + count > bank->size)\r
 753                 return ERROR_FLASH_DST_OUT_OF_BANK;\r
 754         \r
 755         dst_min_alignment = at91sam7_info->pagesize;\r
 756 \r
 757         if (offset % dst_min_alignment)\r
 758         {\r
 759                 WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);\r
 760                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;\r
 761         }\r
 762         \r
 763         if (at91sam7_info->cidr_arch == 0)\r
 764                 return ERROR_FLASH_BANK_NOT_PROBED;\r
 765 \r
 766         first_page = offset/dst_min_alignment;\r
 767         last_page = CEIL(offset + count, dst_min_alignment);\r
 768         \r
 769         DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);\r
 770         \r
 771         at91sam7_read_clock_info(bank); \r
 772 \r
 773         for (pagen=first_page; pagen<last_page; pagen++) \r
 774         {\r
 775                 if (bytes_remaining<dst_min_alignment)\r
 776                         count = bytes_remaining;\r
 777                 else\r
 778                         count = dst_min_alignment;\r
 779                 bytes_remaining -= count;\r
 780                 \r
 781                 /* Write one block to the PageWriteBuffer */\r
 782                 buffer_pos = (pagen-first_page)*dst_min_alignment;\r
 783                 wcount = CEIL(count,4);\r
 784                 target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);\r
 785                 flashplane = (pagen>>10)&0x3;\r
 786                 \r
 787                 /* Configure the flash controller timing */     \r
 788                 at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH);\r
 789                 /* Send Write Page command to Flash Controller */\r
 790                 if (at91sam7_flash_command(bank, flashplane, WP, pagen) != ERROR_OK) \r
 791                 {\r
 792                                 return ERROR_FLASH_OPERATION_FAILED;\r
 793                 }\r
 794                 DEBUG("Write flash plane:%i page number:%i", flashplane, pagen);\r
 795         }\r
 796         \r
 797         return ERROR_OK;\r
 798 }\r
 799 \r
 800 \r
 801 int at91sam7_probe(struct flash_bank_s *bank)\r
 802 {\r
 803         /* we can't probe on an at91sam7\r
 804          * if this is an at91sam7, it has the configured flash\r
 805          */\r
 806         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 807         at91sam7_info->probed = 0;\r
 808         \r
 809         if (at91sam7_info->cidr == 0)\r
 810         {\r
 811                 at91sam7_read_part_info(bank);\r
 812         }\r
 813 \r
 814         if (at91sam7_info->cidr == 0)\r
 815         {\r
 816                 WARNING("Cannot identify target as an AT91SAM");\r
 817                 return ERROR_FLASH_OPERATION_FAILED;\r
 818         }\r
 819         \r
 820         at91sam7_info->probed = 1;\r
 821         \r
 822         return ERROR_OK;\r
 823 }\r
 824 \r
 825 \r
 826 int at91sam7_auto_probe(struct flash_bank_s *bank)\r
 827 {\r
 828         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 829         if (at91sam7_info->probed)\r
 830                 return ERROR_OK;\r
 831         return at91sam7_probe(bank);\r
 832 }\r
 833 \r
 834 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)\r
 835 {\r
 836         int printed, flashplane;\r
 837         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;\r
 838         \r
 839         at91sam7_read_part_info(bank);\r
 840 \r
 841         if (at91sam7_info->cidr == 0)\r
 842         {\r
 843                 printed = snprintf(buf, buf_size, "Cannot identify target as an AT91SAM\n");\r
 844                 buf += printed;\r
 845                 buf_size -= printed;\r
 846                 return ERROR_FLASH_OPERATION_FAILED;\r
 847         }\r
 848         \r
 849         printed = snprintf(buf, buf_size, "\nat91sam7 information: Chip is %s\n",at91sam7_info->target_name);\r
 850         buf += printed;\r
 851         buf_size -= printed;\r
 852         \r
 853         printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x,  flashsize: 0x%8.8x\n",\r
 854                   at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size);\r
 855         buf += printed;\r
 856         buf_size -= printed;\r
 857                         \r
 858         printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz \n", at91sam7_info->mck_freq / 1000);\r
 859         buf += printed;\r
 860         buf_size -= printed;\r
 861         \r
 862         if (at91sam7_info->num_planes>1) {              \r
 863                 printed = snprintf(buf, buf_size, "flashplanes: %i, pagesize: %i, lock regions: %i, pages in lock region: %i \n", \r
 864                            at91sam7_info->num_planes, at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->num_pages/at91sam7_info->num_lockbits);\r
 865                 buf += printed;\r
 866                 buf_size -= printed;\r
 867                 for (flashplane=0; flashplane<at91sam7_info->num_planes; flashplane++)\r
 868                 {\r
 869                         printed = snprintf(buf, buf_size, "lockbits[%i]: 0x%4.4x,  ", flashplane, at91sam7_info->lockbits[flashplane]);\r
 870                         buf += printed;\r
 871                         buf_size -= printed;\r
 872                 }\r
 873         }\r
 874         else\r
 875         if (at91sam7_info->num_lockbits>0) {            \r
 876                 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", \r
 877                            at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits[0], at91sam7_info->num_pages/at91sam7_info->num_lockbits);\r
 878                 buf += printed;\r
 879                 buf_size -= printed;\r
 880         }\r
 881                         \r
 882         printed = snprintf(buf, buf_size, "securitybit: %i, nvmbits: 0x%1.1x\n", at91sam7_info->securitybit, at91sam7_info->nvmbits);\r
 883         buf += printed;\r
 884         buf_size -= printed;\r
 885 \r
 886         return ERROR_OK;\r
 887 }\r
 888 \r
 889 /* \r
 890 * On AT91SAM7S: When the gpnvm bits are set with \r
 891 * > at91sam7 gpnvm 0 bitnr set\r
 892 * the changes are not visible in the flash controller status register MC_FSR \r
 893 * until the processor has been reset.\r
 894 * On the Olimex board this requires a power cycle.\r
 895 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):\r
 896 *       The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes\r
 897 *       Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.\r
 898 */\r
 899 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 900 {\r
 901         flash_bank_t *bank;\r
 902         int bit;\r
 903         u8  flashcmd;\r
 904         u32 status;\r
 905         char *value;\r
 906         at91sam7_flash_bank_t *at91sam7_info;\r
 907 \r
 908         if (argc < 3)\r
 909         {\r
 910                 command_print(cmd_ctx, "at91sam7 gpnvm <num> <bit> <set|clear>");\r
 911                 return ERROR_OK;\r
 912         }\r
 913         \r
 914         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));\r
 915         bit = atoi(args[1]);\r
 916         value = args[2];\r
 917 \r
 918         if (!bank)\r
 919         {\r
 920                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);\r
 921                 return ERROR_OK;\r
 922         }\r
 923 \r
 924         at91sam7_info = bank->driver_priv;\r
 925 \r
 926         if (bank->target->state != TARGET_HALTED)\r
 927         {\r
 928                 return ERROR_TARGET_NOT_HALTED;\r
 929         }\r
 930         \r
 931         if (at91sam7_info->cidr == 0)\r
 932         {\r
 933                 at91sam7_read_part_info(bank);\r
 934         }\r
 935 \r
 936         if (at91sam7_info->cidr == 0)\r
 937         {\r
 938                 WARNING("Cannot identify target as an AT91SAM");\r
 939                 return ERROR_FLASH_OPERATION_FAILED;\r
 940         }\r
 941 \r
 942         if ((bit<0) || (at91sam7_info->num_nvmbits <= bit))\r
 943         { \r
 944                 command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[1],at91sam7_info->target_name);\r
 945                 return ERROR_OK;\r
 946         }\r
 947 \r
 948         if (strcmp(value, "set") == 0)\r
 949         {\r
 950                 flashcmd = SGPB;\r
 951         }\r
 952         else if (strcmp(value, "clear") == 0)\r
 953         {\r
 954                 flashcmd = CGPB;\r
 955         }\r
 956         else\r
 957         {\r
 958                 return ERROR_COMMAND_SYNTAX_ERROR;
 959         }\r
 960 \r
 961         /* Configure the flash controller timing */\r
 962         at91sam7_read_clock_info(bank); \r
 963         at91sam7_set_flash_mode(bank, 0, FMR_TIMING_NVBITS);\r
 964         \r
 965         if (at91sam7_flash_command(bank, 0, flashcmd, (u16)(bit)) != ERROR_OK) \r
 966         {\r
 967                 return ERROR_FLASH_OPERATION_FAILED;\r
 968         }       \r
 969 \r
 970         status = at91sam7_get_flash_status(bank, 0);\r
 971         DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);\r
 972         at91sam7_info->nvmbits = (status>>8)&((1<<at91sam7_info->num_nvmbits)-1);\r
 973 \r
 974         return ERROR_OK;\r
 975 }\r