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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                        *
   4  *                                                                                                             *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 /***************************************************************************
  22 There are some things to notice
  23
  24 * AT91SAM7S64 is tested
  25 * All AT91SAM7Sxx  and  AT91SAM7Xxx should work but is not tested
  26 * All parameters are identified from onchip configuartion registers
  27 *
  28 * The flash controller handles erases automatically on a page (128/265 byte) basis
  29 * Only an EraseAll command is supported by the controller
  30 * Partial erases can be implemented in software by writing one 0xFFFFFFFF word to
  31 * some location in every page in the region to be erased
  32 *
  33 * Lock regions (sectors) are 32 or 64 pages
  34 *
  35  ***************************************************************************/
  36 #ifdef HAVE_CONFIG_H
  37 #include "config.h"
  38 #endif
  39
  40 #include "replacements.h"
  41
  42 #include "at91sam7.h"
  43
  44 #include "flash.h"
  45 #include "target.h"
  46 #include "log.h"
  47 #include "binarybuffer.h"
  48 #include "types.h"
  49
  50 #include <stdlib.h>
  51 #include <string.h>
  52 #include <unistd.h>
  53
  54 int at91sam7_register_commands(struct command_context_s *cmd_ctx);
  55 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  56 int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
  57 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
  58 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  59 int at91sam7_probe(struct flash_bank_s *bank);
  60 int at91sam7_erase_check(struct flash_bank_s *bank);
  61 int at91sam7_protect_check(struct flash_bank_s *bank);
  62 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
  63
  64 u32 at91sam7_get_flash_status(flash_bank_t *bank);
  65 void at91sam7_set_flash_mode(flash_bank_t *bank,int mode);
  66 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
  67 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  68
  69 flash_driver_t at91sam7_flash =
  70 {
  71         .name = "at91sam7",
  72         .register_commands = at91sam7_register_commands,
  73         .flash_bank_command = at91sam7_flash_bank_command,
  74         .erase = at91sam7_erase,
  75         .protect = at91sam7_protect,
  76         .write = at91sam7_write,
  77         .probe = at91sam7_probe,
  78         .erase_check = at91sam7_erase_check,
  79         .protect_check = at91sam7_protect_check,
  80         .info = at91sam7_info
  81 };
  82
  83
  84 char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
  85 long NVPSIZ[16] = {
  86    0,
  87    0x2000, /*  8K */
  88    0x4000, /* 16K */
  89    0x8000, /* 32K */
  90    -1,
  91    0x10000, /* 64K */
  92    -1,
  93    0x20000, /* 128K */
  94    -1,
  95    0x40000, /* 256K */
  96    0x80000, /* 512K */
  97    -1,
  98    0x100000, /* 1024K */
  99    -1,
 100    0x200000, /* 2048K */
 101    -1
 102 };
 103
 104 long SRAMSIZ[16] = {
 105    -1,
 106    0x0400, /*  1K */
 107    0x0800, /*  2K */
 108    -1,
 109    0x1c000,  /* 112K */
 110    0x1000,  /*   4K */
 111    0x14000, /*  80K */
 112    0x28000, /* 160K */
 113    0x2000,  /*   8K */
 114    0x4000,  /*  16K */
 115    0x8000,  /*  32K */
 116    0x10000, /*  64K */
 117    0x20000, /* 128K */
 118    0x40000, /* 256K */
 119    0x18000, /* 96K */
 120    0x80000, /* 512K */
 121 };
 122
 123 int at91sam7_register_commands(struct command_context_s *cmd_ctx)
 124 {
 125         command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
 126         register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
 127                         "at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");
 128
 129         return ERROR_OK;
 130 }
 131
 132 u32 at91sam7_get_flash_status(flash_bank_t *bank)
 133 {
 134         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 135         target_t *target = at91sam7_info->target;
 136         u32 fsr;
 137
 138         target_read_u32(target, MC_FSR, &fsr);
 139
 140         return fsr;
 141 }
 142
 143 /** Read clock configuration and set at91sam7_info->usec_clocks*/
 144 void at91sam7_read_clock_info(flash_bank_t *bank)
 145 {
 146         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 147         target_t *target = at91sam7_info->target;
 148         u32 mckr, mcfr, pllr;
 149         unsigned long tmp, mainfreq;
 150
 151         /* Read main clock freqency register */
 152         target_read_u32(target, CKGR_MCFR, &mcfr);
 153         /* Read master clock register */
 154         target_read_u32(target, PMC_MCKR, &mckr);
 155         /* Read Clock Generator PLL Register  */
 156         target_read_u32(target, CKGR_PLLR, &pllr);
 157
 158         at91sam7_info->mck_valid = 0;
 159         switch (mckr & PMC_MCKR_CSS) {
 160         case 0:                 /* Slow Clock */
 161                 at91sam7_info->mck_valid = 1;
 162                 tmp = RC_FREQ;
 163                 break;
 164         case 1:                 /* Main Clock */
 165                 if (mcfr & CKGR_MCFR_MAINRDY)
 166                 {
 167                         at91sam7_info->mck_valid = 1;
 168                         mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
 169                         tmp = mainfreq;
 170                 }
 171                 break;
 172
 173         case 2:                 /* Reserved */
 174                 break;
 175         case 3:         /* PLL Clock */
 176                 if (mcfr & CKGR_MCFR_MAINRDY)
 177                 {
 178                         target_read_u32(target, CKGR_PLLR, &pllr);
 179                         if (!(pllr & CKGR_PLLR_DIV))
 180                                 break; /* 0 Hz */
 181                         at91sam7_info->mck_valid = 1;
 182                         mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
 183                         /* Integer arithmetic should have sufficient precision
 184                            as long as PLL is properly configured. */
 185                         tmp = mainfreq / (pllr & CKGR_PLLR_DIV) *
 186                           (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
 187                 }
 188                 break;
 189         }
 190
 191         /* Prescaler adjust */
 192         if (((mckr & PMC_MCKR_PRES) >> 2) == 7)
 193                 at91sam7_info->mck_valid = 0;
 194         else
 195                 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
 196
 197         /* Forget old flash timing */
 198        at91sam7_set_flash_mode(bank,FMR_TIMING_NONE);
 199 }
 200
 201 /* Setup the timimg registers for nvbits or normal flash */
 202 void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
 203 {
 204         u32 fmr, fmcn = 0, fws = 0;
 205         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 206         target_t *target = at91sam7_info->target;
 207
 208         if (mode && (mode != at91sam7_info->flashmode))
 209         {
 210                 /* Always round up (ceil) */
 211               if (mode==FMR_TIMING_NVBITS)
 212               {
 213                      if (at91sam7_info->cidr_arch == 0x60)
 214                      {
 215                             /* AT91SAM7A3 uses master clocks in 100 ns */
 216                             fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
 217                      }
 218                      else
 219                      {
 220                             /* master clocks in 1uS for ARCH 0x7 types */
 221                             fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
 222                      }
 223               }
 224               else if (mode==FMR_TIMING_FLASH)
 225                         /* main clocks in 1.5uS */
 226                         fmcn = (at91sam7_info->mck_freq/666666ul)+1;
 227
 228                 /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
 229                 if (at91sam7_info->mck_freq <= 33333ul)
 230                         fmcn = 0;
 231                 /* Only allow fws=0 if clock frequency is < 30 MHz. */
 232                 if (at91sam7_info->mck_freq > 30000000ul)
 233                         fws = 1;
 234
 235                 DEBUG("fmcn: %i", fmcn);
 236                 fmr = fmcn << 16 | fws << 8;
 237                 target_write_u32(target, MC_FMR, fmr);
 238         }
 239
 240         at91sam7_info->flashmode = mode;
 241 }
 242
 243 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
 244 {
 245         u32 status;
 246
 247        while ((!((status = at91sam7_get_flash_status(bank)) & waitbits)) && (timeout-- > 0))
 248         {
 249                 DEBUG("status: 0x%x", status);
 250                 usleep(1000);
 251         }
 252
 253         DEBUG("status: 0x%x", status);
 254
 255         if (status & 0x0C)
 256         {
 257                 ERROR("status register: 0x%x", status);
 258                 if (status & 0x4)
 259                         ERROR("Lock Error Bit Detected, Operation Abort");
 260                 if (status & 0x8)
 261                         ERROR("Invalid command and/or bad keyword, Operation Abort");
 262                 if (status & 0x10)
 263                         ERROR("Security Bit Set, Operation Abort");
 264         }
 265
 266         return status;
 267 }
 268
 269
 270 /* Send one command to the AT91SAM flash controller */
 271 int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
 272 {
 273         u32 fcr;
 274         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 275         target_t *target = at91sam7_info->target;
 276
 277         fcr = (0x5A<<24) | (pagen<<8) | cmd;
 278         target_write_u32(target, MC_FCR, fcr);
 279         DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen);
 280
 281        if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
 282         {
 283               /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
 284               if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
 285               {
 286                      return ERROR_FLASH_OPERATION_FAILED;
 287               }
 288               return ERROR_OK;
 289        }
 290
 291        if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
 292        {
 293                 return ERROR_FLASH_OPERATION_FAILED;
 294         }
 295         return ERROR_OK;
 296 }
 297
 298 /* Read device id register, main clock frequency register and fill in driver info structure */
 299 int at91sam7_read_part_info(struct flash_bank_s *bank)
 300 {
 301         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 302         target_t *target = at91sam7_info->target;
 303         u32 cidr, status;
 304
 305         if (at91sam7_info->target->state != TARGET_HALTED)
 306         {
 307                 return ERROR_TARGET_NOT_HALTED;
 308         }
 309
 310         /* Read and parse chip identification register */
 311         target_read_u32(target, DBGU_CIDR, &cidr);
 312
 313         if (cidr == 0)
 314         {
 315                 WARNING("Cannot identify target as an AT91SAM");
 316                 return ERROR_FLASH_OPERATION_FAILED;
 317         }
 318
 319         at91sam7_info->cidr = cidr;
 320         at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
 321         at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
 322         at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
 323         at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
 324         at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
 325         at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
 326         at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
 327         at91sam7_info->cidr_version = cidr&0x001F;
 328         bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz];
 329         at91sam7_info->target_name = "Unknown";
 330
 331         DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
 332
 333         /* Read main and master clock freqency register */
 334         at91sam7_read_clock_info(bank);
 335
 336         status = at91sam7_get_flash_status(bank);
 337         at91sam7_info->lockbits = status>>16;
 338         at91sam7_info->securitybit = (status>>4)&0x01;
 339
 340         if (at91sam7_info->cidr_arch == 0x70 )
 341         {
 342                 at91sam7_info->num_nvmbits = 2;
 343                 at91sam7_info->nvmbits = (status>>8)&0x03;
 344                 bank->base = 0x100000;
 345                 bank->bus_width = 4;
 346                 if (bank->size==0x40000)  /* AT91SAM7S256 */
 347                 {
 348                         at91sam7_info->target_name = "AT91SAM7S256";
 349                         at91sam7_info->num_lockbits = 16;
 350                         at91sam7_info->pagesize = 256;
 351                         at91sam7_info->pages_in_lockregion = 64;
 352                         at91sam7_info->num_pages = 16*64;
 353                 }
 354                 if (bank->size==0x20000)  /* AT91SAM7S128 */
 355                 {
 356                         at91sam7_info->target_name = "AT91SAM7S128";
 357                         at91sam7_info->num_lockbits = 8;
 358                         at91sam7_info->pagesize = 256;
 359                         at91sam7_info->pages_in_lockregion = 64;
 360                         at91sam7_info->num_pages = 8*64;
 361                 }
 362                 if (bank->size==0x10000)  /* AT91SAM7S64 */
 363                 {
 364                         at91sam7_info->target_name = "AT91SAM7S64";
 365                         at91sam7_info->num_lockbits = 16;
 366                         at91sam7_info->pagesize = 128;
 367                         at91sam7_info->pages_in_lockregion = 32;
 368                         at91sam7_info->num_pages = 16*32;
 369                 }
 370                 if (bank->size==0x08000)  /* AT91SAM7S321/32 */
 371                 {
 372                         at91sam7_info->target_name = "AT91SAM7S321/32";
 373                         at91sam7_info->num_lockbits = 8;
 374                         at91sam7_info->pagesize = 128;
 375                         at91sam7_info->pages_in_lockregion = 32;
 376                         at91sam7_info->num_pages = 8*32;
 377                 }
 378
 379                 return ERROR_OK;
 380         }
 381
 382         if (at91sam7_info->cidr_arch == 0x71 )
 383         {
 384                 at91sam7_info->num_nvmbits = 2;
 385                 at91sam7_info->nvmbits = (status>>8)&0x03;
 386                 bank->base = 0x100000;
 387                 bank->bus_width = 4;
 388                 if (bank->size==0x40000)  /* AT91SAM7XC256 */
 389                 {
 390                         at91sam7_info->target_name = "AT91SAM7XC256";
 391                         at91sam7_info->num_lockbits = 16;
 392                         at91sam7_info->pagesize = 256;
 393                         at91sam7_info->pages_in_lockregion = 64;
 394                         at91sam7_info->num_pages = 16*64;
 395                 }
 396                 if (bank->size==0x20000)  /* AT91SAM7XC128 */
 397                 {
 398                         at91sam7_info->target_name = "AT91SAM7XC128";
 399                         at91sam7_info->num_lockbits = 8;
 400                         at91sam7_info->pagesize = 256;
 401                         at91sam7_info->pages_in_lockregion = 64;
 402                         at91sam7_info->num_pages = 8*64;
 403                 }
 404
 405                 return ERROR_OK;
 406         }
 407
 408         if (at91sam7_info->cidr_arch == 0x75 )
 409         {
 410                 at91sam7_info->num_nvmbits = 3;
 411                 at91sam7_info->nvmbits = (status>>8)&0x07;
 412                 bank->base = 0x100000;
 413                 bank->bus_width = 4;
 414                 if (bank->size==0x40000)  /* AT91SAM7X256 */
 415                 {
 416                         at91sam7_info->target_name = "AT91SAM7X256";
 417                         at91sam7_info->num_lockbits = 16;
 418                         at91sam7_info->pagesize = 256;
 419                         at91sam7_info->pages_in_lockregion = 64;
 420                         at91sam7_info->num_pages = 16*64;
 421                 }
 422                 if (bank->size==0x20000)  /* AT91SAM7X128 */
 423                 {
 424                         at91sam7_info->target_name = "AT91SAM7X128";
 425                         at91sam7_info->num_lockbits = 8;
 426                         at91sam7_info->pagesize = 256;
 427                         at91sam7_info->pages_in_lockregion = 64;
 428                         at91sam7_info->num_pages = 8*64;
 429                 }
 430
 431                 return ERROR_OK;
 432         }
 433
 434         if (at91sam7_info->cidr_arch == 0x60 )
 435         {
 436                 at91sam7_info->num_nvmbits = 3;
 437                 at91sam7_info->nvmbits = (status>>8)&0x07;
 438                 bank->base = 0x100000;
 439                 bank->bus_width = 4;
 440
 441                 if (bank->size == 0x40000)  /* AT91SAM7A3 */
 442                 {
 443                         at91sam7_info->target_name = "AT91SAM7A3";
 444                         at91sam7_info->num_lockbits = 16;
 445                         at91sam7_info->pagesize = 256;
 446                      at91sam7_info->pages_in_lockregion = 16;
 447                         at91sam7_info->num_pages = 16*64;
 448                 }
 449                 return ERROR_OK;
 450         }
 451
 452    WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
 453
 454    return ERROR_OK;
 455 }
 456
 457 int at91sam7_erase_check(struct flash_bank_s *bank)
 458 {
 459         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 460         target_t *target = at91sam7_info->target;
 461         int i;
 462
 463         if (!at91sam7_info->working_area_size)
 464         {
 465         }
 466         else
 467         {
 468         }
 469
 470         return ERROR_OK;
 471 }
 472
 473 int at91sam7_protect_check(struct flash_bank_s *bank)
 474 {
 475         u32 status;
 476
 477         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 478         target_t *target = at91sam7_info->target;
 479
 480         if (at91sam7_info->cidr == 0)
 481         {
 482                 at91sam7_read_part_info(bank);
 483         }
 484
 485         if (at91sam7_info->cidr == 0)
 486         {
 487                 WARNING("Cannot identify target as an AT91SAM");
 488                 return ERROR_FLASH_OPERATION_FAILED;
 489         }
 490
 491         status = at91sam7_get_flash_status(bank);
 492         at91sam7_info->lockbits = status >> 16;
 493
 494         return ERROR_OK;
 495 }
 496
 497 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 498 {
 499         at91sam7_flash_bank_t *at91sam7_info;
 500
 501         if (argc < 6)
 502         {
 503                 WARNING("incomplete flash_bank at91sam7 configuration");
 504                 return ERROR_FLASH_BANK_INVALID;
 505         }
 506
 507         at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));
 508         bank->driver_priv = at91sam7_info;
 509
 510         at91sam7_info->target = get_target_by_num(strtoul(args[5], NULL, 0));
 511         if (!at91sam7_info->target)
 512         {
 513                 ERROR("no target '%i' configured", args[5]);
 514                 exit(-1);
 515         }
 516
 517         /* part wasn't probed for info yet */
 518         at91sam7_info->cidr = 0;
 519
 520         return ERROR_OK;
 521 }
 522
 523 int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
 524 {
 525         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 526
 527         if (at91sam7_info->target->state != TARGET_HALTED)
 528         {
 529                 return ERROR_TARGET_NOT_HALTED;
 530         }
 531
 532         if (at91sam7_info->cidr == 0)
 533         {
 534                 at91sam7_read_part_info(bank);
 535         }
 536
 537         if (at91sam7_info->cidr == 0)
 538         {
 539                 WARNING("Cannot identify target as an AT91SAM");
 540                 return ERROR_FLASH_OPERATION_FAILED;
 541         }
 542
 543         if ((first < 0) || (last < first) || (last >= at91sam7_info->num_lockbits))
 544         {
 545                 return ERROR_FLASH_SECTOR_INVALID;
 546         }
 547
 548         /* Configure the flash controller timing */
 549         at91sam7_read_clock_info(bank);
 550        at91sam7_set_flash_mode(bank,FMR_TIMING_FLASH);
 551
 552         if ((first == 0) && (last == (at91sam7_info->num_lockbits-1)))
 553         {
 554                 return at91sam7_flash_command(bank, EA, 0);
 555         }
 556
 557         WARNING("Can only erase the whole flash area, pages are autoerased on write");
 558         return ERROR_FLASH_OPERATION_FAILED;
 559 }
 560
 561 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
 562 {
 563         u32 cmd, pagen, status;
 564         int lockregion;
 565
 566         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 567         target_t *target = at91sam7_info->target;
 568
 569         if (at91sam7_info->target->state != TARGET_HALTED)
 570         {
 571                 return ERROR_TARGET_NOT_HALTED;
 572         }
 573
 574         if ((first < 0) || (last < first) || (last >= at91sam7_info->num_lockbits))
 575         {
 576                 return ERROR_FLASH_SECTOR_INVALID;
 577         }
 578
 579         if (at91sam7_info->cidr == 0)
 580         {
 581                 at91sam7_read_part_info(bank);
 582         }
 583
 584         if (at91sam7_info->cidr == 0)
 585         {
 586                 WARNING("Cannot identify target as an AT91SAM");
 587                 return ERROR_FLASH_OPERATION_FAILED;
 588         }
 589
 590         /* Configure the flash controller timing */
 591         at91sam7_read_clock_info(bank);
 592        at91sam7_set_flash_mode(bank,FMR_TIMING_NVBITS);
 593
 594         for (lockregion=first;lockregion<=last;lockregion++)
 595         {
 596                 pagen = lockregion*at91sam7_info->pages_in_lockregion;
 597                 if (set)
 598                          cmd = SLB;
 599                 else
 600                          cmd = CLB;
 601                 if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
 602                 {
 603                         return ERROR_FLASH_OPERATION_FAILED;
 604                 }
 605         }
 606
 607         status = at91sam7_get_flash_status(bank);
 608         at91sam7_info->lockbits = status>>16;
 609
 610         return ERROR_OK;
 611 }
 612
 613
 614 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 615 {
 616         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 617         target_t *target = at91sam7_info->target;
 618         u32 dst_min_alignment, wcount, bytes_remaining = count;
 619         u32 first_page, last_page, pagen, buffer_pos;
 620         u32 fcr;
 621
 622         if (at91sam7_info->target->state != TARGET_HALTED)
 623         {
 624                 return ERROR_TARGET_NOT_HALTED;
 625         }
 626
 627         if (at91sam7_info->cidr == 0)
 628         {
 629                 at91sam7_read_part_info(bank);
 630         }
 631
 632         if (at91sam7_info->cidr == 0)
 633         {
 634                 WARNING("Cannot identify target as an AT91SAM");
 635                 return ERROR_FLASH_OPERATION_FAILED;
 636         }
 637
 638         if (offset + count > bank->size)
 639                 return ERROR_FLASH_DST_OUT_OF_BANK;
 640
 641         dst_min_alignment = at91sam7_info->pagesize;
 642
 643         if (offset % dst_min_alignment)
 644         {
 645                 WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
 646                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 647         }
 648
 649         if (offset + count > bank->size)
 650                 return ERROR_FLASH_DST_OUT_OF_BANK;
 651
 652         if (at91sam7_info->cidr_arch == 0)
 653                 return ERROR_FLASH_BANK_NOT_PROBED;
 654
 655         first_page = offset/dst_min_alignment;
 656         last_page = CEIL(offset + count, dst_min_alignment);
 657
 658         DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
 659
 660         /* Configure the flash controller timing */
 661         at91sam7_read_clock_info(bank);
 662        at91sam7_set_flash_mode(bank,FMR_TIMING_FLASH);
 663
 664         for (pagen=first_page; pagen<last_page; pagen++) {
 665                 if (bytes_remaining<dst_min_alignment)
 666                 count = bytes_remaining;
 667                 else
 668                 count = dst_min_alignment;
 669                 bytes_remaining -= count;
 670
 671                 /* Write one block to the PageWriteBuffer */
 672                 buffer_pos = (pagen-first_page)*dst_min_alignment;
 673                 wcount = CEIL(count,4);
 674                 target->type->write_memory(target, bank->base, 4, wcount, buffer+buffer_pos);
 675
 676                 /* Send Write Page command to Flash Controller */
 677                 if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
 678                 {
 679                         return ERROR_FLASH_OPERATION_FAILED;
 680                 }
 681                 DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen);
 682         }
 683
 684         return ERROR_OK;
 685 }
 686
 687
 688 int at91sam7_probe(struct flash_bank_s *bank)
 689 {
 690         /* we can't probe on an at91sam7
 691          * if this is an at91sam7, it has the configured flash
 692          */
 693         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 694
 695         if (at91sam7_info->cidr == 0)
 696         {
 697                 at91sam7_read_part_info(bank);
 698         }
 699
 700         if (at91sam7_info->cidr == 0)
 701         {
 702                 WARNING("Cannot identify target as an AT91SAM");
 703                 return ERROR_FLASH_OPERATION_FAILED;
 704         }
 705
 706         return ERROR_OK;
 707 }
 708
 709 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
 710 {
 711         int printed;
 712         at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
 713
 714         at91sam7_read_part_info(bank);
 715
 716         if (at91sam7_info->cidr == 0)
 717         {
 718                 printed = snprintf(buf, buf_size, "Cannot identify target as an AT91SAM\n");
 719                 buf += printed;
 720                 buf_size -= printed;
 721                 return ERROR_FLASH_OPERATION_FAILED;
 722         }
 723
 724        printed = snprintf(buf, buf_size, "\nat91sam7 information: Chip is %s\n",at91sam7_info->target_name);
 725         buf += printed;
 726         buf_size -= printed;
 727
 728         printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x,  flashsize: 0x%8.8x\n", at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size);
 729         buf += printed;
 730         buf_size -= printed;
 731
 732         printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz \n", at91sam7_info->mck_freq / 1000);
 733         buf += printed;
 734         buf_size -= printed;
 735
 736         if (at91sam7_info->num_lockbits>0) {
 737                 printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits,at91sam7_info->num_pages/at91sam7_info->num_lockbits);
 738                 buf += printed;
 739                 buf_size -= printed;
 740         }
 741
 742         printed = snprintf(buf, buf_size, "securitybit: %i, nvmbits: 0x%1.1x\n", at91sam7_info->securitybit, at91sam7_info->nvmbits);
 743         buf += printed;
 744         buf_size -= printed;
 745
 746         return ERROR_OK;
 747 }
 748
 749 /*
 750 * On AT91SAM7S: When the gpnmv bits are set with
 751 * > at91sam7 gpnvm 0 bitnr set
 752 * the changes are not visible in the flash controller status register MC_FSR
 753 * until the processor has been reset.
 754 * On the Olimex board this requires a power cycle.
 755 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
 756 *       The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
 757 *       Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
 758 */
 759 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 760 {
 761         flash_bank_t *bank;
 762         int bit;
 763         u8  flashcmd;
 764         u32 status;
 765         char *value;
 766         at91sam7_flash_bank_t *at91sam7_info;
 767
 768         if (argc < 3)
 769         {
 770                 command_print(cmd_ctx, "at91sam7 gpnvm <num> <bit> <set|clear>");
 771                 return ERROR_OK;
 772         }
 773
 774         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 775         bit = atoi(args[1]);
 776         value = args[2];
 777
 778         if (!bank)
 779         {
 780                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 781                 return ERROR_OK;
 782         }
 783
 784         at91sam7_info = bank->driver_priv;
 785
 786         if (at91sam7_info->target->state != TARGET_HALTED)
 787         {
 788                 return ERROR_TARGET_NOT_HALTED;
 789         }
 790
 791         if (at91sam7_info->cidr == 0)
 792         {
 793                 at91sam7_read_part_info(bank);
 794         }
 795
 796         if (at91sam7_info->cidr == 0)
 797         {
 798                 WARNING("Cannot identify target as an AT91SAM");
 799                 return ERROR_FLASH_OPERATION_FAILED;
 800         }
 801
 802         if ((bit<0) || (at91sam7_info->num_nvmbits <= bit))
 803         {
 804                 command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[1],at91sam7_info->target_name);
 805                 return ERROR_OK;
 806         }
 807
 808         if (strcmp(value, "set") == 0)
 809         {
 810                 flashcmd = SGPB;
 811         }
 812         else if (strcmp(value, "clear") == 0)
 813         {
 814                 flashcmd = CGPB;
 815         }
 816         else
 817         {
 818                 command_print(cmd_ctx, "usage: at91sam7 gpnvm <num> <bit> <set|clear>");
 819                 return ERROR_OK;
 820         }
 821
 822         /* Configure the flash controller timing */
 823         at91sam7_read_clock_info(bank);
 824        at91sam7_set_flash_mode(bank,FMR_TIMING_NVBITS);
 825
 826         if (at91sam7_flash_command(bank, flashcmd, (u16)(bit)) != ERROR_OK)
 827         {
 828                 return ERROR_FLASH_OPERATION_FAILED;
 829         }
 830
 831         status = at91sam7_get_flash_status(bank);
 832         DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status);
 833         at91sam7_info->nvmbits = (status>>8)&((1<<at91sam7_info->num_nvmbits)-1);
 834
 835         return ERROR_OK;
 836 }