1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
69 #include "time_support.h"
71 #define REG_NAME_WIDTH (12)
74 #define FLASH_BANK0_BASE 0x00080000
75 #define FLASH_BANK1_BASE 0x00100000
77 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
78 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
79 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
80 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
81 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
82 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
83 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
84 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
85 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
87 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
88 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
89 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
90 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
91 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
92 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
93 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
94 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
96 #define offset_EFC_FMR 0
97 #define offset_EFC_FCR 4
98 #define offset_EFC_FSR 8
99 #define offset_EFC_FRR 12
103 _tomhz(uint32_t freq_hz)
107 f = ((float)(freq_hz)) / 1000000.0;
111 // How the chip is configured.
113 uint32_t unique_id[4];
117 uint32_t mainosc_freq;
127 #define SAM3_CHIPID_CIDR (0x400E0740)
128 uint32_t CHIPID_CIDR;
129 #define SAM3_CHIPID_EXID (0x400E0744)
130 uint32_t CHIPID_EXID;
132 #define SAM3_SUPC_CR (0x400E1210)
135 #define SAM3_PMC_BASE (0x400E0400)
136 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
138 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
140 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
142 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
144 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
146 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
148 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
150 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
152 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
154 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
156 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
158 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
160 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
162 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
167 struct sam3_bank_private {
169 // DANGER: THERE ARE DRAGONS HERE..
170 // NOTE: If you add more 'ghost' pointers
171 // be aware that you must *manually* update
172 // these pointers in the function sam3_GetDetails()
173 // See the comment "Here there be dragons"
175 // so we can find the chip we belong to
176 struct sam3_chip *pChip;
177 // so we can find the orginal bank pointer
179 unsigned bank_number;
180 uint32_t controller_address;
181 uint32_t base_address;
185 unsigned sector_size;
189 struct sam3_chip_details {
190 // THERE ARE DRAGONS HERE..
191 // note: If you add pointers here
192 // becareful about them as they
193 // may need to be updated inside
194 // the function: "sam3_GetDetails()
195 // which copy/overwrites the
196 // 'runtime' copy of this structure
197 uint32_t chipid_cidr;
201 #define SAM3_N_NVM_BITS 3
202 unsigned gpnvm[SAM3_N_NVM_BITS];
203 unsigned total_flash_size;
204 unsigned total_sram_size;
206 #define SAM3_MAX_FLASH_BANKS 2
207 // these are "initialized" from the global const data
208 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
213 struct sam3_chip *next;
216 // this is "initialized" from the global const structure
217 struct sam3_chip_details details;
225 struct sam3_reg_list {
226 uint32_t address; size_t struct_offset; const char *name;
227 void (*explain_func)(struct sam3_chip *pInfo);
231 static struct sam3_chip *all_sam3_chips;
233 static struct sam3_chip *
234 get_current_sam3(struct command_context_s *cmd_ctx)
237 static struct sam3_chip *p;
239 t = get_current_target(cmd_ctx);
241 command_print(cmd_ctx, "No current target?");
247 // this should not happen
248 // the command is not registered until the chip is created?
249 command_print(cmd_ctx, "No SAM3 chips exist?");
254 if (p->target == t) {
259 command_print(cmd_ctx, "Cannot find SAM3 chip?");
264 // these are used to *initialize* the "pChip->details" structure.
265 static const struct sam3_chip_details all_sam3_details[] = {
267 .chipid_cidr = 0x28100960,
268 .name = "at91sam3u4e",
269 .total_flash_size = 256 * 1024,
270 .total_sram_size = 52 * 1024,
274 // System boots at address 0x0
275 // gpnvm[1] = selects boot code
277 // boot is via "SAMBA" (rom)
280 // Selection is via gpnvm[2]
283 // NOTE: banks 0 & 1 switch places
285 // Bank0 is the boot rom
287 // Bank1 is the boot rom
296 .base_address = FLASH_BANK0_BASE,
297 .controller_address = 0x400e0800,
299 .size_bytes = 128 * 1024,
311 .base_address = FLASH_BANK1_BASE,
312 .controller_address = 0x400e0a00,
314 .size_bytes = 128 * 1024,
323 .chipid_cidr = 0x281a0760,
324 .name = "at91sam3u2e",
325 .total_flash_size = 128 * 1024,
326 .total_sram_size = 36 * 1024,
330 // System boots at address 0x0
331 // gpnvm[1] = selects boot code
333 // boot is via "SAMBA" (rom)
336 // Selection is via gpnvm[2]
345 .base_address = FLASH_BANK0_BASE,
346 .controller_address = 0x400e0800,
348 .size_bytes = 128 * 1024,
362 .chipid_cidr = 0x28190560,
363 .name = "at91sam3u1e",
364 .total_flash_size = 64 * 1024,
365 .total_sram_size = 20 * 1024,
369 // System boots at address 0x0
370 // gpnvm[1] = selects boot code
372 // boot is via "SAMBA" (rom)
375 // Selection is via gpnvm[2]
386 .base_address = FLASH_BANK0_BASE,
387 .controller_address = 0x400e0800,
389 .size_bytes = 64 * 1024,
405 .chipid_cidr = 0x28000960,
406 .name = "at91sam3u4c",
407 .total_flash_size = 256 * 1024,
408 .total_sram_size = 52 * 1024,
412 // System boots at address 0x0
413 // gpnvm[1] = selects boot code
415 // boot is via "SAMBA" (rom)
418 // Selection is via gpnvm[2]
421 // NOTE: banks 0 & 1 switch places
423 // Bank0 is the boot rom
425 // Bank1 is the boot rom
434 .base_address = FLASH_BANK0_BASE,
435 .controller_address = 0x400e0800,
437 .size_bytes = 128 * 1024,
448 .base_address = FLASH_BANK1_BASE,
449 .controller_address = 0x400e0a00,
451 .size_bytes = 128 * 1024,
460 .chipid_cidr = 0x280a0760,
461 .name = "at91sam3u2c",
462 .total_flash_size = 128 * 1024,
463 .total_sram_size = 36 * 1024,
467 // System boots at address 0x0
468 // gpnvm[1] = selects boot code
470 // boot is via "SAMBA" (rom)
473 // Selection is via gpnvm[2]
482 .base_address = FLASH_BANK0_BASE,
483 .controller_address = 0x400e0800,
485 .size_bytes = 128 * 1024,
499 .chipid_cidr = 0x28090560,
500 .name = "at91sam3u1c",
501 .total_flash_size = 64 * 1024,
502 .total_sram_size = 20 * 1024,
506 // System boots at address 0x0
507 // gpnvm[1] = selects boot code
509 // boot is via "SAMBA" (rom)
512 // Selection is via gpnvm[2]
523 .base_address = FLASH_BANK0_BASE,
524 .controller_address = 0x400e0800,
526 .size_bytes = 64 * 1024,
549 /***********************************************************************
550 **********************************************************************
551 **********************************************************************
552 **********************************************************************
553 **********************************************************************
554 **********************************************************************/
555 /* *ATMEL* style code - from the SAM3 driver code */
557 /** Get the current status of the EEFC
559 * the value of some status bits (LOCKE, PROGE).
560 * @param pPrivate - info about the bank
561 * @param v - result goes here
564 EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
567 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
568 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
570 ((unsigned int)((*v >> 2) & 1)),
571 ((unsigned int)((*v >> 1) & 1)),
572 ((unsigned int)((*v >> 0) & 1)));
577 /** Get the result of the last executed command.
578 * @param pPrivate - info about the bank
579 * @param v - result goes here
582 EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
586 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
590 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
595 EFC_StartCommand(struct sam3_bank_private *pPrivate,
596 unsigned command, unsigned argument)
605 // Check command & argument
608 case AT91C_EFC_FCMD_WP:
609 case AT91C_EFC_FCMD_WPL:
610 case AT91C_EFC_FCMD_EWP:
611 case AT91C_EFC_FCMD_EWPL:
612 // case AT91C_EFC_FCMD_EPL:
613 // case AT91C_EFC_FCMD_EPA:
614 case AT91C_EFC_FCMD_SLB:
615 case AT91C_EFC_FCMD_CLB:
616 n = (pPrivate->size_bytes / pPrivate->page_size);
618 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
622 case AT91C_EFC_FCMD_SFB:
623 case AT91C_EFC_FCMD_CFB:
624 if (argument >= pPrivate->pChip->details.n_gpnvms) {
625 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
626 pPrivate->pChip->details.n_gpnvms);
630 case AT91C_EFC_FCMD_GETD:
631 case AT91C_EFC_FCMD_EA:
632 case AT91C_EFC_FCMD_GLB:
633 case AT91C_EFC_FCMD_GFB:
634 case AT91C_EFC_FCMD_STUI:
635 case AT91C_EFC_FCMD_SPUI:
637 LOG_ERROR("Argument is meaningless for cmd: %d", command);
641 LOG_ERROR("Unknown command %d", command);
645 if (command == AT91C_EFC_FCMD_SPUI) {
646 // this is a very special situation.
647 // Situation (1) - error/retry - see below
648 // And we are being called recursively
649 // Situation (2) - normal, finished reading unique id
651 // it should be "ready"
652 EFC_GetStatus(pPrivate, &v);
658 // we have done this before
659 // the controller is not responding.
660 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
664 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
665 pPrivate->bank_number);
666 // we do that by issuing the *STOP* command
667 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
668 // above is recursive, and further recursion is blocked by
669 // if (command == AT91C_EFC_FCMD_SPUI) above
675 v = (0x5A << 24) | (argument << 8) | command;
676 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
677 r = target_write_u32(pPrivate->pBank->target,
678 pPrivate->controller_address + offset_EFC_FCR,
681 LOG_DEBUG("Error Write failed");
686 /** Performs the given command and wait until its completion (or an error).
688 * @param pPrivate - info about the bank
689 * @param command - Command to perform.
690 * @param argument - Optional command argument.
691 * @param status - put command status bits here
694 EFC_PerformCommand(struct sam3_bank_private *pPrivate,
702 long long ms_now, ms_end;
709 r = EFC_StartCommand(pPrivate, command, argument);
714 ms_end = 500 + timeval_ms();
718 r = EFC_GetStatus(pPrivate, &v);
722 ms_now = timeval_ms();
723 if (ms_now > ms_end) {
725 LOG_ERROR("Command timeout");
744 /** Read the unique ID.
746 * \param pPrivate - info about the bank
748 * The unique ID is stored in the 'pPrivate' structure.
752 FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
758 pPrivate->pChip->cfg.unique_id[0] = 0;
759 pPrivate->pChip->cfg.unique_id[1] = 0;
760 pPrivate->pChip->cfg.unique_id[2] = 0;
761 pPrivate->pChip->cfg.unique_id[3] = 0;
764 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
769 for (x = 0 ; x < 4 ; x++) {
770 r = target_read_u32(pPrivate->pChip->target,
771 pPrivate->pBank->base + (x * 4),
776 pPrivate->pChip->cfg.unique_id[x] = v;
779 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
780 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
782 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
783 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
784 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
785 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
790 /** Erases the entire flash.
791 * @param pPrivate - the info about the bank.
794 FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
797 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
802 /** Gets current GPNVM state.
803 * @param pPrivate - info about the bank.
804 * @param gpnvm - GPNVM bit index.
805 * @param puthere - result stored here.
808 //------------------------------------------------------------------------------
810 FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
816 if (pPrivate->bank_number != 0) {
817 LOG_ERROR("GPNVM only works with Bank0");
821 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
822 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
823 gpnvm,pPrivate->pChip->details.n_gpnvms);
828 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
834 r = EFC_GetResult(pPrivate, &v);
837 // Check if GPNVM is set
838 // get the bit and make it a 0/1
839 *puthere = (v >> gpnvm) & 1;
848 /** Clears the selected GPNVM bit.
849 * @param gpnvm GPNVM index.
851 * Returns 0 if successful; otherwise returns an error code.
854 FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
860 if (pPrivate->bank_number != 0) {
861 LOG_ERROR("GPNVM only works with Bank0");
865 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
866 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
867 gpnvm,pPrivate->pChip->details.n_gpnvms);
871 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
873 LOG_DEBUG("Failed: %d",r);
876 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
877 LOG_DEBUG("End: %d",r);
883 /** Sets the selected GPNVM bit.
884 * @param gpnvm GPNVM index.
888 FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
893 if (pPrivate->bank_number != 0) {
894 LOG_ERROR("GPNVM only works with Bank0");
898 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
899 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
900 gpnvm,pPrivate->pChip->details.n_gpnvms);
904 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
913 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
919 /** Returns a bit field (at most 64) of locked regions within a page.
920 * @param pPrivate - info about the bank
921 * @param v - where to store locked bits
922 * \param end End address of range.
926 FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
930 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
932 r = EFC_GetResult(pPrivate, v);
934 LOG_DEBUG("End: %d",r);
939 /**Unlocks all the regions in the given address range.
941 * \param start_sector - first sector to unlock
942 * \param end_sector - last (inclusive) to unlock
946 FLASHD_Unlock(struct sam3_bank_private *pPrivate,
947 unsigned start_sector,
953 uint32_t pages_per_sector;
955 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
957 /* Unlock all pages */
958 while (start_sector <= end_sector) {
959 pg = start_sector * pages_per_sector;
961 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
974 * @param start_sector - first sector to lock
975 * @param end_sector - last sector (inclusive) to lock
980 FLASHD_Lock(struct sam3_bank_private *pPrivate,
981 unsigned start_sector,
986 uint32_t pages_per_sector;
989 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
992 while (start_sector <= end_sector) {
993 pg = start_sector * pages_per_sector;
995 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1005 /****** END SAM3 CODE ********/
1007 /* begin helpful debug code */
1010 sam3_sprintf(struct sam3_chip *pChip , const char *fmt, ...)
1014 if (pChip->mbuf == NULL) {
1018 membuf_vsprintf(pChip->mbuf, fmt, ap);
1022 // print the fieldname, the field value, in dec & hex, and return field value
1024 sam3_reg_fieldname(struct sam3_chip *pChip,
1025 const char *regname,
1034 // extract the field
1036 v = v & ((1 << width)-1);
1046 sam3_sprintf(pChip, "\t%*s: %*d [0x%0*x] ",
1047 REG_NAME_WIDTH, regname,
1054 static const char _unknown[] = "unknown";
1055 static const char * const eproc_names[] = {
1074 #define nvpsize2 nvpsize // these two tables are identical
1075 static const char * const nvpsize[] = {
1088 "1024K bytes", // 12
1090 "2048K bytes", // 14
1095 static const char * const sramsize[] = {
1115 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1116 { 0x19, "AT91SAM9xx Series" },
1117 { 0x29, "AT91SAM9XExx Series" },
1118 { 0x34, "AT91x34 Series" },
1119 { 0x37, "CAP7 Series" },
1120 { 0x39, "CAP9 Series" },
1121 { 0x3B, "CAP11 Series" },
1122 { 0x40, "AT91x40 Series" },
1123 { 0x42, "AT91x42 Series" },
1124 { 0x55, "AT91x55 Series" },
1125 { 0x60, "AT91SAM7Axx Series" },
1126 { 0x61, "AT91SAM7AQxx Series" },
1127 { 0x63, "AT91x63 Series" },
1128 { 0x70, "AT91SAM7Sxx Series" },
1129 { 0x71, "AT91SAM7XCxx Series" },
1130 { 0x72, "AT91SAM7SExx Series" },
1131 { 0x73, "AT91SAM7Lxx Series" },
1132 { 0x75, "AT91SAM7Xxx Series" },
1133 { 0x76, "AT91SAM7SLxx Series" },
1134 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1135 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1136 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1137 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1138 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1139 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1140 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1141 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1142 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1143 { 0x92, "AT91x92 Series" },
1144 { 0xF0, "AT75Cxx Series" },
1149 static const char * const nvptype[] = {
1151 "romless or onchip flash", // 1
1152 "embedded flash memory", // 2
1153 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1154 "sram emulating flash", // 4
1161 static const char *_yes_or_no(uint32_t v)
1170 static const char * const _rc_freq[] = {
1171 "4 MHz", "8 MHz", "12 MHz", "reserved"
1175 sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1180 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1181 sam3_sprintf(pChip, "(main xtal enabled: %s)\n",
1183 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1184 sam3_sprintf(pChip, "(main osc bypass: %s)\n",
1186 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
1187 sam3_sprintf(pChip, "(onchip RC-OSC enabled: %s)\n",
1189 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1190 sam3_sprintf(pChip, "(onchip RC-OSC freq: %s)\n",
1193 pChip->cfg.rc_freq = 0;
1197 pChip->cfg.rc_freq = 0;
1199 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1202 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1205 pChip->cfg.rc_freq = 12* 1000 * 1000;
1210 v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1211 sam3_sprintf(pChip, "(startup clks, time= %f uSecs)\n",
1212 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1213 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1214 sam3_sprintf(pChip, "(mainosc source: %s)\n",
1215 v ? "external xtal" : "internal RC");
1217 v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1218 sam3_sprintf(pChip, "(clock failure enabled: %s)\n",
1225 sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1231 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1232 sam3_sprintf(pChip,"\n");
1234 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1235 sam3_sprintf(pChip, "%s\n", eproc_names[v]);
1237 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1238 sam3_sprintf(pChip, "%s\n", nvpsize[v]);
1240 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1241 sam3_sprintf(pChip, "%s\n", nvpsize2[v]);
1243 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
1244 sam3_sprintf(pChip, "%s\n", sramsize[ v ]);
1246 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1248 for (x = 0 ; archnames[x].name ; x++) {
1249 if (v == archnames[x].value) {
1250 cp = archnames[x].name;
1255 sam3_sprintf(pChip, "%s\n", cp);
1257 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1258 sam3_sprintf(pChip, "%s\n", nvptype[ v ]);
1260 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1261 sam3_sprintf(pChip, "(exists: %s)\n", _yes_or_no(v));
1265 sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1270 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1271 sam3_sprintf(pChip, "(main ready: %s)\n", _yes_or_no(v));
1273 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1275 v = (v * pChip->cfg.slow_freq) / 16;
1276 pChip->cfg.mainosc_freq = v;
1278 sam3_sprintf(pChip, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1280 pChip->cfg.slow_freq / 1000,
1281 pChip->cfg.slow_freq % 1000);
1286 sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1290 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1291 sam3_sprintf(pChip,"\n");
1292 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1293 sam3_sprintf(pChip,"\n");
1294 pChip->cfg.plla_freq = 0;
1296 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,mula = 0)\n");
1297 } else if (diva == 0) {
1298 sam3_sprintf(pChip,"\tPLLA Freq: (Disabled,diva = 0)\n");
1299 } else if (diva == 1) {
1300 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1301 sam3_sprintf(pChip,"\tPLLA Freq: %3.03f MHz\n",
1302 _tomhz(pChip->cfg.plla_freq));
1308 sam3_explain_mckr(struct sam3_chip *pChip)
1310 uint32_t css, pres,fin;
1314 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1317 fin = pChip->cfg.slow_freq;
1321 fin = pChip->cfg.mainosc_freq;
1325 fin = pChip->cfg.plla_freq;
1329 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1330 fin = 480 * 1000 * 1000;
1334 cp = "upll (*ERROR* UPLL is disabled)";
1342 sam3_sprintf(pChip, "%s (%3.03f Mhz)\n",
1345 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1346 switch (pres & 0x07) {
1349 cp = "selected clock";
1382 sam3_sprintf(pChip, "(%s)\n", cp);
1384 // sam3 has a *SINGLE* clock -
1385 // other at91 series parts have divisors for these.
1386 pChip->cfg.cpu_freq = fin;
1387 pChip->cfg.mclk_freq = fin;
1388 pChip->cfg.fclk_freq = fin;
1389 sam3_sprintf(pChip, "\t\tResult CPU Freq: %3.03f\n",
1394 static struct sam3_chip *
1395 target2sam3(target_t *pTarget)
1397 struct sam3_chip *pChip;
1399 if (pTarget == NULL) {
1403 pChip = all_sam3_chips;
1405 if (pChip->target == pTarget) {
1406 break; // return below
1408 pChip = pChip->next;
1416 sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
1418 // this function exists to help
1419 // keep funky offsetof() errors
1420 // and casting from causing bugs
1422 // By using prototypes - we can detect what would
1423 // be casting errors.
1425 return ((uint32_t *)(((char *)(pCfg)) + pList->struct_offset));
1429 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1430 static const struct sam3_reg_list sam3_all_regs[] = {
1431 SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
1432 SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
1433 SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
1434 SAM3_ENTRY(CKGR_UCKR , NULL),
1435 SAM3_ENTRY(PMC_FSMR , NULL),
1436 SAM3_ENTRY(PMC_FSPR , NULL),
1437 SAM3_ENTRY(PMC_IMR , NULL),
1438 SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
1439 SAM3_ENTRY(PMC_PCK0 , NULL),
1440 SAM3_ENTRY(PMC_PCK1 , NULL),
1441 SAM3_ENTRY(PMC_PCK2 , NULL),
1442 SAM3_ENTRY(PMC_PCSR , NULL),
1443 SAM3_ENTRY(PMC_SCSR , NULL),
1444 SAM3_ENTRY(PMC_SR , NULL),
1445 SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
1446 SAM3_ENTRY(CHIPID_EXID , NULL),
1447 SAM3_ENTRY(SUPC_CR, NULL),
1449 // TERMINATE THE LIST
1457 static struct sam3_bank_private *
1458 get_sam3_bank_private(flash_bank_t *bank)
1460 return (struct sam3_bank_private *)(bank->driver_priv);
1464 * Given a pointer to where it goes in the structure..
1465 * Determine the register name, address from the all registers table.
1467 static const struct sam3_reg_list *
1468 sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
1470 const struct sam3_reg_list *pReg;
1472 pReg = &(sam3_all_regs[0]);
1473 while (pReg->name) {
1474 uint32_t *pPossible;
1476 // calculate where this one go..
1477 // it is "possibly" this register.
1479 pPossible = ((uint32_t *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1481 // well? Is it this register
1482 if (pPossible == goes_here) {
1490 // This is *TOTAL*PANIC* - we are totally screwed.
1491 LOG_ERROR("INVALID SAM3 REGISTER");
1497 sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
1499 const struct sam3_reg_list *pReg;
1502 pReg = sam3_GetReg(pChip, goes_here);
1507 r = target_read_u32(pChip->target, pReg->address, goes_here);
1508 if (r != ERROR_OK) {
1509 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1510 pReg->name, (unsigned)(pReg->address), r);
1518 sam3_ReadAllRegs(struct sam3_chip *pChip)
1521 const struct sam3_reg_list *pReg;
1523 pReg = &(sam3_all_regs[0]);
1524 while (pReg->name) {
1525 r = sam3_ReadThisReg(pChip,
1526 sam3_get_reg_ptr(&(pChip->cfg), pReg));
1527 if (r != ERROR_OK) {
1528 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1529 pReg->name, ((unsigned)(pReg->address)), r);
1541 sam3_GetInfo(struct sam3_chip *pChip)
1543 const struct sam3_reg_list *pReg;
1546 membuf_reset(pChip->mbuf);
1549 pReg = &(sam3_all_regs[0]);
1550 while (pReg->name) {
1552 LOG_DEBUG("Start: %s", pReg->name);
1553 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
1554 sam3_sprintf(pChip, "%*s: [0x%08x] -> 0x%08x\n",
1559 if (pReg->explain_func) {
1560 (*(pReg->explain_func))(pChip);
1562 LOG_DEBUG("End: %s", pReg->name);
1565 sam3_sprintf(pChip," rc-osc: %3.03f MHz\n", _tomhz(pChip->cfg.rc_freq));
1566 sam3_sprintf(pChip," mainosc: %3.03f MHz\n", _tomhz(pChip->cfg.mainosc_freq));
1567 sam3_sprintf(pChip," plla: %3.03f MHz\n", _tomhz(pChip->cfg.plla_freq));
1568 sam3_sprintf(pChip," cpu-freq: %3.03f MHz\n", _tomhz(pChip->cfg.cpu_freq));
1569 sam3_sprintf(pChip,"mclk-freq: %3.03f MHz\n", _tomhz(pChip->cfg.mclk_freq));
1572 sam3_sprintf(pChip, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1573 pChip->cfg.unique_id[0],
1574 pChip->cfg.unique_id[1],
1575 pChip->cfg.unique_id[2],
1576 pChip->cfg.unique_id[3]);
1584 sam3_erase_check(struct flash_bank_s *bank)
1589 if (bank->target->state != TARGET_HALTED) {
1590 LOG_ERROR("Target not halted");
1591 return ERROR_TARGET_NOT_HALTED;
1593 if (0 == bank->num_sectors) {
1594 LOG_ERROR("Target: not supported/not probed\n");
1598 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1599 for (x = 0 ; x < bank->num_sectors ; x++) {
1600 bank->sectors[x].is_erased = 1;
1608 sam3_protect_check(struct flash_bank_s *bank)
1613 struct sam3_bank_private *pPrivate;
1616 if (bank->target->state != TARGET_HALTED) {
1617 LOG_ERROR("Target not halted");
1618 return ERROR_TARGET_NOT_HALTED;
1621 pPrivate = get_sam3_bank_private(bank);
1623 LOG_ERROR("no private for this bank?");
1626 if (!(pPrivate->probed)) {
1627 return ERROR_FLASH_BANK_NOT_PROBED;
1630 r = FLASHD_GetLockBits(pPrivate , &v);
1631 if (r != ERROR_OK) {
1632 LOG_DEBUG("Failed: %d",r);
1636 for (x = 0 ; x < pPrivate->nsectors ; x++) {
1637 bank->sectors[x].is_protected = (!!(v & (1 << x)));
1644 sam3_flash_bank_command(struct command_context_s *cmd_ctx,
1648 struct flash_bank_s *bank)
1650 struct sam3_chip *pChip;
1652 pChip = all_sam3_chips;
1654 // is this an existing chip?
1656 if (pChip->target == bank->target) {
1659 pChip = pChip->next;
1663 // this is a *NEW* chip
1664 pChip = calloc(1, sizeof(struct sam3_chip));
1666 LOG_ERROR("NO RAM!");
1669 pChip->target = bank->target;
1671 pChip->next = all_sam3_chips;
1672 all_sam3_chips = pChip;
1673 pChip->target = bank->target;
1674 // assumption is this runs at 32khz
1675 pChip->cfg.slow_freq = 32768;
1677 pChip->mbuf = membuf_new();
1678 if (!(pChip->mbuf)) {
1679 LOG_ERROR("no memory");
1684 switch (bank->base) {
1686 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1687 ((unsigned int)(bank->base)),
1688 ((unsigned int)(FLASH_BANK0_BASE)),
1689 ((unsigned int)(FLASH_BANK1_BASE)));
1692 case FLASH_BANK0_BASE:
1693 bank->driver_priv = &(pChip->details.bank[0]);
1694 bank->bank_number = 0;
1695 pChip->details.bank[0].pChip = pChip;
1696 pChip->details.bank[0].pBank = bank;
1698 case FLASH_BANK1_BASE:
1699 bank->driver_priv = &(pChip->details.bank[1]);
1700 bank->bank_number = 1;
1701 pChip->details.bank[1].pChip = pChip;
1702 pChip->details.bank[1].pBank = bank;
1706 // we initialize after probing.
1711 sam3_GetDetails(struct sam3_bank_private *pPrivate)
1713 const struct sam3_chip_details *pDetails;
1714 struct sam3_chip *pChip;
1716 flash_bank_t *saved_banks[SAM3_MAX_FLASH_BANKS];
1722 pDetails = all_sam3_details;
1723 while (pDetails->name) {
1724 if (pDetails->chipid_cidr == pPrivate->pChip->cfg.CHIPID_CIDR) {
1730 if (pDetails->name == NULL) {
1731 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1732 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1733 // Help the victim, print details about the chip
1734 membuf_reset(pPrivate->pChip->mbuf);
1735 membuf_sprintf(pPrivate->pChip->mbuf,
1736 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1737 pPrivate->pChip->cfg.CHIPID_CIDR);
1738 sam3_explain_chipid_cidr(pPrivate->pChip);
1739 cp = membuf_strtok(pPrivate->pChip->mbuf, "\n", &vp);
1742 cp = membuf_strtok(NULL, "\n", &vp);
1747 // DANGER: THERE ARE DRAGONS HERE
1749 // get our pChip - it is going
1750 // to be over-written shortly
1751 pChip = pPrivate->pChip;
1753 // Note that, in reality:
1755 // pPrivate = &(pChip->details.bank[0])
1756 // or pPrivate = &(pChip->details.bank[1])
1759 // save the "bank" pointers
1760 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1761 saved_banks[ x ] = pChip->details.bank[x].pBank;
1764 // Overwrite the "details" structure.
1765 memcpy(&(pPrivate->pChip->details),
1767 sizeof(pPrivate->pChip->details));
1769 // now fix the ghosted pointers
1770 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1771 pChip->details.bank[x].pChip = pChip;
1772 pChip->details.bank[x].pBank = saved_banks[x];
1775 // update the *BANK*SIZE*
1784 _sam3_probe(struct flash_bank_s *bank, int noise)
1788 struct sam3_bank_private *pPrivate;
1791 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1792 if (bank->target->state != TARGET_HALTED)
1794 LOG_ERROR("Target not halted");
1795 return ERROR_TARGET_NOT_HALTED;
1798 pPrivate = get_sam3_bank_private(bank);
1800 LOG_ERROR("Invalid/unknown bank number\n");
1804 r = sam3_ReadAllRegs(pPrivate->pChip);
1805 if (r != ERROR_OK) {
1811 r = sam3_GetInfo(pPrivate->pChip);
1812 if (r != ERROR_OK) {
1815 if (!(pPrivate->pChip->probed)) {
1816 pPrivate->pChip->probed = 1;
1818 r = sam3_GetDetails(pPrivate);
1819 if (r != ERROR_OK) {
1824 // update the flash bank size
1825 for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
1826 if (bank->base == pPrivate->pChip->details.bank[0].base_address) {
1827 bank->size = pPrivate->pChip->details.bank[0].size_bytes;
1832 if (bank->sectors == NULL) {
1833 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1834 if (bank->sectors == NULL) {
1835 LOG_ERROR("No memory!");
1838 bank->num_sectors = pPrivate->nsectors;
1840 for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
1841 bank->sectors[x].size = pPrivate->sector_size;
1842 bank->sectors[x].offset = x * (pPrivate->sector_size);
1844 bank->sectors[x].is_erased = -1;
1845 bank->sectors[x].is_protected = -1;
1849 pPrivate->probed = 1;
1851 r = sam3_protect_check(bank);
1852 if (r != ERROR_OK) {
1856 LOG_DEBUG("Bank = %d, nbanks = %d",
1857 pPrivate->bank_number , pPrivate->pChip->details.n_banks);
1858 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1860 // it appears to be associated with the *last* flash bank.
1861 FLASHD_ReadUniqueID(pPrivate);
1868 sam3_probe(struct flash_bank_s *bank)
1870 return _sam3_probe(bank, 1);
1874 sam3_auto_probe(struct flash_bank_s *bank)
1876 return _sam3_probe(bank, 0);
1882 sam3_erase(struct flash_bank_s *bank, int first, int last)
1884 struct sam3_bank_private *pPrivate;
1888 if (bank->target->state != TARGET_HALTED) {
1889 LOG_ERROR("Target not halted");
1890 return ERROR_TARGET_NOT_HALTED;
1893 r = sam3_auto_probe(bank);
1894 if (r != ERROR_OK) {
1895 LOG_DEBUG("Here,r=%d",r);
1899 pPrivate = get_sam3_bank_private(bank);
1900 if (!(pPrivate->probed)) {
1901 return ERROR_FLASH_BANK_NOT_PROBED;
1904 if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
1907 return FLASHD_EraseEntireBank(pPrivate);
1909 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1914 sam3_protect(struct flash_bank_s *bank, int set, int first, int last)
1916 struct sam3_bank_private *pPrivate;
1920 if (bank->target->state != TARGET_HALTED) {
1921 LOG_ERROR("Target not halted");
1922 return ERROR_TARGET_NOT_HALTED;
1925 pPrivate = get_sam3_bank_private(bank);
1926 if (!(pPrivate->probed)) {
1927 return ERROR_FLASH_BANK_NOT_PROBED;
1931 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1933 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1935 LOG_DEBUG("End: r=%d",r);
1943 sam3_info(flash_bank_t *bank, char *buf, int buf_size)
1945 if (bank->target->state != TARGET_HALTED) {
1946 LOG_ERROR("Target not halted");
1947 return ERROR_TARGET_NOT_HALTED;
1954 sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1959 adr = pagenum * pPrivate->page_size;
1960 adr += adr + pPrivate->base_address;
1962 r = target_read_memory(pPrivate->pChip->target,
1964 4, /* THIS*MUST*BE* in 32bit values */
1965 pPrivate->page_size / 4,
1967 if (r != ERROR_OK) {
1968 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
1973 // The code below is basically this:
1975 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1977 // Only the *CPU* can write to the flash buffer.
1978 // the DAP cannot... so - we download this 28byte thing
1979 // Run the algorithm - (below)
1980 // to program the device
1982 // ========================================
1983 // #include <stdint.h>
1987 // const uint32_t *src;
1989 // volatile uint32_t *base;
1994 // uint32_t sam3_function(struct foo *p)
1996 // volatile uint32_t *v;
1998 // const uint32_t *s;
2020 // ========================================
2024 static const uint8_t
2025 sam3_page_write_opcodes[] = {
2026 // 24 0000 0446 mov r4, r0
2028 // 25 0002 6168 ldr r1, [r4, #4]
2030 // 26 0004 0068 ldr r0, [r0, #0]
2032 // 27 0006 A268 ldr r2, [r4, #8]
2034 // 28 @ lr needed for prologue
2036 // 30 0008 51F8043B ldr r3, [r1], #4
2037 0x51,0xf8,0x04,0x3b,
2038 // 31 000c 12F1FF32 adds r2, r2, #-1
2039 0x12,0xf1,0xff,0x32,
2040 // 32 0010 40F8043B str r3, [r0], #4
2041 0x40,0xf8,0x04,0x3b,
2042 // 33 0014 F8D1 bne .L2
2044 // 34 0016 E268 ldr r2, [r4, #12]
2046 // 35 0018 2369 ldr r3, [r4, #16]
2048 // 36 001a 5360 str r3, [r2, #4]
2050 // 37 001c 0832 adds r2, r2, #8
2053 // 39 001e 1068 ldr r0, [r2, #0]
2055 // 40 0020 10F0010F tst r0, #1
2056 0x10,0xf0,0x01,0x0f,
2057 // 41 0024 FBD0 beq .L4
2060 // 43 0026 FEE7 b .done
2066 sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2072 adr = pagenum * pPrivate->page_size;
2073 adr += (adr + pPrivate->base_address);
2075 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2076 r = target_write_memory(pPrivate->pChip->target,
2078 4, /* THIS*MUST*BE* in 32bit values */
2079 pPrivate->page_size / 4,
2081 if (r != ERROR_OK) {
2082 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
2086 r = EFC_PerformCommand(pPrivate,
2087 // send Erase & Write Page
2092 if (r != ERROR_OK) {
2093 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
2095 if (status & (1 << 2)) {
2096 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2099 if (status & (1 << 1)) {
2100 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2111 sam3_write(struct flash_bank_s *bank,
2120 unsigned page_offset;
2121 struct sam3_bank_private *pPrivate;
2122 uint8_t *pagebuffer;
2124 // incase we bail further below, set this to null
2127 // ignore dumb requests
2133 if (bank->target->state != TARGET_HALTED) {
2134 LOG_ERROR("Target not halted");
2135 r = ERROR_TARGET_NOT_HALTED;
2139 pPrivate = get_sam3_bank_private(bank);
2140 if (!(pPrivate->probed)) {
2141 r = ERROR_FLASH_BANK_NOT_PROBED;
2146 if ((offset + count) > pPrivate->size_bytes) {
2147 LOG_ERROR("Flash write error - past end of bank");
2148 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2149 (unsigned int)(offset),
2150 (unsigned int)(count),
2151 (unsigned int)(pPrivate->size_bytes));
2156 pagebuffer = malloc(pPrivate->page_size);
2158 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2163 // what page do we start & end in?
2164 page_cur = offset / pPrivate->page_size;
2165 page_end = (offset + count - 1) / pPrivate->page_size;
2167 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2168 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2170 // Special case: all one page
2173 // (1) non-aligned start
2175 // (3) non-aligned end.
2177 // Handle special case - all one page.
2178 if (page_cur == page_end) {
2179 LOG_DEBUG("Special case, all in one page");
2180 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2181 if (r != ERROR_OK) {
2185 page_offset = (offset & (pPrivate->page_size-1));
2186 memcpy(pagebuffer + page_offset,
2190 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2191 if (r != ERROR_OK) {
2198 // non-aligned start
2199 page_offset = offset & (pPrivate->page_size - 1);
2201 LOG_DEBUG("Not-Aligned start");
2203 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2204 if (r != ERROR_OK) {
2208 // over-write with new data
2209 n = (pPrivate->page_size - page_offset);
2210 memcpy(pagebuffer + page_offset,
2214 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2215 if (r != ERROR_OK) {
2225 // intermediate large pages
2226 // also - the final *terminal*
2227 // if that terminal page is a full page
2228 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2229 (int)page_cur, (int)page_end, (unsigned int)(count));
2231 while ((page_cur < page_end) &&
2232 (count >= pPrivate->page_size)) {
2233 r = sam3_page_write(pPrivate, page_cur, buffer);
2234 if (r != ERROR_OK) {
2237 count -= pPrivate->page_size;
2238 buffer += pPrivate->page_size;
2242 // terminal partial page?
2244 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2245 // we have a partial page
2246 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2247 if (r != ERROR_OK) {
2250 // data goes at start
2251 memcpy(pagebuffer, buffer, count);
2252 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2253 if (r != ERROR_OK) {
2269 sam3_handle_info_command(struct command_context_s *cmd_ctx, char *cmd, char **argv, int argc)
2271 struct sam3_chip *pChip;
2277 pChip = get_current_sam3(cmd_ctx);
2284 // bank0 must exist before we can do anything
2285 if (pChip->details.bank[0].pBank == NULL) {
2288 command_print(cmd_ctx,
2289 "Please define bank %d via command: flash bank %s ... ",
2291 at91sam3_flash.name);
2295 // if bank 0 is not probed, then probe it
2296 if (!(pChip->details.bank[0].probed)) {
2297 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2298 if (r != ERROR_OK) {
2302 // above garentees the "chip details" structure is valid
2303 // and thus, bank private areas are valid
2304 // and we have a SAM3 chip, what a concept!
2307 // auto-probe other banks, 0 done above
2308 for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
2309 // skip banks not present
2310 if (!(pChip->details.bank[x].present)) {
2314 if (pChip->details.bank[x].pBank == NULL) {
2318 if (pChip->details.bank[x].probed) {
2322 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2323 if (r != ERROR_OK) {
2329 r = sam3_GetInfo(pChip);
2330 if (r != ERROR_OK) {
2331 LOG_DEBUG("Sam3Info, Failed %d\n",r);
2337 cp = membuf_strtok(pChip->mbuf, "\n", &vp);
2339 command_print(cmd_ctx,"%s", cp);
2340 cp = membuf_strtok(NULL, "\n", &vp);
2346 sam3_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **argv, int argc)
2351 struct sam3_chip *pChip;
2353 pChip = get_current_sam3(cmd_ctx);
2358 if (pChip->target->state != TARGET_HALTED) {
2359 LOG_ERROR("sam3 - target not halted");
2360 return ERROR_TARGET_NOT_HALTED;
2364 if (pChip->details.bank[0].pBank == NULL) {
2365 command_print(cmd_ctx, "Bank0 must be defined first via: flash bank %s ...",
2366 at91sam3_flash.name);
2369 if (!pChip->details.bank[0].probed) {
2370 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2371 if (r != ERROR_OK) {
2379 command_print(cmd_ctx,"Too many parameters\n");
2380 return ERROR_COMMAND_SYNTAX_ERROR;
2390 if ((0 == strcmp(argv[0], "show")) && (0 == strcmp(argv[1], "all"))) {
2393 r = parse_u32(argv[1], &v32);
2394 if (r != ERROR_OK) {
2395 command_print(cmd_ctx, "Not a number: %s", argv[1]);
2403 if (0 == strcmp("show", argv[0])) {
2407 for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
2408 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2409 if (r != ERROR_OK) {
2412 command_print(cmd_ctx, "sam3-gpnvm%u: %u", x, v);
2416 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2417 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2418 command_print(cmd_ctx, "sam3-gpnvm%u: %u", who, v);
2421 command_print(cmd_ctx, "sam3-gpnvm invalid GPNVM: %u", who);
2422 return ERROR_COMMAND_SYNTAX_ERROR;
2427 command_print(cmd_ctx, "Missing GPNVM number");
2428 return ERROR_COMMAND_SYNTAX_ERROR;
2431 if (0 == strcmp("set", argv[0])) {
2432 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2433 } else if ((0 == strcmp("clr", argv[0])) ||
2434 (0 == strcmp("clear", argv[0]))) { // quietly accept both
2435 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2437 command_print(cmd_ctx, "Unkown command: %s", argv[0]);
2438 r = ERROR_COMMAND_SYNTAX_ERROR;
2444 sam3_handle_slowclk_command(struct command_context_s *cmd_ctx, char *cmd, char **argv, int argc)
2449 struct sam3_chip *pChip;
2451 pChip = get_current_sam3(cmd_ctx);
2463 r = parse_u32(argv[0], &v);
2465 // absurd slow clock of 200Khz?
2466 command_print(cmd_ctx,"Absurd/illegal slow clock freq: %d\n", (int)(v));
2467 return ERROR_COMMAND_SYNTAX_ERROR;
2469 pChip->cfg.slow_freq = v;
2474 command_print(cmd_ctx,"Too many parameters");
2475 return ERROR_COMMAND_SYNTAX_ERROR;
2478 command_print(cmd_ctx, "Slowclk freq: %d.%03dkhz",
2479 (int)(pChip->cfg.slow_freq/ 1000),
2480 (int)(pChip->cfg.slow_freq% 1000));
2485 static int sam3_registered;
2487 sam3_register_commands(struct command_context_s *cmd_ctx)
2491 // only register once
2492 if (!sam3_registered) {
2495 pCmd = register_command(cmd_ctx, NULL, "at91sam3", NULL, COMMAND_ANY, NULL);
2496 register_command(cmd_ctx, pCmd,
2498 sam3_handle_gpnvm_command,
2500 "at91sam3 gpnvm [action [<BIT>], by default 'show', otherwise set | clear BIT");
2501 register_command(cmd_ctx, pCmd,
2503 sam3_handle_info_command,
2505 "at91sam3 info - print information about the current sam3 chip");
2506 register_command(cmd_ctx, pCmd,
2508 sam3_handle_slowclk_command,
2510 "at91sam3 slowclk [VALUE] set the slowclock frequency (default 32768hz)");
2516 flash_driver_t at91sam3_flash =
2519 .register_commands = sam3_register_commands,
2521 .flash_bank_command = sam3_flash_bank_command,
2522 .erase = sam3_erase,
2523 .protect = sam3_protect,
2524 .write = sam3_write,
2525 .probe = sam3_probe,
2526 .auto_probe = sam3_auto_probe,
2527 .erase_check = sam3_erase_check,
2528 .protect_check = sam3_protect_check,
2535 * Local Variables: **
2537 * c-basic-offset: 4 **