2 * Copyright © 2016 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
18 /* VGA output from the SPI port
28 * pixel clock PA8 -> PB3
29 * pixel enable PA1 -> PA15
32 /* GRF formula for 640x480 yields a pixel clock very close to 24MHz. Pad by
33 * three scanlines to hit exactly that value
37 #define HSYNC_START (656)
38 #define HSYNC_END (720)
42 #define VSYNC_START 481
47 * The horizontal counter is set so that the end of hsync is reached
48 * at the maximum counter value. That means that the hblank interval
49 * is offset by HSYNC_END.
52 #define HSYNC (HSYNC_END - HSYNC_START)
53 #define HBLANK_END (HTOTAL - HSYNC_END)
54 #define HBLANK_START (HBLANK_END + HACTIVE)
57 * The vertical counter is set so that the end of vsync is reached at
58 * the maximum counter value. That means that the vblank interval is
59 * offset by VSYNC_END. We send a blank line at the start of the
60 * frame, so each of these is off by one
62 #define VSYNC (VSYNC_END - VSYNC_START)
63 #define VBLANK_END (VTOTAL - VSYNC_END)
64 #define VBLANK_START (VBLANK_END + VACTIVE)
66 #define WIDTH_BYTES (AO_VGA_WIDTH >> 3)
67 #define SCANOUT ((WIDTH_BYTES+2) >> 1)
69 uint32_t ao_vga_fb[AO_VGA_STRIDE * AO_VGA_HEIGHT];
71 const struct ao_bitmap ao_vga_bitmap = {
73 .stride = AO_VGA_STRIDE,
74 .width = AO_VGA_WIDTH,
75 .height = AO_VGA_HEIGHT
78 static uint32_t *scanline;
80 #define DMA_INDEX STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX)
82 #define DMA_CCR(en) ((0 << STM_DMA_CCR_MEM2MEM) | \
83 (STM_DMA_CCR_PL_VERY_HIGH << STM_DMA_CCR_PL) | \
84 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) | \
85 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) | \
86 (1 << STM_DMA_CCR_MINC) | \
87 (0 << STM_DMA_CCR_PINC) | \
88 (0 << STM_DMA_CCR_CIRC) | \
89 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) | \
90 (0 << STM_DMA_CCR_TCIE) | \
91 (en << STM_DMA_CCR_EN))
94 void stm_tim2_isr(void)
96 int16_t line = stm_tim3.cnt;
98 if (VBLANK_END <= line && line < VBLANK_START) {
100 stm_dma.channel[DMA_INDEX].ccr = DMA_CCR(0);
101 /* Reset DMA engine for the next scanline */
102 stm_dma.channel[DMA_INDEX].cmar = scanline;
103 stm_dma.channel[DMA_INDEX].cndtr = SCANOUT;
110 stm_dma.channel[DMA_INDEX].ccr = DMA_CCR(1);
111 if (((line - VBLANK_END) & 1))
112 scanline += AO_VGA_STRIDE;
114 scanline = ao_vga_fb;
125 /* Initialize spi1 using MISO PB4 for output */
126 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
127 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
129 stm_ospeedr_set(&stm_gpiob, 4, STM_OSPEEDR_40MHz);
130 stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
131 stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
132 stm_afr_set(&stm_gpioa, 15, STM_AFR_AF5);
135 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
137 stm_spi1.cr1 = ((1 << STM_SPI_CR1_BIDIMODE) | /* Two wire mode */
138 (1 << STM_SPI_CR1_BIDIOE) |
139 (0 << STM_SPI_CR1_CRCEN) | /* CRC disabled */
140 (0 << STM_SPI_CR1_CRCNEXT) |
141 (1 << STM_SPI_CR1_DFF) |
142 (0 << STM_SPI_CR1_RXONLY) | /* transmit, not receive */
143 (0 << STM_SPI_CR1_SSM) | /* Software SS handling */
144 (1 << STM_SPI_CR1_SSI) | /* ... */
145 (1 << STM_SPI_CR1_LSBFIRST) | /* Little endian */
146 (1 << STM_SPI_CR1_SPE) | /* Enable SPI unit */
147 (0 << STM_SPI_CR1_BR) | /* baud rate to pclk/2 */
148 (0 << STM_SPI_CR1_MSTR) | /* slave */
149 (0 << STM_SPI_CR1_CPOL) | /* Format 0 */
150 (0 << STM_SPI_CR1_CPHA));
151 stm_spi1.cr2 = ((0 << STM_SPI_CR2_TXEIE) |
152 (0 << STM_SPI_CR2_RXNEIE) |
153 (0 << STM_SPI_CR2_ERRIE) |
154 (0 << STM_SPI_CR2_SSOE) |
155 (1 << STM_SPI_CR2_TXDMAEN) |
156 (0 << STM_SPI_CR2_RXDMAEN));
161 /* Grab the DMA channel for SPI1 MOSI */
162 stm_dma.channel[DMA_INDEX].cpar = &stm_spi1.dr;
163 stm_dma.channel[DMA_INDEX].cmar = ao_vga_fb;
166 * Hsync Configuration
168 /* Turn on timer 2 */
169 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM2EN);
171 /* tim2 runs at full speed */
174 /* Disable channels while modifying */
177 /* Channel 1 hsync PWM values */
178 stm_tim2.ccr1 = HSYNC;
180 /* Channel 2 trigger scanout */
181 /* wait for the time to start scanout */
182 stm_tim2.ccr2 = HBLANK_END;
186 /* Configure channel 1 to output on the pin and
187 * channel 2 to to set the trigger for the vsync timer
189 stm_tim2.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
190 (STM_TIM234_CCMR1_OC2M_PWM_MODE_1 << STM_TIM234_CCMR1_OC2M) |
191 (1 << STM_TIM234_CCMR1_OC2PE) |
192 (0 << STM_TIM234_CCMR1_OC2FE) |
193 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
195 (0 << STM_TIM234_CCMR1_OC1CE) |
196 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
197 (1 << STM_TIM234_CCMR1_OC1PE) |
198 (0 << STM_TIM234_CCMR1_OC1FE) |
199 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
201 stm_tim2.ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
202 (0 << STM_TIM234_CCMR2_OC4M) |
203 (0 << STM_TIM234_CCMR2_OC4PE) |
204 (0 << STM_TIM234_CCMR2_OC4FE) |
205 (0 << STM_TIM234_CCMR2_CC4S) |
207 (0 << STM_TIM234_CCMR2_OC3CE) |
208 (STM_TIM234_CCMR2_OC3M_PWM_MODE_1 << STM_TIM234_CCMR2_OC3M) |
209 (1 << STM_TIM234_CCMR2_OC3PE) |
210 (0 << STM_TIM234_CCMR2_OC3FE) |
211 (0 << STM_TIM234_CCMR2_CC3S));
214 stm_tim2.arr = HTOTAL;
218 /* Update the register contents */
219 stm_tim2.egr |= (1 << STM_TIM234_EGR_UG);
221 /* Enable the timer */
223 /* Enable the output */
224 stm_tim2.ccer = ((0 << STM_TIM234_CCER_CC2NP) |
225 (STM_TIM234_CCER_CC2P_ACTIVE_HIGH << STM_TIM234_CCER_CC2P) |
226 (1 << STM_TIM234_CCER_CC2E) |
227 (0 << STM_TIM234_CCER_CC1NP) |
228 (STM_TIM234_CCER_CC1P_ACTIVE_LOW << STM_TIM234_CCER_CC1P) |
229 (1 << STM_TIM234_CCER_CC1E));
231 stm_tim2.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
232 (STM_TIM234_CR2_MMS_UPDATE << STM_TIM234_CR2_MMS) |
233 (0 << STM_TIM234_CR2_CCDS));
235 /* hsync is not a slave timer */
238 /* Send an interrupt on channel 3 */
239 stm_tim2.dier = ((1 << STM_TIM234_DIER_CC3IE));
241 stm_tim2.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
242 (1 << STM_TIM234_CR1_ARPE) |
243 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
244 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
245 (0 << STM_TIM234_CR1_OPM) |
246 (1 << STM_TIM234_CR1_URS) |
247 (0 << STM_TIM234_CR1_UDIS) |
248 (0 << STM_TIM234_CR1_CEN));
250 /* Hsync is on PA5 which is Timer 2 CH1 output */
251 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
252 stm_ospeedr_set(&stm_gpioa, 5, STM_OSPEEDR_40MHz);
253 stm_afr_set(&stm_gpioa, 5, STM_AFR_AF1);
255 /* pixel transmit enable is on PA1 */
256 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
257 stm_ospeedr_set(&stm_gpioa, 1, STM_OSPEEDR_40MHz);
258 stm_afr_set(&stm_gpioa, 1, STM_AFR_AF1);
261 * Vsync configuration
264 /* Turn on timer 3, slaved to timer 1 using ITR1 (table 61) */
265 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM3EN);
270 /* Channel 1 or 2 vsync PWM values */
271 stm_tim3.ccr1 = VSYNC;
272 stm_tim3.ccr2 = VSYNC;
274 stm_tim3.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
275 (STM_TIM234_CCMR1_OC2M_PWM_MODE_1 << STM_TIM234_CCMR1_OC2M) |
276 (1 << STM_TIM234_CCMR1_OC2PE) |
277 (0 << STM_TIM234_CCMR1_OC2FE) |
278 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
280 (0 << STM_TIM234_CCMR1_OC1CE) |
281 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
282 (1 << STM_TIM234_CCMR1_OC1PE) |
283 (0 << STM_TIM234_CCMR1_OC1FE) |
284 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
286 stm_tim3.arr = VTOTAL;
289 /* Update the register contents */
290 stm_tim3.egr |= (1 << STM_TIM234_EGR_UG);
292 /* Enable the timer */
294 /* Enable the output */
295 stm_tim3.ccer = ((0 << STM_TIM234_CCER_CC1NP) |
296 (STM_TIM234_CCER_CC2P_ACTIVE_LOW << STM_TIM234_CCER_CC2P) |
297 (1 << STM_TIM234_CCER_CC2E) |
298 (STM_TIM234_CCER_CC1P_ACTIVE_LOW << STM_TIM234_CCER_CC1P) |
299 (1 << STM_TIM234_CCER_CC1E));
301 stm_tim3.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
302 (STM_TIM234_CR2_MMS_UPDATE << STM_TIM234_CR2_MMS) |
303 (0 << STM_TIM234_CR2_CCDS));
306 stm_tim3.smcr = ((0 << STM_TIM234_SMCR_ETP) |
307 (0 << STM_TIM234_SMCR_ECE) |
308 (STM_TIM234_SMCR_ETPS_OFF << STM_TIM234_SMCR_ETPS) |
309 (STM_TIM234_SMCR_ETF_NONE << STM_TIM234_SMCR_ETF) |
310 (0 << STM_TIM234_SMCR_MSM) |
311 (STM_TIM234_SMCR_TS_ITR1 << STM_TIM234_SMCR_TS) |
312 (0 << STM_TIM234_SMCR_OCCS) |
313 (STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK << STM_TIM234_SMCR_SMS));
317 stm_tim3.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
318 (1 << STM_TIM234_CR1_ARPE) |
319 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
320 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
321 (0 << STM_TIM234_CR1_OPM) |
322 (1 << STM_TIM234_CR1_URS) |
323 (0 << STM_TIM234_CR1_UDIS) |
324 (1 << STM_TIM234_CR1_CEN));
326 /* Vsync is on PB5 which is is Timer 3 CH2 output */
327 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
328 stm_ospeedr_set(&stm_gpiob, 5, STM_OSPEEDR_40MHz);
329 stm_afr_set(&stm_gpiob, 5, STM_AFR_AF2);
331 /* Use MCO for the pixel clock, that appears on PA8 */
332 cfgr = stm_rcc.cfgr & ~((STM_RCC_CFGR_MCOPRE_MASK << STM_RCC_CFGR_MCOPRE) |
333 (STM_RCC_CFGR_MCOSEL_MASK << STM_RCC_CFGR_MCOSEL));
335 cfgr |= ((STM_RCC_CFGR_MCOPRE_DIV_2 << STM_RCC_CFGR_MCOPRE) |
336 (STM_RCC_CFGR_MCOSEL_SYSCLK << STM_RCC_CFGR_MCOSEL));
340 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
341 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
343 /* Enable the scanline interrupt */
344 stm_nvic_set_priority(STM_ISR_TIM2_POS, AO_STM_NVIC_NONMASK_PRIORITY);
345 stm_nvic_set_enable(STM_ISR_TIM2_POS);
351 ao_vga_enable(int enable)
355 ++ao_task_minimize_latency;
358 stm_tim2.cr1 |= (1 << STM_TIM234_CR1_CEN);
361 --ao_task_minimize_latency;
364 stm_tim2.cr1 &= ~(1 << STM_TIM234_CR1_CEN);