2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 static volatile __data uint16_t ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
40 #define T1_CLOCK_DIVISOR 8 /* 24e6/8 = 3e6 */
41 #define T1_SAMPLE_TIME 30000 /* 3e6/30000 = 100 */
44 volatile __data uint8_t ao_adc_interval = 1;
45 volatile __data uint8_t ao_adc_count;
51 ISR(TIMER1_COMPA_vect)
55 if (++ao_adc_count == ao_adc_interval) {
64 ao_timer_set_adc_interval(uint8_t interval) __critical
66 ao_adc_interval = interval;
74 TCCR1A = ((0 << WGM11) | /* CTC mode, OCR1A */
75 (0 << WGM10)); /* CTC mode, OCR1A */
76 TCCR1B = ((0 << ICNC1) | /* no input capture noise canceler */
77 (0 << ICES1) | /* input capture on falling edge (don't care) */
78 (0 << WGM13) | /* CTC mode, OCR1A */
79 (1 << WGM12) | /* CTC mode, OCR1A */
80 (3 << CS10)); /* clk/64 from prescaler */
83 OCR1A = 2500; /* 16MHz clock */
85 OCR1A = 1250; /* 8MHz clock */
88 TIMSK1 = (1 << OCIE1A); /* Interrupt on compare match */
92 * AltOS always cranks the clock to the max frequency
97 /* disable RC clock */
98 CLKSEL0 &= ~(1 << RCE);
101 PLLCSR &= ~(1 << PLLE);
103 /* Enable external clock */
104 CLKSEL0 |= (1 << EXTE);
106 /* wait for external clock to be ready */
107 while ((CLKSTA & (1 << EXTON)) == 0)
110 /* select external clock */
111 CLKSEL0 |= (1 << CLKS);
113 /* Disable the clock prescaler */
115 CLKPR = (1 << CLKPCE);
117 /* Always run the system clock at 8MHz */
118 #if AVR_CLOCK > 12000000UL
125 /* Set up the PLL to use the crystal */
127 /* Use primary system clock as PLL source */
128 PLLFRQ = ((0 << PINMUX) | /* Use primary clock */
129 (0 << PLLUSB) | /* No divide by 2 for USB */
130 (0 << PLLTM0) | /* Disable high speed timer */
131 (0x4 << PDIV0)); /* 48MHz PLL clock */
133 /* Set the frequency of the crystal */
134 #if AVR_CLOCK > 12000000UL
135 PLLCSR |= (1 << PINDIV); /* For 16MHz crystal on Teensy board */
137 PLLCSR &= ~(1 << PINDIV); /* For 8MHz crystal on TeleScience board */
141 PLLCSR |= (1 << PLLE);
142 while (!(PLLCSR & (1 << PLOCK)))
145 set_sleep_mode(SLEEP_MODE_IDLE);