2 * Simulator of microcontrollers (z80.cc)
4 * some z80 code base from Karl Bongers karl@turbobit.com
6 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
8 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
12 /* This file is part of microcontroller simulator: ucsim.
14 UCSIM is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 UCSIM is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with UCSIM; see the file COPYING. If not, write to the Free
26 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
32 #include <stdarg.h> /* for va_list */
50 #define uint8 unsigned char
52 /*******************************************************************/
56 * Base type of Z80 controllers
59 cl_z80::cl_z80(class cl_sim *asim):
68 cl_uc::init(); /* Memories now exist */
70 rom= address_space(MEM_ROM_ID);
71 // ram= mem(MEM_XRAM);
74 // zero out ram(this is assumed in regression tests)
75 for (int i=0x8000; i<0x10000; i++) {
76 ram->set((t_addr) i, 0);
83 cl_z80::id_string(void)
85 return("unspecified Z80");
90 * Making elements of the controller
94 cl_z80::get_mem_size(enum mem_class type)
98 case MEM_ROM: return(0x10000);
99 case MEM_XRAM: return(0x10000);
102 return(cl_uc::get_mem_size(type));
107 cl_z80::mk_hw_elements(void)
110 /* t_uc::mk_hw() does nothing */
114 cl_z80::make_memories(void)
116 class cl_address_space *as;
118 as= new cl_address_space("rom", 0, 0x10000, 8);
120 address_spaces->add(as);
122 class cl_address_decoder *ad;
123 class cl_memory_chip *chip;
125 chip= new cl_memory_chip("rom_chip", 0x10000, 8);
128 ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
130 as->decoders->add(ad);
136 * Help command interpreter
140 cl_z80::dis_tbl(void)
145 /*struct name_entry *
146 cl_z80::sfr_tbl(void)
151 /*struct name_entry *
152 cl_z80::bit_tbl(void)
159 cl_z80::inst_length(t_addr addr)
164 s = get_disasm_info(addr, &len, NULL, NULL);
170 cl_z80::inst_branch(t_addr addr)
175 s = get_disasm_info(addr, NULL, &b, NULL);
181 cl_z80::longest_inst(void)
188 cl_z80::get_disasm_info(t_addr addr,
198 int start_addr = addr;
199 struct dis_entry *dis_e;
201 code= get_mem(MEM_ROM_ID, addr++);
205 case 0xcb: /* ESC code to lots of op-codes, all 2-byte */
206 code= get_mem(MEM_ROM_ID, addr++);
208 while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code &&
209 disass_z80_cb[i].mnemonic)
211 dis_e = &disass_z80_cb[i];
212 b= disass_z80_cb[i].mnemonic;
214 len += (disass_z80_cb[i].length + 1);
217 case 0xed: /* ESC code to about 80 opcodes of various lengths */
218 code= get_mem(MEM_ROM_ID, addr++);
220 while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code &&
221 disass_z80_ed[i].mnemonic)
223 dis_e = &disass_z80_ed[i];
224 b= disass_z80_ed[i].mnemonic;
226 len += (disass_z80_ed[i].length + 1);
229 case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */
230 code= get_mem(MEM_ROM_ID, addr++);
233 addr++; // pass up immed data
234 code= get_mem(MEM_ROM_ID, addr++);
236 while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code &&
237 disass_z80_ddcb[i].mnemonic)
239 dis_e = &disass_z80_ddcb[i];
240 b= disass_z80_ddcb[i].mnemonic;
242 len += (disass_z80_ddcb[i].length + 2);
245 while ((code & disass_z80_dd[i].mask) != disass_z80_dd[i].code &&
246 disass_z80_dd[i].mnemonic)
248 dis_e = &disass_z80_dd[i];
249 b= disass_z80_dd[i].mnemonic;
251 len += (disass_z80_dd[i].length + 1);
255 case 0xfd: /* ESC codes,sme as dd but IY centric */
256 code= get_mem(MEM_ROM_ID, addr++);
259 addr++; // pass up immed data
260 code= get_mem(MEM_ROM_ID, addr++);
262 while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code &&
263 disass_z80_fdcb[i].mnemonic)
265 dis_e = &disass_z80_fdcb[i];
266 b= disass_z80_fdcb[i].mnemonic;
268 len += (disass_z80_fdcb[i].length + 2);
271 while ((code & disass_z80_fd[i].mask) != disass_z80_fd[i].code &&
272 disass_z80_fd[i].mnemonic)
274 dis_e = &disass_z80_fd[i];
275 b= disass_z80_fd[i].mnemonic;
277 len += (disass_z80_fd[i].length + 1);
283 while ((code & disass_z80[i].mask) != disass_z80[i].code &&
284 disass_z80[i].mnemonic)
286 dis_e = &disass_z80[i];
287 b= disass_z80[i].mnemonic;
289 len += (disass_z80[i].length);
295 *ret_branch = dis_e->branch;
300 *immed_offset = immed_n;
301 else *immed_offset = (addr - start_addr);
314 cl_z80::disass(t_addr addr, char *sep)
316 char work[256], temp[20];
317 char *buf, *p, *b, *t;
319 int immed_offset = 0;
323 b = get_disasm_info(addr, &len, NULL, &immed_offset);
326 buf= (char*)malloc(30);
327 strcpy(buf, "UNKNOWN/INVALID");
338 case 'd': // d jump relative target, signed? byte immediate operand
339 sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset));
342 case 'w': // w word immediate operand
343 sprintf(temp, "#0x%04x",
344 (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) |
345 (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) );
349 case 'b': // b byte immediate operand
350 sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset));
366 p= strchr(work, ' ');
373 buf= (char *)malloc(6+strlen(p)+1);
375 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
376 for (p= work, b= buf; *p != ' '; p++, b++)
382 while (strlen(buf) < 6)
393 cl_z80::print_regs(class cl_console_base *con)
395 con->dd_printf("SZ-A--P-C Flags= 0x%02x %3d %c ",
396 regs.F, regs.F, isprint(regs.F)?regs.F:'.');
397 con->dd_printf("A= 0x%02x %3d %c\n",
398 regs.A, regs.A, isprint(regs.A)?regs.A:'.');
399 con->dd_printf("%c%c-%c--%c-%c\n",
400 (regs.F&BIT_S)?'1':'0',
401 (regs.F&BIT_Z)?'1':'0',
402 (regs.F&BIT_A)?'1':'0',
403 (regs.F&BIT_P)?'1':'0',
404 (regs.F&BIT_C)?'1':'0');
405 con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
406 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
407 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
408 con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
409 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
410 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
411 con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
412 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
413 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
414 con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ",
415 regs.IX, ram->get(regs.IX), ram->get(regs.IX),
416 isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
417 con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ",
418 regs.IY, ram->get(regs.IY), ram->get(regs.IY),
419 isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
420 con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
421 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
422 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
424 print_disass(PC, con);
432 cl_z80::exec_inst(void)
437 return(resBREAKPOINT);
441 case 0x00: return(inst_nop(code));
442 case 0x01: case 0x02: case 0x06: return(inst_ld(code));
443 case 0x03: case 0x04: return(inst_inc(code));
444 case 0x05: return(inst_dec(code));
445 case 0x07: return(inst_rlca(code));
447 case 0x08: return(inst_ex(code));
448 case 0x09: return(inst_add(code));
449 case 0x0a: case 0x0e: return(inst_ld(code));
450 case 0x0b: case 0x0d: return(inst_dec(code));
451 case 0x0c: return(inst_inc(code));
452 case 0x0f: return(inst_rrca(code));
455 case 0x10: return(inst_djnz(code));
456 case 0x11: case 0x12: case 0x16: return(inst_ld(code));
457 case 0x13: case 0x14: return(inst_inc(code));
458 case 0x15: return(inst_dec(code));
459 case 0x17: return(inst_rla(code));
461 case 0x18: return(inst_jr(code));
462 case 0x19: return(inst_add(code));
463 case 0x1a: case 0x1e: return(inst_ld(code));
464 case 0x1b: case 0x1d: return(inst_dec(code));
465 case 0x1c: return(inst_inc(code));
466 case 0x1f: return(inst_rra(code));
469 case 0x20: return(inst_jr(code));
470 case 0x21: case 0x22: case 0x26: return(inst_ld(code));
471 case 0x23: case 0x24: return(inst_inc(code));
472 case 0x25: return(inst_dec(code));
473 case 0x27: return(inst_daa(code));
475 case 0x28: return(inst_jr(code));
476 case 0x29: return(inst_add(code));
477 case 0x2a: case 0x2e: return(inst_ld(code));
478 case 0x2b: case 0x2d: return(inst_dec(code));
479 case 0x2c: return(inst_inc(code));
480 case 0x2f: return(inst_cpl(code));
483 case 0x30: return(inst_jr(code));
484 case 0x31: case 0x32: case 0x36: return(inst_ld(code));
485 case 0x33: case 0x34: return(inst_inc(code));
486 case 0x35: return(inst_dec(code));
487 case 0x37: return(inst_scf(code));
489 case 0x38: return(inst_jr(code));
490 case 0x39: return(inst_add(code));
491 case 0x3a: case 0x3e: return(inst_ld(code));
492 case 0x3b: case 0x3d: return(inst_dec(code));
493 case 0x3c: return(inst_inc(code));
494 case 0x3f: return(inst_ccf(code));
496 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
497 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
498 return(inst_ld(code));
500 case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
501 case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
502 return(inst_ld(code));
504 case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
505 case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
506 return(inst_ld(code));
508 case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
509 case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
510 return(inst_ld(code));
512 return(inst_halt(code));
514 case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
515 return(inst_add(code));
516 case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
517 return(inst_adc(code));
519 case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
520 return(inst_sub(code));
521 case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
522 return(inst_sbc(code));
524 case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
525 return(inst_and(code));
526 case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
527 return(inst_xor(code));
529 case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
530 return(inst_or(code));
531 case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
532 return(inst_cp(code));
534 case 0xc0: return(inst_ret(code));
535 case 0xc1: return(inst_pop(code));
536 case 0xc2: case 0xc3: return(inst_jp(code));
537 case 0xc4: return(inst_call(code));
538 case 0xc5: return(inst_push(code));
539 case 0xc6: return(inst_add(code));
540 case 0xc7: return(inst_rst(code));
542 case 0xc8: case 0xc9: return(inst_ret(code));
543 case 0xca: return(inst_jp(code));
545 /* CB escapes out to 2 byte opcodes(CB include), opcodes
546 to do register bit manipulations */
547 case 0xcb: return(inst_cb());
548 case 0xcc: case 0xcd: return(inst_call(code));
549 case 0xce: return(inst_adc(code));
550 case 0xcf: return(inst_rst(code));
553 case 0xd0: return(inst_ret(code));
554 case 0xd1: return(inst_pop(code));
555 case 0xd2: return(inst_jp(code));
556 case 0xd3: return(inst_out(code));
557 case 0xd4: return(inst_call(code));
558 case 0xd5: return(inst_push(code));
559 case 0xd6: return(inst_sub(code));
560 case 0xd7: return(inst_rst(code));
562 case 0xd8: return(inst_ret(code));
563 case 0xd9: return(inst_exx(code));
564 case 0xda: return(inst_jp(code));
565 case 0xdb: return(inst_in(code));
566 case 0xdc: return(inst_call(code));
567 /* DD escapes out to 2 to 4 byte opcodes(DD included)
568 with a variety of uses. It can precede the CB escape
569 sequence to extend CB codes with IX+immed_byte */
570 case 0xdd: return(inst_dd());
571 case 0xde: return(inst_sbc(code));
572 case 0xdf: return(inst_rst(code));
575 case 0xe0: return(inst_ret(code));
576 case 0xe1: return(inst_pop(code));
577 case 0xe2: return(inst_jp(code));
578 case 0xe3: return(inst_ex(code));
579 case 0xe4: return(inst_call(code));
580 case 0xe5: return(inst_push(code));
581 case 0xe6: return(inst_and(code));
582 case 0xe7: return(inst_rst(code));
584 case 0xe8: return(inst_ret(code));
585 case 0xe9: return(inst_jp(code));
586 case 0xea: return(inst_jp(code));
587 case 0xeb: return(inst_ex(code));
588 case 0xec: return(inst_call(code));
589 /* ED escapes out to misc IN, OUT and other oddball opcodes */
590 case 0xed: return(inst_ed());
591 case 0xee: return(inst_xor(code));
592 case 0xef: return(inst_rst(code));
595 case 0xf0: return(inst_ret(code));
596 case 0xf1: return(inst_pop(code));
597 case 0xf2: return(inst_jp(code));
598 case 0xf3: return(inst_di(code));
599 case 0xf4: return(inst_call(code));
600 case 0xf5: return(inst_push(code));
601 case 0xf6: return(inst_or(code));
602 case 0xf7: return(inst_rst(code));
604 case 0xf8: return(inst_ret(code));
605 case 0xf9: return(inst_ld(code));
606 case 0xfa: return(inst_jp(code));
607 case 0xfb: return(inst_ei(code));
608 case 0xfc: return(inst_call(code));
609 /* DD escapes out to 2 to 4 byte opcodes(DD included)
610 with a variety of uses. It can precede the CB escape
611 sequence to extend CB codes with IX+immed_byte */
612 case 0xfd: return(inst_fd());
613 case 0xfe: return(inst_cp(code));
614 case 0xff: return(inst_rst(code));
620 PC= get_mem_size(MEM_ROM_ID)-1;*/
621 PC= rom->inc_address(PC, -1);
623 sim->stop(resINV_INST);
628 /* End of z80.src/z80.cc */