2 * Simulator of microcontrollers (z80.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
48 * Base type of Z80 controllers
51 cl_z80::cl_z80(class cl_sim *asim):
60 cl_uc::init(); /* Memories now exist */
67 cl_z80::id_string(void)
69 return("unspecified Z80");
74 * Making elements of the controller
78 cl_z80::get_mem_size(enum mem_class type)
82 case MEM_ROM: return(0x10000);
83 case MEM_XRAM: return(0x10000);
86 return(cl_uc::get_mem_size(type));
90 cl_z80::mk_hw_elements(void)
93 /* t_uc::mk_hw() does nothing */
98 * Help command interpreter
102 cl_z80::dis_tbl(void)
107 /*struct name_entry *
108 cl_z80::sfr_tbl(void)
113 /*struct name_entry *
114 cl_z80::bit_tbl(void)
121 cl_z80::disass(t_addr addr, char *sep)
123 char work[256], temp[20];
124 char *buf, *p, *b, *t;
130 code= get_mem(MEM_ROM, addr);
132 while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code &&
133 dis_tbl()[i].mnemonic)
135 if (dis_tbl()[i].mnemonic == NULL)
137 buf= (char*)malloc(30);
138 strcpy(buf, "UNKNOWN/INVALID");
141 b= dis_tbl()[i].mnemonic;
150 case 'd': // Rd .... ...d dddd .... 0<=d<=31
151 if (!get_name(data= (code&0x01f0)>>4, sfr_tbl(), temp))
152 sprintf(temp, "r%d", data);
154 case 'D': // Rd .... .... dddd .... 16<=d<=31
155 if (!get_name(data= 16+((code&0xf0)>>4), sfr_tbl(), temp))
156 sprintf(temp, "r%d", data);
158 case 'K': // K .... KKKK .... KKKK 0<=K<=255
159 sprintf(temp, "%d", ((code&0xf00)>>4)|(code&0xf));
161 case 'r': // Rr .... ..r. .... rrrr 0<=r<=31
162 if (!get_name(data= ((code&0x0200)>>5)|(code&0x000f),
164 sprintf(temp, "r%d", data);
166 case '2': // Rdl .... .... ..dd .... dl= {24,26,28,30}
167 if (!get_name(data= 24+(2*((code&0x0030)>>4)),
169 sprintf(temp, "r%d", data);
171 case '6': // K .... .... KK.. KKKK 0<=K<=63
172 sprintf(temp, "%d", ((code&0xc0)>>2)|(code&0xf));
174 case 's': // s .... .... .sss .... 0<=s<=7
175 sprintf(temp, "%d", (code&0x70)>>4);
177 case 'b': // b .... .... .... .bbb 0<=b<=7
178 sprintf(temp, "%d", code&0x7);
180 case 'k': // k .... ..kk kkkk k... -64<=k<=+63
182 int k= (code&0x3f8)>>3;
185 sprintf(temp, "0x%06x", k+1+(signed int)addr);
188 case 'A': // k .... ...k kkkk ...k 0<=k<=64K
189 // kkkk kkkk kkkk kkkk 0<=k<=4M
190 sprintf(temp, "0x%06x",
191 (((code&0x1f0)>>3)|(code&1))*0x10000+
192 (uint)get_mem(MEM_ROM, addr+1));
194 case 'P': // P .... .... pppp p... 0<=P<=31
195 data= (code&0xf8)>>3;
196 if (!get_name(data+0x20, sfr_tbl(), temp))
197 sprintf(temp, "%d", data);
199 case 'p': // P .... .PP. .... PPPP 0<=P<=63
200 data= ((code&0x600)>>5)|(code&0xf);
201 if (!get_name(data+0x20, sfr_tbl(), temp))
202 sprintf(temp, "%d", data);
204 case 'q': // q ..q. qq.. .... .qqq 0<=q<=63
206 ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&7));
208 case 'R': // k SRAM address on second word 0<=k<=65535
209 sprintf(temp, "0x%06x", (uint)get_mem(MEM_ROM, addr+1));
211 case 'a': // k .... kkkk kkkk kkkk -2k<=k<=2k
216 sprintf(temp, "0x%06lx",
217 (k+1+(signed int)addr) % rom->size);
233 p= strchr(work, ' ');
240 buf= (char *)malloc(6+strlen(p)+1);
242 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
243 for (p= work, b= buf; *p != ' '; p++, b++)
249 while (strlen(buf) < 6)
260 cl_z80::print_regs(class cl_console *con)
262 con->dd_printf("SZ-A--P-C Flags= 0x%02x %3d %c ",
263 regs.F, regs.F, isprint(regs.F)?regs.F:'.');
264 con->dd_printf("A= 0x%02x %3d %c\n",
265 regs.A, regs.A, isprint(regs.A)?regs.A:'.');
266 con->dd_printf("%c%c-%c--%c-%c\n",
267 (regs.F&BIT_S)?'1':'0',
268 (regs.F&BIT_Z)?'1':'0',
269 (regs.F&BIT_A)?'1':'0',
270 (regs.F&BIT_P)?'1':'0',
271 (regs.F&BIT_C)?'1':'0');
272 con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
273 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
274 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
275 con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
276 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
277 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
278 con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
279 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
280 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
281 con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ",
282 regs.IX, ram->get(regs.IX), ram->get(regs.IX),
283 isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
284 con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ",
285 regs.IY, ram->get(regs.IY), ram->get(regs.IY),
286 isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
287 con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
288 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
289 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
291 print_disass(PC, con);
300 cl_z80::exec_inst(void)
305 return(resBREAKPOINT);
315 PC= get_mem_size(MEM_ROM)-1;
316 //tick(-clock_per_cycle());
317 sim->stop(resINV_INST);
322 /* End of z80.src/z80.cc */