2 * Simulator of microcontrollers (inst_xxcb.cc)
3 * DD CB or FD CB escaped multi-byte opcodes for Z80.
5 * This module gets pulled in and pre-processed to create
6 * two modules. DD CB prefixed opcodes reference
7 * IX register, while FD CB prefixes reference IY register.
8 * See inst_ddcb.cc and inst_fdcb.cc
10 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
12 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
16 /* This file is part of microcontroller simulator: ucsim.
18 UCSIM is free software; you can redistribute it and/or modify
19 it under the terms of the GNU General Public License as published by
20 the Free Software Foundation; either version 2 of the License, or
21 (at your option) any later version.
23 UCSIM is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with UCSIM; see the file COPYING. If not, write to the Free
30 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
34 static unsigned char n_offset;
37 cl_z80::inst_XXcb_rlc(t_mem code)
42 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
65 case 0x06: // RLC (HL)
80 cl_z80::inst_XXcb_rrc(t_mem code)
84 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
107 case 0x0E: // RRC (HL)
122 cl_z80::inst_XXcb_rl(t_mem code)
126 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
149 case 0x16: // RL (HL)
164 cl_z80::inst_XXcb_rr(t_mem code)
168 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
191 case 0x1E: // RR (HL)
206 cl_z80::inst_XXcb_sla(t_mem code)
210 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
233 case 0x26: // SLA (HL)
247 cl_z80::inst_XXcb_sra(t_mem code)
251 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
274 case 0x2E: // SRA (HL)
288 cl_z80::inst_XXcb_slia(t_mem code)
292 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
297 case 0x30: // SLIA B (Shift Left Inverted Arithmetic)
300 case 0x31: // SLIA C like SLA, but shifts in a 1 bit
315 case 0x36: // SLIA (HL)
329 cl_z80::inst_XXcb_srl(t_mem code)
333 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
356 case 0x3E: // SRL (HL)
371 cl_z80::inst_XXcb_bit(t_mem code)
376 #define bit_bitnum ((code >> 3) & 7)
378 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
380 bit_byte(tmp, bit_bitnum);
388 cl_z80::inst_XXcb_res(t_mem code)
393 #define bit_bitnum ((code >> 3) & 7)
395 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
397 tmp &= ~(1 << bit_bitnum);
401 regs.bc.h = tmp; break;
403 regs.bc.l = tmp; break;
405 regs.de.h = tmp; break;
407 regs.de.l = tmp; break;
409 regs.hl.h = tmp; break;
411 regs.hl.l = tmp; break;
412 case 0x6: // RES x,(HL)
423 cl_z80::inst_XXcb_set(t_mem code)
428 #define bit_bitnum ((code >> 3) & 7)
430 addr = add_u16_disp(regs_IX_OR_IY, n_offset);
432 tmp |= (1 << bit_bitnum);
436 regs.bc.h = tmp; break;
438 regs.bc.l = tmp; break;
440 regs.de.h = tmp; break;
442 regs.de.l = tmp; break;
444 regs.de.h = tmp; break;
446 regs.de.h = tmp; break;
447 case 0x6: // SET x,(IX+dd)
450 regs.de.h = tmp; break;
460 /******** start CB codes *****************/
462 cl_z80::inst_XXcb(void)
466 // all DD CB escaped opcodes have a 3rd byte which is a displacement,
467 // 4th byte is opcode extension.
471 return(resBREAKPOINT);
481 case 0x06: // RLC (HL)
483 return (inst_XXcb_rlc(code));
490 case 0x0E: // RRC (HL)
492 return (inst_XXcb_rrc(code));
499 case 0x16: // RL (HL)
501 return (inst_XXcb_rl(code));
508 case 0x1E: // RR (HL)
510 return (inst_XXcb_rr(code));
517 case 0x26: // SLA (HL)
519 return (inst_XXcb_sla(code));
526 case 0x2E: // SRA (HL)
528 return (inst_XXcb_sra(code));
529 case 0x30: // SLIA B (Shift Left Inverted Arithmetic)
530 case 0x31: // SLIA C like SLA, but shifts in a 1 bit
535 case 0x36: // SLIA (HL)
537 return (inst_XXcb_slia(code));
544 case 0x3E: // SRL (HL)
546 return (inst_XXcb_srl(code));
547 case 0x46: // BIT 0,(HL)
548 case 0x4E: // BIT 1,(HL)
549 case 0x56: // BIT 2,(HL)
550 case 0x5E: // BIT 3,(HL)
551 case 0x66: // BIT 4,(HL)
552 case 0x6E: // BIT 5,(HL)
553 case 0x76: // BIT 6,(HL)
554 case 0x7E: // BIT 7,(HL)
555 return (inst_XXcb_bit(code));
556 case 0x80: // RES 0,B
557 case 0x81: // RES 0,C
558 case 0x82: // RES 0,D
559 case 0x83: // RES 0,E
560 case 0x84: // RES 0,H
561 case 0x85: // RES 0,L
562 case 0x86: // RES 0,(HL)
563 case 0x87: // RES 0,A
564 case 0x88: // RES 1,B
565 case 0x89: // RES 1,C
566 case 0x8A: // RES 1,D
567 case 0x8B: // RES 1,E
568 case 0x8C: // RES 1,H
569 case 0x8D: // RES 1,L
570 case 0x8E: // RES 1,(HL)
571 case 0x8F: // RES 1,A
572 case 0x90: // RES 2,B
573 case 0x91: // RES 2,C
574 case 0x92: // RES 2,D
575 case 0x93: // RES 2,E
576 case 0x94: // RES 2,H
577 case 0x95: // RES 2,L
578 case 0x96: // RES 2,(HL)
579 case 0x97: // RES 2,A
580 case 0x98: // RES 3,B
581 case 0x99: // RES 3,C
582 case 0x9A: // RES 3,D
583 case 0x9B: // RES 3,E
584 case 0x9C: // RES 3,H
585 case 0x9D: // RES 3,L
586 case 0x9E: // RES 3,(HL)
587 case 0x9F: // RES 3,A
588 case 0xA0: // RES 4,B
589 case 0xA1: // RES 4,C
590 case 0xA2: // RES 4,D
591 case 0xA3: // RES 4,E
592 case 0xA4: // RES 4,H
593 case 0xA5: // RES 4,L
594 case 0xA6: // RES 4,(HL)
595 case 0xA7: // RES 4,A
596 case 0xA8: // RES 5,B
597 case 0xA9: // RES 5,C
598 case 0xAA: // RES 5,D
599 case 0xAB: // RES 5,E
600 case 0xAC: // RES 5,H
601 case 0xAD: // RES 5,L
602 case 0xAE: // RES 5,(HL)
603 case 0xAF: // RES 5,A
604 case 0xB0: // RES 6,B
605 case 0xB1: // RES 6,C
606 case 0xB2: // RES 6,D
607 case 0xB3: // RES 6,E
608 case 0xB4: // RES 6,H
609 case 0xB5: // RES 6,L
610 case 0xB6: // RES 6,(HL)
611 case 0xB7: // RES 6,A
612 case 0xB8: // RES 7,B
613 case 0xB9: // RES 7,C
614 case 0xBA: // RES 7,D
615 case 0xBB: // RES 7,E
616 case 0xBC: // RES 7,H
617 case 0xBD: // RES 7,L
618 case 0xBE: // RES 7,(HL)
619 case 0xBF: // RES 7,A
620 return (inst_XXcb_res(code));
621 case 0xC0: // SET 0,B
622 case 0xC1: // SET 0,C
623 case 0xC2: // SET 0,D
624 case 0xC3: // SET 0,E
625 case 0xC4: // SET 0,H
626 case 0xC5: // SET 0,L
627 case 0xC6: // SET 0,(HL)
628 case 0xC7: // SET 0,A
629 case 0xC8: // SET 1,B
630 case 0xC9: // SET 1,C
631 case 0xCA: // SET 1,D
632 case 0xCB: // SET 1,E
633 case 0xCC: // SET 1,H
634 case 0xCD: // SET 1,L
635 case 0xCE: // SET 1,(HL)
636 case 0xCF: // SET 1,A
637 case 0xD0: // SET 2,B
638 case 0xD1: // SET 2,C
639 case 0xD2: // SET 2,D
640 case 0xD3: // SET 2,E
641 case 0xD4: // SET 2,H
642 case 0xD5: // SET 2,L
643 case 0xD6: // SET 2,(HL)
644 case 0xD7: // SET 2,A
645 case 0xD8: // SET 3,B
646 case 0xD9: // SET 3,C
647 case 0xDA: // SET 3,D
648 case 0xDB: // SET 3,E
649 case 0xDC: // SET 3,H
650 case 0xDD: // SET 3,L
651 case 0xDE: // SET 3,(HL)
652 case 0xDF: // SET 3,A
653 case 0xE0: // SET 4,B
654 case 0xE1: // SET 4,C
655 case 0xE2: // SET 4,D
656 case 0xE3: // SET 4,E
657 case 0xE4: // SET 4,H
658 case 0xE5: // SET 4,L
659 case 0xE6: // SET 4,(HL)
660 case 0xE7: // SET 4,A
661 case 0xE8: // SET 5,B
662 case 0xE9: // SET 5,C
663 case 0xEA: // SET 5,D
664 case 0xEB: // SET 5,E
665 case 0xEC: // SET 5,H
666 case 0xED: // SET 5,L
667 case 0xEE: // SET 5,(HL)
668 case 0xEF: // SET 5,A
669 case 0xF0: // SET 6,B
670 case 0xF1: // SET 6,C
671 case 0xF2: // SET 6,D
672 case 0xF3: // SET 6,E
673 case 0xF4: // SET 6,H
674 case 0xF5: // SET 6,L
675 case 0xF6: // SET 6,(HL)
676 case 0xF7: // SET 6,A
677 case 0xF8: // SET 7,B
678 case 0xF9: // SET 7,C
679 case 0xFA: // SET 7,D
680 case 0xFB: // SET 7,E
681 case 0xFC: // SET 7,H
682 case 0xFD: // SET 7,L
683 case 0xFE: // SET 7,(HL)
684 case 0xFF: // SET 7,A
685 return (inst_XXcb_set(code));
690 PC= get_mem_size(MEM_ROM_ID)-1;*/
691 PC= rom->inc_address(PC, -1);
695 /* End of z80.src/inst_xxcb.cc */