2 * Simulator of microcontrollers (inst_ed.cc)
3 * ED escaped multi-byte opcodes for Z80.
5 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
7 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
11 /* This file is part of microcontroller simulator: ucsim.
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 cl_z80::inst_ed_(t_mem code)
45 /******** start CB codes *****************/
53 return(resBREAKPOINT);
58 case 0x40: // IN B,(C)
60 case 0x41: // OUT (C),B
63 case 0x42: // SBC HL,BC
64 sbc_HL_wordreg(regs.BC);
66 case 0x43: // LD (nnnn),BC
71 regs.F &= ~(BIT_ALL); /* clear these */
73 regs.F |= BIT_N; /* not addition */
74 if (regs.A == 0) regs.F |= BIT_Z;
75 if (regs.A & 0x80) regs.F |= BIT_S;
76 /* Skip BIT_A for now */
78 case 0x45: // RETN (return from non-maskable interrupt)
83 /* interrupt device puts opcode on data bus */
90 case 0x48: // IN C,(C)
92 case 0x49: // OUT (C),C
95 case 0x4A: // ADC HL,BC
96 adc_HL_wordreg(regs.BC);
98 case 0x4B: // LD BC,(nnnn)
102 case 0x4D: // RETI (return from interrupt)
106 /* Load "refresh" register(whats that?) */
109 case 0x50: // IN D,(C)
111 case 0x51: // OUT (C),D
114 case 0x52: // SBC HL,DE
115 sbc_HL_wordreg(regs.DE);
117 case 0x53: // LD (nnnn),DE
125 case 0x57: // LD A,IV
129 case 0x58: // IN E,(C)
131 case 0x59: // OUT (C),E
134 case 0x5A: // ADC HL,DE
135 adc_HL_wordreg(regs.DE);
137 case 0x5B: // LD DE,(nnnn)
147 case 0x60: // IN H,(C)
149 case 0x61: // OUT (C),H
152 case 0x62: // SBC HL,HL
153 sbc_HL_wordreg(regs.HL);
155 case 0x63: // LD (nnnn),HL opcode 22 does the same faster
164 case 0x68: // IN L,(C)
166 case 0x69: // OUT (C),L
169 case 0x6A: // ADC HL,HL
170 adc_HL_wordreg(regs.HL);
172 case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster
179 /* rotate 1 bcd digit left between ACC and memory location */
183 case 0x70: // IN (C) set flags only (TSTI)
185 case 0x71: // OUT (C),0
188 case 0x72: // SBC HL,SP
189 sbc_HL_wordreg(regs.SP);
191 case 0x73: // LD (nnnn),SP
196 case 0x78: // IN A,(C)
198 case 0x79: // OUT (C),A
201 case 0x7A: // ADC HL,SP
202 adc_HL_wordreg(regs.SP);
204 case 0x7B: // LD SP,(nnnn)
210 // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero
211 regs.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
212 store1(regs.DE, get1(regs.HL));
216 if (regs.BC != 0) regs.F |= BIT_P;
219 // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC.
226 if (regs.BC != 0) regs.F |= BIT_P;
236 // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero
237 regs.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
238 store1(regs.DE, get1(regs.HL));
242 if (regs.BC != 0) regs.F |= BIT_P;
245 /* fixme: checkme, compare to other emul. */
247 regs.F &= ~(BIT_ALL); /* clear these */
248 if ((regs.A - get1(regs.HL)) == 0) {
249 regs.F |= (BIT_Z | BIT_P);
253 if (regs.BC != 0) regs.F |= BIT_P;
263 // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero
264 regs.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
266 store1(regs.DE, get1(regs.HL));
270 } while (regs.BC != 0);
274 /* fixme: checkme, compare to other emul. */
275 // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC.
276 regs.F &= ~(BIT_ALL); /* clear these */
277 regs.F |= BIT_N | BIT_P;
279 if ((regs.A - get1(regs.HL)) == 0) {
280 regs.F |= (BIT_Z | BIT_P);
285 } while (regs.BC != 0);
295 // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero
296 regs.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
298 store1(regs.DE, get1(regs.HL));
302 } while (regs.BC != 0);
305 // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC.
306 regs.F &= ~(BIT_ALL); /* clear these */
308 if ((regs.A - get1(regs.HL)) == 0) {
309 regs.F |= (BIT_Z | BIT_P);
314 } while (regs.BC != 0);
330 /* End of z80.src/inst_ed.cc */