2 * Simulator of microcontrollers (inst.cc)
4 * some z80 code base from Karl Bongers karl@turbobit.com
6 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
8 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
12 /* This file is part of microcontroller simulator: ucsim.
14 UCSIM is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 UCSIM is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with UCSIM; see the file COPYING. If not, write to the Free
26 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
42 *----------------------------------------------------------------------------
46 cl_z80::inst_nop(t_mem code)
55 *----------------------------------------------------------------------------
59 cl_z80::inst_ld(t_mem code)
66 store1(regs.BC, regs.A);
71 case 0xa: // LD A,(BC)
72 regs.A = get1(regs.BC);
77 case 0x11: // LD DE,nnnn
80 case 0x12: // LD (DE),A
81 store1(regs.DE, regs.A);
86 case 0x1A: // LD A,(DE)
87 regs.A = get1(regs.DE);
92 case 0x21: // LD HL,nnnn
95 case 0x22: // LD (nnnn),HL
102 case 0x26: // LD H,nn
105 case 0x2A: // LD HL,(nnnn)
112 case 0x2E: // LD L,nn
115 case 0x31: // LD SP,nnnn
118 case 0x32: // LD (nnnn),A
125 case 0x36: // LD (HL),nn
126 store1(regs.HL, fetch());
128 case 0x3A: // LD A,(nnnn)
129 regs.A = get1(fetch2());
131 case 0x3E: // LD A,nn
137 regs.bc.h = regs.bc.l;
140 regs.bc.h = regs.de.h;
143 regs.bc.h = regs.de.l;
146 regs.bc.h = regs.hl.h;
149 regs.bc.h = regs.hl.l;
151 case 0x46: // LD B,(HL)
152 regs.bc.h = get1(regs.HL);
158 regs.bc.l = regs.bc.h;
163 regs.bc.l = regs.de.h;
166 regs.bc.l = regs.de.l;
169 regs.bc.l = regs.hl.h;
172 regs.bc.l = regs.hl.l;
174 case 0x4E: // LD C,(HL)
175 regs.bc.l = get1(regs.HL);
181 regs.de.h = regs.bc.h;
184 regs.de.h = regs.bc.l;
189 regs.de.h = regs.de.l;
192 regs.de.h = regs.hl.h;
195 regs.de.h = regs.hl.l;
197 case 0x56: // LD D,(HL)
198 regs.de.h = get1(regs.HL);
204 regs.de.l = regs.bc.h;
207 regs.de.l = regs.bc.l;
210 regs.de.l = regs.de.h;
215 regs.de.l = regs.hl.h;
218 regs.de.l = regs.hl.l;
220 case 0x5E: // LD E,(HL)
221 regs.de.l = get1(regs.HL);
227 regs.hl.h = regs.bc.h;
230 regs.hl.h = regs.bc.l;
233 regs.hl.h = regs.de.h;
236 regs.hl.h = regs.de.l;
239 regs.hl.h = regs.hl.h;
242 regs.hl.h = regs.hl.l;
244 case 0x66: // LD H,(HL)
245 regs.hl.h = get1(regs.HL);
251 regs.hl.l = regs.bc.h;
254 regs.hl.l = regs.bc.l;
257 regs.hl.l = regs.de.h;
260 regs.hl.l = regs.de.l;
263 regs.hl.l = regs.hl.h;
267 case 0x6E: // LD L,(HL)
268 regs.hl.l = get1(regs.HL);
273 case 0x70: // LD (HL),B
274 store1(regs.HL, regs.bc.h);
276 case 0x71: // LD (HL),C
277 store1(regs.HL, regs.bc.l);
279 case 0x72: // LD (HL),D
280 store1(regs.HL, regs.de.h);
282 case 0x73: // LD (HL),E
283 store1(regs.HL, regs.de.l);
285 case 0x74: // LD (HL),H
286 store1(regs.HL, regs.hl.h);
288 case 0x75: // LD (HL),L
289 store1(regs.HL, regs.hl.l);
294 case 0x77: // LD (HL),A
295 store1(regs.HL, regs.A);
315 case 0x7E: // LD A,(HL)
316 regs.A = get1(regs.HL);
320 case 0xF9: // LD SP,HL
331 cl_z80::inst_inc(t_mem code)
364 case 0x34: // INC (HL)
365 {unsigned char t=get1(regs.HL);
381 cl_z80::inst_dec(t_mem code)
411 case 0x35: // DEC (HL)
412 {unsigned char t=get1(regs.HL);
431 cl_z80::inst_rlca(t_mem code)
439 cl_z80::inst_rrca(t_mem code)
446 cl_z80::inst_ex(t_mem code)
448 /* 0x08 // EX AF,AF' */
453 case 0x08: // EX AF,AF'
463 case 0xE3: // EX (SP),HL
465 regs.HL = get2(regs.SP);
466 store2(regs.SP, tempw);
469 case 0xEB: // EX DE,HL
484 cl_z80::inst_add(t_mem code)
486 #define add_HL_Word(wr) { \
488 regs.F &= ~(BIT_ALL); /* clear these */ \
489 tmp = (unsigned int)regs.HL + (unsigned int)(wr); \
490 if (tmp > 0xffff) regs.F |= BIT_C; \
491 regs.HL = (unsigned short) tmp; }
494 case 0x09: // ADD HL,BC
495 add_HL_Word(regs.BC);
497 case 0x19: // ADD HL,DE
498 add_HL_Word(regs.DE);
500 case 0x29: // ADD HL,HL
501 add_HL_Word(regs.HL);
503 case 0x39: // ADD HL,SP
504 add_HL_Word(regs.SP);
507 case 0x80: // ADD A,B
508 add_A_bytereg(regs.bc.h);
510 case 0x81: // ADD A,C
511 add_A_bytereg(regs.bc.l);
513 case 0x82: // ADD A,D
514 add_A_bytereg(regs.de.h);
516 case 0x83: // ADD A,E
517 add_A_bytereg(regs.de.l);
519 case 0x84: // ADD A,H
520 add_A_bytereg(regs.hl.h);
522 case 0x85: // ADD A,L
523 add_A_bytereg(regs.hl.l);
526 case 0x86: // ADD A,(HL)
527 { unsigned char utmp;
528 utmp = get1(regs.HL);
533 case 0x87: // ADD A,A
534 add_A_bytereg(regs.A);
537 case 0xC6: // ADD A,nn
541 add_A_bytereg(utmp1);
554 cl_z80::inst_djnz(t_mem code)
561 if ((--regs.bc.h != 0)) {
569 cl_z80::inst_rra(t_mem code)
576 cl_z80::inst_rla(t_mem code)
583 cl_z80::inst_jr(t_mem code)
592 case 0x20: // JR NZ,dd
593 if (!(regs.F & BIT_Z)) {
597 case 0x28: // JR Z,dd
598 if ((regs.F & BIT_Z)) {
602 case 0x30: // JR NC,dd
603 if (!(regs.F & BIT_C)) {
607 case 0x38: // JR C,dd
608 if ((regs.F & BIT_C)) {
620 cl_z80::inst_daa(t_mem code)
622 /************* from MH's z80ops.c:
623 unsigned char incr=0, carry=cy;
624 if((f&0x10) || (a&0x0f)>9) incr=6;
625 if((f&1) || (a>>4)>9) incr|=0x60;
628 if(a>0x90 && (a&15)>9)incr|=0x60;
633 /* I have not tried to understand this archaic bit of BCD logic(kpb),
634 taking the lazy way out for now and just transcribing MH's code.
637 if ((regs.F & BIT_A) || ((regs.A & 0x0f) > 9))
641 if ((regs.F & BIT_C) || ((regs.A & 0xf0) > 0x90))
644 if (regs.F & BIT_N) { /* not addition */
647 if ((regs.A > 0x90) && ((regs.A & 0x0f) >9)) incr |= 0x60;
655 cl_z80::inst_cpl(t_mem code)
657 regs.F |= (BIT_A | BIT_N);
663 cl_z80::inst_scf(t_mem code)
671 cl_z80::inst_ccf(t_mem code)
673 /* Compliment Carry Flag */
679 cl_z80::inst_halt(t_mem code)
685 cl_z80::inst_adc(t_mem code)
688 case 0x88: // ADC A,B
689 adc_A_bytereg(regs.bc.h);
691 case 0x89: // ADC A,C
692 adc_A_bytereg(regs.bc.l);
694 case 0x8A: // ADC A,D
695 adc_A_bytereg(regs.de.h);
697 case 0x8B: // ADC A,E
698 adc_A_bytereg(regs.de.l);
700 case 0x8C: // ADC A,H
701 adc_A_bytereg(regs.hl.h);
703 case 0x8D: // ADC A,L
704 adc_A_bytereg(regs.hl.l);
706 case 0x8E: // ADC A,(HL)
707 { unsigned char utmp;
708 utmp = get1(regs.HL);
712 case 0x8F: // ADC A,A
713 adc_A_bytereg(regs.A);
716 case 0xCE: // ADC A,nn
717 { unsigned char utmp;
731 cl_z80::inst_sbc(t_mem code)
734 case 0x98: // SBC A,B
735 sbc_A_bytereg(regs.bc.h);
737 case 0x99: // SBC A,C
738 sbc_A_bytereg(regs.bc.l);
740 case 0x9A: // SBC A,D
741 sbc_A_bytereg(regs.de.h);
743 case 0x9B: // SBC A,E
744 sbc_A_bytereg(regs.de.l);
746 case 0x9C: // SBC A,H
747 sbc_A_bytereg(regs.hl.h);
749 case 0x9D: // SBC A,L
750 sbc_A_bytereg(regs.hl.l);
752 case 0x9E: // SBC A,(HL)
753 { unsigned char utmp;
754 utmp = get1(regs.HL);
758 case 0x9F: // SBC A,A
759 sbc_A_bytereg(regs.A);
761 case 0xDE: // SBC A,nn
762 { unsigned char utmp;
775 cl_z80::inst_and(t_mem code)
779 and_A_bytereg(regs.bc.h);
782 and_A_bytereg(regs.bc.l);
785 and_A_bytereg(regs.de.h);
788 and_A_bytereg(regs.de.l);
791 and_A_bytereg(regs.hl.h);
794 and_A_bytereg(regs.hl.l);
796 case 0xA6: // AND (HL)
797 { unsigned char utmp;
798 utmp = get1(regs.HL);
803 and_A_bytereg(regs.A);
806 and_A_bytereg(fetch());
817 cl_z80::inst_xor(t_mem code)
821 xor_A_bytereg(regs.bc.h);
824 xor_A_bytereg(regs.bc.l);
827 xor_A_bytereg(regs.de.h);
830 xor_A_bytereg(regs.de.l);
833 xor_A_bytereg(regs.hl.h);
836 xor_A_bytereg(regs.hl.l);
838 case 0xAE: // XOR (HL)
839 { unsigned char utmp;
840 utmp = get1(regs.HL);
845 xor_A_bytereg(regs.A);
848 xor_A_bytereg(fetch());
859 cl_z80::inst_or(t_mem code)
863 or_A_bytereg(regs.bc.h);
866 or_A_bytereg(regs.bc.l);
869 or_A_bytereg(regs.de.h);
872 or_A_bytereg(regs.de.l);
875 or_A_bytereg(regs.hl.h);
878 or_A_bytereg(regs.hl.l);
880 case 0xB6: // OR (HL)
881 { unsigned char utmp;
882 utmp = get1(regs.HL);
887 or_A_bytereg(regs.A);
890 or_A_bytereg(fetch());
900 cl_z80::inst_cp(t_mem code)
902 /* Compare with Accumulator - subtract and test, leave A unchanged */
905 cp_bytereg(regs.bc.h);
908 cp_bytereg(regs.bc.l);
911 cp_bytereg(regs.de.h);
914 cp_bytereg(regs.de.l);
917 cp_bytereg(regs.hl.h);
920 cp_bytereg(regs.hl.l);
922 case 0xBE: // CP (HL)
923 { unsigned char utmp;
924 utmp = get1(regs.HL);
932 { unsigned char utmp;
945 cl_z80::inst_rst(t_mem code)
960 //printf("PUTCHAR-----> %xH\n", regs.hl.l);
966 case 0xD7: // RST 10H
970 case 0xDF: // RST 18H
974 case 0xE7: // RST 20H
978 case 0xEF: // RST 28H
982 case 0xF7: // RST 30H
986 case 0xFF: // RST 38H
998 cl_z80::inst_ret(t_mem code)
1001 case 0xC0: // RET NZ
1002 if (!(regs.F & BIT_Z)) {
1007 if ((regs.F & BIT_Z)) {
1014 case 0xD0: // RET NC
1015 if (!(regs.F & BIT_C)) {
1020 if ((regs.F & BIT_C)) {
1024 case 0xE0: // RET PO
1025 if (!(regs.F & BIT_P)) {
1029 case 0xE8: // RET PE
1030 if ((regs.F & BIT_P)) {
1035 if (!(regs.F & BIT_S)) {
1040 if ((regs.F & BIT_S)) {
1045 return(resINV_INST);
1052 cl_z80::inst_call(t_mem code)
1057 case 0xC4: // CALL NZ,nnnn
1058 if (!(regs.F & BIT_Z)) {
1065 case 0xCC: // CALL Z,nnnn
1066 if (regs.F & BIT_Z) {
1073 case 0xCD: // CALL nnnn
1077 case 0xD4: // CALL NC,nnnn
1078 if (!(regs.F & BIT_C)) {
1085 case 0xDC: // CALL C,nnnn
1086 if (regs.F & BIT_C) {
1093 case 0xE4: // CALL PO,nnnn
1094 if (!(regs.F & BIT_P)) {
1101 case 0xEC: // CALL PE,nnnn
1102 if (regs.F & BIT_P) {
1109 case 0xF4: // CALL P,nnnn
1110 if (!(regs.F & BIT_S)) {
1117 case 0xFC: // CALL M,nnnn
1118 if (regs.F & BIT_S) {
1126 return(resINV_INST);
1134 cl_z80::inst_out(t_mem code)
1140 cl_z80::inst_push(t_mem code)
1143 case 0xC5: // PUSH BC
1146 case 0xD5: // PUSH DE
1149 case 0xE5: // PUSH HL
1152 case 0xF5: // PUSH AF
1157 return(resINV_INST);
1164 cl_z80::inst_exx(t_mem code)
1166 /* case 0xD9: // EXX - swap BC,DE,HL with alternates */
1185 cl_z80::inst_in(t_mem code)
1191 cl_z80::inst_sub(t_mem code)
1195 sub_A_bytereg(regs.bc.h);
1198 sub_A_bytereg(regs.bc.l);
1201 sub_A_bytereg(regs.de.h);
1204 sub_A_bytereg(regs.de.l);
1207 sub_A_bytereg(regs.hl.h);
1210 sub_A_bytereg(regs.hl.l);
1212 case 0x96: // SUB (HL)
1213 { unsigned char tmp1;
1214 tmp1 = get1(regs.HL);
1215 sub_A_bytereg(tmp1);
1221 case 0xD6: // SUB nn
1222 { unsigned char tmp1;
1224 sub_A_bytereg(tmp1);
1228 return(resINV_INST);
1235 cl_z80::inst_pop(t_mem code)
1238 case 0xC1: // POP BC
1239 regs.BC = get2(regs.SP);
1242 case 0xD1: // POP DE
1243 regs.DE = get2(regs.SP);
1246 case 0xE1: // POP HL
1247 regs.HL = get2(regs.SP);
1250 case 0xF1: // POP AF
1251 regs.A = get1(regs.SP++);
1252 regs.F = get1(regs.SP++);
1255 return(resINV_INST);
1262 cl_z80::inst_jp(t_mem code)
1267 case 0xC2: // JP NZ,nnnn
1268 if (!(regs.F & BIT_Z)) {
1275 case 0xC3: // JP nnnn
1279 case 0xCA: // JP Z,nnnn
1280 if (regs.F & BIT_Z) {
1287 case 0xD2: // JP NC,nnnn
1288 if (!(regs.F & BIT_C)) {
1295 case 0xDA: // JP C,nnnn
1296 if (regs.F & BIT_C) {
1303 case 0xE2: // JP PO,nnnn
1304 if (regs.F & BIT_P) {
1311 case 0xE9: // JP (HL)
1315 case 0xea: // JP PO,nnnn
1316 if (!(regs.F & BIT_P)) {
1323 case 0xF2: // JP P,nnnn (positive)
1324 if (!(regs.F & BIT_S)) {
1331 case 0xfa: // JP M,nnnn (sign negative)
1332 if (regs.F & BIT_S) {
1339 return(resINV_INST);
1346 cl_z80::inst_di(t_mem code)
1348 /* disable interrupts */
1353 cl_z80::inst_ei(t_mem code)
1355 /* enable interrupts */
1359 /* End of z80.src/inst.cc */