2 * Simulator of microcontrollers (inst.cc)
4 * some z80 code base from Karl Bongers karl@turbobit.com
6 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
8 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
12 /* This file is part of microcontroller simulator: ucsim.
14 UCSIM is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 UCSIM is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with UCSIM; see the file COPYING. If not, write to the Free
26 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
44 *----------------------------------------------------------------------------
48 cl_z80::inst_nop(t_mem code)
57 *----------------------------------------------------------------------------
61 cl_z80::inst_ld(t_mem code)
68 store1(regs.BC, regs.A);
73 case 0xa: // LD A,(BC)
74 regs.A = get1(regs.BC);
79 case 0x11: // LD DE,nnnn
82 case 0x12: // LD (DE),A
83 store1(regs.DE, regs.A);
88 case 0x1A: // LD A,(DE)
89 regs.A = get1(regs.DE);
94 case 0x21: // LD HL,nnnn
97 case 0x22: // LD (nnnn),HL
104 case 0x26: // LD H,nn
107 case 0x2A: // LD HL,(nnnn)
114 case 0x2E: // LD L,nn
117 case 0x31: // LD SP,nnnn
120 case 0x32: // LD (nnnn),A
127 case 0x36: // LD (HL),nn
128 store1(regs.HL, fetch());
130 case 0x3A: // LD A,(nnnn)
131 regs.A = get1(fetch2());
133 case 0x3E: // LD A,nn
139 regs.bc.h = regs.bc.l;
142 regs.bc.h = regs.de.h;
145 regs.bc.h = regs.de.l;
148 regs.bc.h = regs.hl.h;
151 regs.bc.h = regs.hl.l;
153 case 0x46: // LD B,(HL)
154 regs.bc.h = get1(regs.HL);
160 regs.bc.l = regs.bc.h;
165 regs.bc.l = regs.de.h;
168 regs.bc.l = regs.de.l;
171 regs.bc.l = regs.hl.h;
174 regs.bc.l = regs.hl.l;
176 case 0x4E: // LD C,(HL)
177 regs.bc.l = get1(regs.HL);
183 regs.de.h = regs.bc.h;
186 regs.de.h = regs.bc.l;
191 regs.de.h = regs.de.l;
194 regs.de.h = regs.hl.h;
197 regs.de.h = regs.hl.l;
199 case 0x56: // LD D,(HL)
200 regs.de.h = get1(regs.HL);
206 regs.de.l = regs.bc.h;
209 regs.de.l = regs.bc.l;
212 regs.de.l = regs.de.h;
217 regs.de.l = regs.hl.h;
220 regs.de.l = regs.hl.l;
222 case 0x5E: // LD E,(HL)
223 regs.de.l = get1(regs.HL);
229 regs.hl.h = regs.bc.h;
232 regs.hl.h = regs.bc.l;
235 regs.hl.h = regs.de.h;
238 regs.hl.h = regs.de.l;
241 regs.hl.h = regs.hl.h;
244 regs.hl.h = regs.hl.l;
246 case 0x66: // LD H,(HL)
247 regs.hl.h = get1(regs.HL);
253 regs.hl.l = regs.bc.h;
256 regs.hl.l = regs.bc.l;
259 regs.hl.l = regs.de.h;
262 regs.hl.l = regs.de.l;
265 regs.hl.l = regs.hl.h;
269 case 0x6E: // LD L,(HL)
270 regs.hl.l = get1(regs.HL);
275 case 0x70: // LD (HL),B
276 store1(regs.HL, regs.bc.h);
278 case 0x71: // LD (HL),C
279 store1(regs.HL, regs.bc.l);
281 case 0x72: // LD (HL),D
282 store1(regs.HL, regs.de.h);
284 case 0x73: // LD (HL),E
285 store1(regs.HL, regs.de.l);
287 case 0x74: // LD (HL),H
288 store1(regs.HL, regs.hl.h);
290 case 0x75: // LD (HL),L
291 store1(regs.HL, regs.hl.l);
296 case 0x77: // LD (HL),A
297 store1(regs.HL, regs.A);
317 case 0x7E: // LD A,(HL)
318 regs.A = get1(regs.HL);
322 case 0xF9: // LD SP,HL
333 cl_z80::inst_inc(t_mem code)
366 case 0x34: // INC (HL)
367 {unsigned char t=get1(regs.HL);
383 cl_z80::inst_dec(t_mem code)
413 case 0x35: // DEC (HL)
414 {unsigned char t=get1(regs.HL);
433 cl_z80::inst_rlca(t_mem code)
441 cl_z80::inst_rrca(t_mem code)
448 cl_z80::inst_ex(t_mem code)
450 /* 0x08 // EX AF,AF' */
455 case 0x08: // EX AF,AF'
465 case 0xE3: // EX (SP),HL
467 regs.HL = get2(regs.SP);
468 store2(regs.SP, tempw);
471 case 0xEB: // EX DE,HL
486 cl_z80::inst_add(t_mem code)
488 #define add_HL_Word(wr) { \
490 regs.F &= ~(BIT_ALL); /* clear these */ \
491 tmp = (unsigned int)regs.HL + (unsigned int)(wr); \
492 if (tmp > 0xffff) regs.F |= BIT_C; \
493 regs.HL = (unsigned short) tmp; }
496 case 0x09: // ADD HL,BC
497 add_HL_Word(regs.BC);
499 case 0x19: // ADD HL,DE
500 add_HL_Word(regs.DE);
502 case 0x29: // ADD HL,HL
503 add_HL_Word(regs.HL);
505 case 0x39: // ADD HL,SP
506 add_HL_Word(regs.SP);
509 case 0x80: // ADD A,B
510 add_A_bytereg(regs.bc.h);
512 case 0x81: // ADD A,C
513 add_A_bytereg(regs.bc.l);
515 case 0x82: // ADD A,D
516 add_A_bytereg(regs.de.h);
518 case 0x83: // ADD A,E
519 add_A_bytereg(regs.de.l);
521 case 0x84: // ADD A,H
522 add_A_bytereg(regs.hl.h);
524 case 0x85: // ADD A,L
525 add_A_bytereg(regs.hl.l);
528 case 0x86: // ADD A,(HL)
529 { unsigned char utmp;
530 utmp = get1(regs.HL);
535 case 0x87: // ADD A,A
536 add_A_bytereg(regs.A);
539 case 0xC6: // ADD A,nn
543 add_A_bytereg(utmp1);
556 cl_z80::inst_djnz(t_mem code)
563 if ((--regs.bc.h != 0)) {
571 cl_z80::inst_rra(t_mem code)
578 cl_z80::inst_rla(t_mem code)
585 cl_z80::inst_jr(t_mem code)
594 case 0x20: // JR NZ,dd
595 if (!(regs.F & BIT_Z)) {
599 case 0x28: // JR Z,dd
600 if ((regs.F & BIT_Z)) {
604 case 0x30: // JR NC,dd
605 if (!(regs.F & BIT_C)) {
609 case 0x38: // JR C,dd
610 if ((regs.F & BIT_C)) {
622 cl_z80::inst_daa(t_mem code)
624 /************* from MH's z80ops.c:
625 unsigned char incr=0, carry=cy;
626 if((f&0x10) || (a&0x0f)>9) incr=6;
627 if((f&1) || (a>>4)>9) incr|=0x60;
630 if(a>0x90 && (a&15)>9)incr|=0x60;
635 /* I have not tried to understand this archaic bit of BCD logic(kpb),
636 taking the lazy way out for now and just transcribing MH's code.
639 if ((regs.F & BIT_A) || ((regs.A & 0x0f) > 9))
643 if ((regs.F & BIT_C) || ((regs.A & 0xf0) > 0x90))
646 if (regs.F & BIT_N) { /* not addition */
649 if ((regs.A > 0x90) && ((regs.A & 0x0f) >9)) incr |= 0x60;
657 cl_z80::inst_cpl(t_mem code)
659 regs.F |= (BIT_A | BIT_N);
665 cl_z80::inst_scf(t_mem code)
673 cl_z80::inst_ccf(t_mem code)
675 /* Compliment Carry Flag */
681 cl_z80::inst_halt(t_mem code)
687 cl_z80::inst_adc(t_mem code)
690 case 0x88: // ADC A,B
691 adc_A_bytereg(regs.bc.h);
693 case 0x89: // ADC A,C
694 adc_A_bytereg(regs.bc.l);
696 case 0x8A: // ADC A,D
697 adc_A_bytereg(regs.de.h);
699 case 0x8B: // ADC A,E
700 adc_A_bytereg(regs.de.l);
702 case 0x8C: // ADC A,H
703 adc_A_bytereg(regs.hl.h);
705 case 0x8D: // ADC A,L
706 adc_A_bytereg(regs.hl.l);
708 case 0x8E: // ADC A,(HL)
709 { unsigned char utmp;
710 utmp = get1(regs.HL);
714 case 0x8F: // ADC A,A
715 adc_A_bytereg(regs.A);
718 case 0xCE: // ADC A,nn
719 { unsigned char utmp;
733 cl_z80::inst_sbc(t_mem code)
736 case 0x98: // SBC A,B
737 sbc_A_bytereg(regs.bc.h);
739 case 0x99: // SBC A,C
740 sbc_A_bytereg(regs.bc.l);
742 case 0x9A: // SBC A,D
743 sbc_A_bytereg(regs.de.h);
745 case 0x9B: // SBC A,E
746 sbc_A_bytereg(regs.de.l);
748 case 0x9C: // SBC A,H
749 sbc_A_bytereg(regs.hl.h);
751 case 0x9D: // SBC A,L
752 sbc_A_bytereg(regs.hl.l);
754 case 0x9E: // SBC A,(HL)
755 { unsigned char utmp;
756 utmp = get1(regs.HL);
760 case 0x9F: // SBC A,A
761 sbc_A_bytereg(regs.A);
763 case 0xDE: // SBC A,nn
764 { unsigned char utmp;
777 cl_z80::inst_and(t_mem code)
781 and_A_bytereg(regs.bc.h);
784 and_A_bytereg(regs.bc.l);
787 and_A_bytereg(regs.de.h);
790 and_A_bytereg(regs.de.l);
793 and_A_bytereg(regs.hl.h);
796 and_A_bytereg(regs.hl.l);
798 case 0xA6: // AND (HL)
799 { unsigned char utmp;
800 utmp = get1(regs.HL);
805 and_A_bytereg(regs.A);
808 and_A_bytereg(fetch());
819 cl_z80::inst_xor(t_mem code)
823 xor_A_bytereg(regs.bc.h);
826 xor_A_bytereg(regs.bc.l);
829 xor_A_bytereg(regs.de.h);
832 xor_A_bytereg(regs.de.l);
835 xor_A_bytereg(regs.hl.h);
838 xor_A_bytereg(regs.hl.l);
840 case 0xAE: // XOR (HL)
841 { unsigned char utmp;
842 utmp = get1(regs.HL);
847 xor_A_bytereg(regs.A);
850 xor_A_bytereg(fetch());
861 cl_z80::inst_or(t_mem code)
865 or_A_bytereg(regs.bc.h);
868 or_A_bytereg(regs.bc.l);
871 or_A_bytereg(regs.de.h);
874 or_A_bytereg(regs.de.l);
877 or_A_bytereg(regs.hl.h);
880 or_A_bytereg(regs.hl.l);
882 case 0xB6: // OR (HL)
883 { unsigned char utmp;
884 utmp = get1(regs.HL);
889 or_A_bytereg(regs.A);
892 or_A_bytereg(fetch());
902 cl_z80::inst_cp(t_mem code)
904 /* Compare with Accumulator - subtract and test, leave A unchanged */
907 cp_bytereg(regs.bc.h);
910 cp_bytereg(regs.bc.l);
913 cp_bytereg(regs.de.h);
916 cp_bytereg(regs.de.l);
919 cp_bytereg(regs.hl.h);
922 cp_bytereg(regs.hl.l);
924 case 0xBE: // CP (HL)
925 { unsigned char utmp;
926 utmp = get1(regs.HL);
934 { unsigned char utmp;
947 cl_z80::inst_rst(t_mem code)
962 //printf("PUTCHAR-----> %xH\n", regs.hl.l);
968 case 0xD7: // RST 10H
972 case 0xDF: // RST 18H
976 case 0xE7: // RST 20H
980 case 0xEF: // RST 28H
984 case 0xF7: // RST 30H
988 case 0xFF: // RST 38H
1000 cl_z80::inst_ret(t_mem code)
1003 case 0xC0: // RET NZ
1004 if (!(regs.F & BIT_Z)) {
1009 if ((regs.F & BIT_Z)) {
1016 case 0xD0: // RET NC
1017 if (!(regs.F & BIT_C)) {
1022 if ((regs.F & BIT_C)) {
1026 case 0xE0: // RET PO
1027 if (!(regs.F & BIT_P)) {
1031 case 0xE8: // RET PE
1032 if ((regs.F & BIT_P)) {
1037 if (!(regs.F & BIT_S)) {
1042 if ((regs.F & BIT_S)) {
1047 return(resINV_INST);
1054 cl_z80::inst_call(t_mem code)
1059 case 0xC4: // CALL NZ,nnnn
1060 if (!(regs.F & BIT_Z)) {
1067 case 0xCC: // CALL Z,nnnn
1068 if (regs.F & BIT_Z) {
1075 case 0xCD: // CALL nnnn
1079 case 0xD4: // CALL NC,nnnn
1080 if (!(regs.F & BIT_C)) {
1087 case 0xDC: // CALL C,nnnn
1088 if (regs.F & BIT_C) {
1095 case 0xE4: // CALL PO,nnnn
1096 if (!(regs.F & BIT_P)) {
1103 case 0xEC: // CALL PE,nnnn
1104 if (regs.F & BIT_P) {
1111 case 0xF4: // CALL P,nnnn
1112 if (!(regs.F & BIT_S)) {
1119 case 0xFC: // CALL M,nnnn
1120 if (regs.F & BIT_S) {
1128 return(resINV_INST);
1136 cl_z80::inst_out(t_mem code)
1142 cl_z80::inst_push(t_mem code)
1145 case 0xC5: // PUSH BC
1148 case 0xD5: // PUSH DE
1151 case 0xE5: // PUSH HL
1154 case 0xF5: // PUSH AF
1159 return(resINV_INST);
1166 cl_z80::inst_exx(t_mem code)
1168 /* case 0xD9: // EXX - swap BC,DE,HL with alternates */
1187 cl_z80::inst_in(t_mem code)
1193 cl_z80::inst_sub(t_mem code)
1197 sub_A_bytereg(regs.bc.h);
1200 sub_A_bytereg(regs.bc.l);
1203 sub_A_bytereg(regs.de.h);
1206 sub_A_bytereg(regs.de.l);
1209 sub_A_bytereg(regs.hl.h);
1212 sub_A_bytereg(regs.hl.l);
1214 case 0x96: // SUB (HL)
1215 { unsigned char tmp1;
1216 tmp1 = get1(regs.HL);
1217 sub_A_bytereg(tmp1);
1223 case 0xD6: // SUB nn
1224 { unsigned char tmp1;
1226 sub_A_bytereg(tmp1);
1230 return(resINV_INST);
1237 cl_z80::inst_pop(t_mem code)
1240 case 0xC1: // POP BC
1241 regs.BC = get2(regs.SP);
1244 case 0xD1: // POP DE
1245 regs.DE = get2(regs.SP);
1248 case 0xE1: // POP HL
1249 regs.HL = get2(regs.SP);
1252 case 0xF1: // POP AF
1253 regs.F = get1(regs.SP++);
1254 regs.A = get1(regs.SP++);
1257 return(resINV_INST);
1264 cl_z80::inst_jp(t_mem code)
1269 case 0xC2: // JP NZ,nnnn
1270 if (!(regs.F & BIT_Z)) {
1277 case 0xC3: // JP nnnn
1281 case 0xCA: // JP Z,nnnn
1282 if (regs.F & BIT_Z) {
1289 case 0xD2: // JP NC,nnnn
1290 if (!(regs.F & BIT_C)) {
1297 case 0xDA: // JP C,nnnn
1298 if (regs.F & BIT_C) {
1305 case 0xE2: // JP PO,nnnn
1306 if (regs.F & BIT_P) {
1313 case 0xE9: // JP (HL)
1317 case 0xea: // JP PO,nnnn
1318 if (!(regs.F & BIT_P)) {
1325 case 0xF2: // JP P,nnnn (positive)
1326 if (!(regs.F & BIT_S)) {
1333 case 0xfa: // JP M,nnnn (sign negative)
1334 if (regs.F & BIT_S) {
1341 return(resINV_INST);
1348 cl_z80::inst_di(t_mem code)
1350 /* disable interrupts */
1355 cl_z80::inst_ei(t_mem code)
1357 /* enable interrupts */
1361 /* End of z80.src/inst.cc */