2 * Simulator of microcontrollers (regsxa.h)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * Written by Karl Bongers karl@turbobit.com
8 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
12 /* This file is part of microcontroller simulator: ucsim.
14 UCSIM is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 UCSIM is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with UCSIM; see the file COPYING. If not, write to the Free
26 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
30 #ifndef REGSAVR_HEADER
31 #define REGSAVR_HEADER
40 /* macros suck, can we use inline functions instead
41 for the same effect? karl
44 /* direct is a special code space for built-in ram and SFR, 1K size */
45 #ifdef WORDS_BIGENDIAN
46 #define set_word_direct(_index, _value) { \
47 mem_direct[(_index)] = (_value >> 8); \
48 mem_direct[(_index)] = (_value & 0xff); }
50 #define get_word_direct(_index) \
51 ( (mem_direct[(_index)] << 8) | mem_direct[(_index)+1] )
53 #define set_word_direct(_index, _value) { \
54 wmem_direct[(_index) >> 1] = _value; }
55 #define get_word_direct(_index) (wmem_direct[(_index) >> 1] )
58 #define get_byte_direct(_index) (mem_direct[_index])
61 #define store2(addr, val) { ram->set((t_addr) (addr), val & 0xff); \
62 ram->set((t_addr) (addr+1), (val >> 8) & 0xff); }
63 #define store1(addr, val) ram->set((t_addr) (addr), val)
66 #define get1(addr) ram->get((t_addr) (addr))
67 #define get2(addr) (ram->get((t_addr) (addr)) | (ram->get((t_addr) (addr+1)) << 8) )
69 /* fetch from opcode code space */
70 #define fetch2() ((fetch() << 8) | fetch())
71 #define fetch1() fetch()
73 /* get a 1 or 2 byte register */
74 #define reg2(_index) get_reg(1, (_index))
75 #define reg1(_index) (unsigned char)get_reg(0, (_index))
77 #define set_byte_direct(_index, _value) { \
78 mem_direct[_index] = _value; \
81 #define set_reg1(_index, _value) { \
82 if ((_index) < 3) { /* banked */ \
83 mem_direct[0x400+(_index)] = _value; \
84 } else { /* non-banked */ \
85 mem_direct[0x400+(_index)] = _value; \
89 #define set_reg2(_index, _value) { \
90 if ((_index) < 3) { /* banked */ \
91 set_word_direct((0x400+_index), _value); \
92 } else { /* non-banked */ \
93 set_word_direct((0x400+_index), _value); \
97 #define set_reg(_word_flag, _index, _value) { \
99 { set_reg2((_index), _value) } \
101 { set_reg1((_index), _value) } \
104 /* R7 mirrors 1 of 2 real SP's */
105 #define set_sp(_value) { \
106 { set_word_direct(0x400+(7*2), _value); } \
109 #define get_sp() ((TYPE_UWORD)(get_word_direct(0x400+(7*2))))
111 // fixme: I don't know where the psw is kept, just want to compile...
112 #define get_psw() ((TYPE_UWORD)(get_word_direct(0x400+(0x80*2))))
113 #define set_psw(_flags) set_word_direct(0x400+(0x80*2), _flags)
116 --------------------------------------------------------------------
120 f: {unused slot(word accessable only) for R8-R15}
121 e: R7h,R7l Stack pointer, ptr to USP(PSW.SM=0), or SSP(PSW.SM=1)
125 below are the banked registers which mirror(B0..B3) depending on
132 Registers are all bit addressable as:
133 2: bx1f,bx1e...b8(R0h) bx17,bx16..bx10(R0l)
134 0: bxf,bxe...b8(R0h) b7,b6..b0(R0l)
136 Memory is little endian:
140 Data word access limited to word boundaries. If non-word address used,
141 then will act as lesser word alignment used(addr b0=0).
142 (note: trigger an exception in simulator if otherwise).
144 Internal memory takes precedence over external memory, unless
147 64K segment memory layout, bank registers used include:
148 DS(data segment) and ES(extra segment) and forms high byte of
149 24 bit address. Stack is in DS, so ES typically used to access
152 SFR(1K direct space) is above normal 1K direct address space(0-3FFH)
153 between 400H to 7FFH.
155 Branch targets must reside on even boundaries
156 (note: trigger an exception in simulator if otherwise).
158 MOVC instructions use either PC(SSEL.4=0) or CS(SSEL.4=1) register.
161 PCON, SCR, SSEL, PSWH, PSWL, CS, ES, DS
163 400H-43FH are bit or byte accesable.
164 400H-5FFH is for built in SFR hardware.
165 600H-7FFH is for external SFR hardware access.
166 SFR access is independent of segment regs.
167 SFR inacessable from indirect addressing(must use direct-addr in opcodes).
171 100H to 1ffH - 20h to 3fH(direct ram, relative to DS)
172 200H to 3FFH - 400H to 43FH(on board SFRs)
174 PSW Flags: Carry(C), Aux Carry(AC), Overflow(V), Negative(N), Zero(Z).
176 Stack ptr is pre-decremented, followed by load(word operation),
177 default SPs are set to 100H. So first PUSH would go to FEH-FFH.
188 #define BIT_ALL (BIT_C | BIT_AC | BIT_V | BIT_N | BIT_Z)
191 /* End of xa.src/regsxa.h */