2 * Simulator of microcontrollers (regsxa.h)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
32 //#define REGS_OFFSET 0x400
34 #ifndef REGSAVR_HEADER
35 #define REGSAVR_HEADER
44 /* macros suck, can we use inline functions instead
45 for the same effect? karl
48 /* direct is a special code space for built-in ram and SFR, 1K size */
49 #define set_word_direct(_index, _value) { \
50 mem_direct[(_index)+1] = (_value >> 8); \
51 mem_direct[(_index)] = (_value & 0xff); }
53 #define get_word_direct(_index) \
54 ( (mem_direct[(_index+1)] << 8) | mem_direct[(_index)] )
56 #define set_byte_direct(_index, _value) (mem_direct[_index] = _value)
57 #define get_byte_direct(_index) (mem_direct[_index])
60 #define store2(addr, val) { ram->set((t_addr) (addr), (val) & 0xff); \
61 ram->set((t_addr) (addr+1), ((val) >> 8) & 0xff); }
62 #define store1(addr, val) ram->set((t_addr) (addr), val)
65 #define get1(addr) ram->get((t_addr) (addr))
66 #define get2(addr) (ram->get((t_addr) (addr)) | (ram->get((t_addr) (addr+1)) << 8) )
69 #define getcode1(addr) rom->get((t_addr) (addr))
70 #define getcode2(addr) (rom->get((t_addr) (addr)) | (rom->get((t_addr) (addr+1)) << 8) )
72 /* fetch from opcode code space */
73 #define fetch2() ((fetch() << 8) | fetch())
74 #define fetch1() fetch()
76 /* get a 1 or 2 byte register */
77 #define reg2(_index) get_reg(1, (_index<<1)) /* function in inst.cc */
78 #define reg1(_index) (unsigned char)get_reg(0, (_index))
80 #define set_reg1(_index, _value) { \
81 if ((_index) < 3) { /* banked */ \
82 mem_direct[REGS_OFFSET+(_index)] = _value; \
83 } else { /* non-banked */ \
84 mem_direct[REGS_OFFSET+(_index)] = _value; \
88 #define set_reg2(_index, _value) { \
89 if ((_index) < 3) { /* banked */ \
90 set_word_direct((REGS_OFFSET+(_index<<1)), _value); \
91 } else { /* non-banked */ \
92 set_word_direct((REGS_OFFSET+(_index<<1)), _value); \
96 #define set_reg(_word_flag, _index, _value) { \
98 { set_reg2((_index), _value) } \
100 { set_reg1((_index), _value) } \
103 /* R7 mirrors 1 of 2 real SP's */
104 #define set_sp(_value) { \
105 { set_word_direct(REGS_OFFSET+(7*2), _value); } \
108 #define get_sp() ((TYPE_UWORD)(get_word_direct(REGS_OFFSET+(7*2))))
110 /* the program status word */
112 #define get_psw() ((TYPE_UWORD)(get_word_direct(PSW)))
113 #define set_psw(_flags) set_word_direct(PSW, _flags)
115 /* the system configuration register */
117 #define get_scr() get_byte_direct(SCR)
118 #define set_scr(scr) set_byte_direct(SCR, scr)
126 #define BIT_ALL (BIT_C | BIT_AC | BIT_V | BIT_N | BIT_Z)
130 --------------------------------------------------------------------
133 This user guide has got the detailed information on the XA chip.
135 http://www.semiconductors.philips.com/acrobat/various/XA_USER_GUIDE_1.pdf
138 f: {unused slot(word accessable only) for R8-R15}
139 e: R7h,R7l Stack pointer, ptr to USP(PSW.SM=0), or SSP(PSW.SM=1)
143 below are the banked registers which mirror(B0..B3) depending on
150 Registers are all bit addressable as:
151 2: bx1f,bx1e...b8(R0h) bx17,bx16..bx10(R0l)
152 0: bxf,bxe...b8(R0h) b7,b6..b0(R0l)
154 Memory is little endian:
158 Data word access limited to word boundaries. If non-word address used,
159 then will act as lesser word alignment used(addr b0=0).
160 (note: trigger an exception in simulator if otherwise).
162 Internal memory takes precedence over external memory, unless
165 64K segment memory layout, bank registers used include:
166 DS(data segment) and ES(extra segment) and forms high byte of
167 24 bit address. Stack is in DS, so ES typically used to access
170 SFR(1K direct space) is above normal 1K direct address space(0-3FFH)
171 between 400H to 7FFH.
173 Branch targets must reside on even boundaries
174 (note: trigger an exception in simulator if otherwise).
176 MOVC instructions use either PC(SSEL.4=0) or CS(SSEL.4=1) register.
179 PCON, SCR, SSEL, PSWH, PSWL, CS, ES, DS
181 400H-43FH are bit or byte accesable.
182 400H-5FFH is for built in SFR hardware.
183 600H-7FFH is for external SFR hardware access.
184 SFR access is independent of segment regs.
185 SFR inacessable from indirect addressing(must use direct-addr in opcodes).
189 100H to 1ffH - 20h to 3fH(direct ram, relative to DS)
190 200H to 3FFH - 400H to 43FH(on board SFRs)
192 PSW Flags: Carry(C), Aux Carry(AC), Overflow(V), Negative(N), Zero(Z).
194 Stack ptr is pre-decremented, followed by load(word operation),
195 default SPs are set to 100H. So first PUSH would go to FEH-FFH.
196 --------------------------------------------------------------------
201 /* End of xa.src/regsxa.h */