2 * Simulator of microcontrollers (inst_gen.cc)
3 * this code pulled into various parts
4 of inst.cc with FUNC1 and FUNC2 defined as
5 various operations to implement ADD, ADDC, ...
7 * Written by Karl Bongers karl@turbobit.com
9 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
11 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
15 /* This file is part of microcontroller simulator: ucsim.
17 UCSIM is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
22 UCSIM is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with UCSIM; see the file COPYING. If not, write to the Free
29 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
35 if (code & 0x0800) { /* word op */
37 FUNC2( reg2(RI_F0), reg2(RI_0F) )
41 FUNC1( reg1(RI_F0), reg1(RI_0F) )
48 short srcreg = reg2(RI_07);
49 if (code & 0x0800) { /* word op */
62 if (operands == REG_IREGINC) {
63 set_reg2(RI_07, srcreg+1);
70 short addr = reg2(RI_07);
71 if (code & 0x0800) { /* word op */
72 unsigned short wtmp, wtotal;
74 wtotal = FUNC2( wtmp, reg2(RI_F0) );
78 total = FUNC1( get1(addr), reg1(RI_F0) );
81 if (operands == IREGINC_REG) {
82 set_reg2(RI_07, addr+1);
91 if (operands == REG_IREGOFF8) {
92 offset = (int)((char) fetch());
94 offset = (int)((short)fetch2());
96 if (code & 0x0800) { /* word op */
97 t_mem addr = reg2(RI_70) + offset;
98 unsigned short wtmp, wtotal;
100 wtotal = FUNC2( wtmp, reg2(RI_F0) );
101 store2(addr, wtotal);
103 t_mem addr = reg2(RI_70) + ((short) fetch2());
105 total = FUNC1( get1(addr), reg1(RI_F0) );
115 if (operands == REG_IREGOFF8) {
116 offset = (int)((char) fetch());
118 offset = (int)((short)fetch2());
121 if (code & 0x0800) { /* word op */
124 get2(reg2(RI_07)+offset)
128 int offset = (int)((short)fetch2());
131 get1(reg2(RI_07)+offset)
140 int addr = ((code & 0x7) << 8) | fetch();
141 if (code & 0x0800) { /* word op */
142 unsigned short wtmp = get_word_direct(addr);
143 set_word_direct( addr,
144 FUNC2( wtmp, reg2(RI_F0) )
147 unsigned char tmp = get_byte_direct(addr);
148 set_byte_direct( addr,
149 FUNC1( tmp, reg1(RI_F0) )
157 int addr = ((code & 0x7) << 8) | fetch();
158 if (code & 0x0800) { /* word op */
161 get_word_direct(addr)
167 get_byte_direct(addr)
175 set_reg1( RI_F0, FUNC1( reg1(RI_F0), fetch()) );
179 set_reg2( RI_F0, FUNC2( reg2(RI_F0), fetch2()) );
187 t_mem addr = reg2(RI_70);
189 total = FUNC1(tmp, fetch() );
191 if (operands == IREGINC_DATA8) {
192 set_reg2(RI_70, addr+1);
197 case IREGINC_DATA16 :
200 unsigned short total;
202 t_mem addr = reg2(RI_70);
204 total = FUNC2(tmp, fetch2() );
206 if (operands == IREGINC_DATA16) {
207 set_reg2(RI_70, addr+1);
212 case IREGOFF8_DATA8 :
213 case IREGOFF16_DATA8 :
218 if (operands == IREGOFF8_DATA8) {
219 offset = (int)((char) fetch());
221 offset = (int)((short)fetch2());
234 case IREGOFF8_DATA16 :
235 case IREGOFF16_DATA16 :
240 if (operands == IREGOFF8_DATA16) {
241 offset = (int)((char) fetch());
243 offset = (int)((short)fetch2());
258 int addr = ((code & 0x70) << 4) | fetch();
259 unsigned char bdir = get_byte_direct(addr);
260 unsigned char bdat = fetch();
261 set_byte_direct( addr, FUNC1( bdir, bdat) );
267 int addr = ((code & 0x70) << 4) | fetch();
268 unsigned short wdir = get_word_direct(addr);
269 unsigned short wdat = fetch2();
270 set_word_direct( addr, FUNC2( wdir, wdat) );