2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * Written by Karl Bongers karl@turbobit.com
8 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
12 /* This file is part of microcontroller simulator: ucsim.
14 UCSIM is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 UCSIM is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with UCSIM; see the file COPYING. If not, write to the Free
26 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 cl_xa::get_reg(int word_flag, unsigned int index)
40 //if (index < 3) { /* banked */
42 // return get_word_direct(0x400+index);
44 // return mem_direct[0x400+index];
45 //} else { /* non-banked */
47 return get_word_direct(0x400+index);
49 return mem_direct[0x400+index];
54 cl_xa::inst_NOP(uint code, int operands)
59 #define RI_F0 ((code >> 4) & 0xf)
60 #define RI_70 ((code >> 4) & 0x7)
61 #define RI_0F (code & 0xf)
62 #define RI_07 (code & 0x7)
65 cl_xa::inst_ADD(uint code, int operands)
71 #include "inst_gen.cc"
77 cl_xa::inst_ADDC(uint code, int operands)
83 #include "inst_gen.cc"
89 cl_xa::inst_SUB(uint code, int operands)
95 #include "inst_gen.cc"
100 cl_xa::inst_SUBB(uint code, int operands)
106 #include "inst_gen.cc"
111 cl_xa::inst_CMP(uint code, int operands)
117 #include "inst_gen.cc"
121 cl_xa::inst_AND(uint code, int operands)
127 #include "inst_gen.cc"
131 cl_xa::inst_OR(uint code, int operands)
137 #include "inst_gen.cc"
141 cl_xa::inst_XOR(uint code, int operands)
147 #include "inst_gen.cc"
151 cl_xa::inst_ADDS(uint code, int operands)
156 cl_xa::inst_NEG(uint code, int operands)
161 cl_xa::inst_SEXT(uint code, int operands)
166 cl_xa::inst_MUL(uint code, int operands)
171 cl_xa::inst_DIV(uint code, int operands)
176 cl_xa::inst_DA(uint code, int operands)
181 cl_xa::inst_ASL(uint code, int operands)
186 cl_xa::inst_ASR(uint code, int operands)
191 cl_xa::inst_LEA(uint code, int operands)
196 cl_xa::inst_CPL(uint code, int operands)
201 cl_xa::inst_LSR(uint code, int operands)
206 cl_xa::inst_NORM(uint code, int operands)
211 cl_xa::inst_RL(uint code, int operands)
216 cl_xa::inst_RLC(uint code, int operands)
221 cl_xa::inst_RR(uint code, int operands)
226 cl_xa::inst_RRC(uint code, int operands)
231 cl_xa::inst_MOVS(uint code, int operands)
236 cl_xa::inst_MOVC(uint code, int operands)
241 short srcreg = reg2(RI_07);
242 if (code & 0x0800) { /* word op */
255 if (operands == REG_IREGINC) {
256 set_reg2(RI_07, srcreg+1);
265 cl_xa::inst_MOVX(uint code, int operands)
270 cl_xa::inst_PUSH(uint code, int operands)
276 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
280 if (code & 0x0800) { /* word op */
281 store2( sp, get_word_direct(direct_addr));
283 store2( sp, get_byte_direct(direct_addr));
290 unsigned char rlist = fetch();
291 rlist = rlist; //shutup compiler
298 cl_xa::inst_POP(uint code, int operands)
304 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
307 if (code & 0x0800) { /* word op */
308 set_word_direct(direct_addr, get2(sp) );
310 set_byte_direct(direct_addr, get2(sp) & 0xff );
318 unsigned char rlist = fetch();
319 rlist = rlist; //shutup compiler
325 cl_xa::inst_XCH(uint code, int operands)
330 cl_xa::inst_SETB(uint code, int operands)
335 cl_xa::inst_CLR(uint code, int operands)
340 cl_xa::inst_MOV(uint code, int operands)
346 #include "inst_gen.cc"
350 cl_xa::inst_ANL(uint code, int operands)
355 cl_xa::inst_ORL(uint code, int operands)
360 cl_xa::inst_BR(uint code, int operands)
365 cl_xa::inst_JMP(uint code, int operands)
367 unsigned int jmpaddr;
376 PC = (PC + jmpaddr) & 0xfffffffe;
381 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
383 /* fixme 2 more... */
388 cl_xa::inst_CALL(uint code, int operands)
390 unsigned int jmpaddr;
400 store2(sp+2, 0); /* segment(not sure about ordering...) */
402 PC = (PC + jmpaddr) & 0xfffffffe;
410 store2(sp+2, 0); /* segment(not sure about ordering...) */
411 jmpaddr = reg2(RI_07);
413 PC = (PC + jmpaddr) & 0xfffffffe;
416 /* fixme 2 more... */
421 cl_xa::inst_RET(uint code, int operands)
423 unsigned int retaddr;
427 //retaddr |= get2(sp+2) << 16);
432 cl_xa::inst_Bcc(uint code, int operands)
437 cl_xa::inst_JB(uint code, int operands)
442 cl_xa::inst_JNB(uint code, int operands)
447 cl_xa::inst_CJNE(uint code, int operands)
452 cl_xa::inst_DJNZ(uint code, int operands)
457 cl_xa::inst_JZ(uint code, int operands)
459 short saddr = (fetch1() * 2);
460 if (get_psw() & BIT_Z) {
466 cl_xa::inst_JNZ(uint code, int operands)
468 short saddr = (fetch1() * 2);
469 if (!(get_psw() & BIT_Z)) {
475 cl_xa::inst_BKPT(uint code, int operands)
480 cl_xa::inst_TRAP(uint code, int operands)
485 cl_xa::inst_RESET(uint code, int operands)
491 /* End of xa.src/inst.cc */