2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 int cl_xa::get_reg(int word_flag, unsigned int index)
43 result = get_word_direct(index);
46 result = get_byte_direct(index);
51 bool cl_xa::get_bit(int bit) {
60 result = get_byte_direct(offset + (bit/8)) & (1 << (bit%8));
62 //return mem_direct[offset + (bit/8)] & (1 << (bit%8));
65 void cl_xa::set_bit(int bit, int value) {
74 i = get_byte_direct(offset + (bit/8));
76 set_byte_direct(offset + (bit/8), i | (1 << (bit%8)) );
77 //mem_direct[offset + (bit/8)] |= (1 << (bit%8));
79 set_byte_direct(offset + (bit/8), i & ~(1 << (bit%8)) );
80 //mem_direct[offset + (bit/8)] &= ~(1 << (bit%8));
84 #define RI_F0 ((code >> 4) & 0xf)
85 #define RI_70 ((code >> 4) & 0x7)
86 #define RI_0F (code & 0xf)
87 #define RI_07 (code & 0x7)
89 int cl_xa::inst_ADD(uint code, int operands)
95 #include "inst_gen.cc"
100 int cl_xa::inst_ADDC(uint code, int operands)
106 #include "inst_gen.cc"
111 int cl_xa::inst_ADDS(uint code, int operands)
116 int cl_xa::inst_AND(uint code, int operands)
122 #include "inst_gen.cc"
126 int cl_xa::inst_ANL(uint code, int operands)
131 int cl_xa::inst_ASL(uint code, int operands)
136 int cl_xa::inst_ASR(uint code, int operands)
141 int cl_xa::inst_BCC(uint code, int operands)
146 int cl_xa::inst_BCS(uint code, int operands)
151 int cl_xa::inst_BEQ(uint code, int operands)
153 short jmpAddr = fetch1()*2;
154 if (get_psw() & BIT_Z) {
155 PC=(PC+jmpAddr)&0xfffffffe;
160 int cl_xa::inst_BG(uint code, int operands)
164 int cl_xa::inst_BGE(uint code, int operands)
168 int cl_xa::inst_BGT(uint code, int operands)
172 int cl_xa::inst_BKPT(uint code, int operands)
176 int cl_xa::inst_BL(uint code, int operands)
180 int cl_xa::inst_BLE(uint code, int operands)
184 int cl_xa::inst_BLT(uint code, int operands)
188 int cl_xa::inst_BMI(uint code, int operands)
192 int cl_xa::inst_BNE(uint code, int operands)
196 int cl_xa::inst_BNV(uint code, int operands)
200 int cl_xa::inst_BOV(uint code, int operands)
204 int cl_xa::inst_BPL(uint code, int operands)
209 int cl_xa::inst_BR(uint code, int operands)
211 short jmpAddr = fetch1()*2;
212 PC=(PC+jmpAddr)&0xfffffe;
216 int cl_xa::inst_CALL(uint code, int operands)
220 bool pageZero=get_scr()&1;
225 jmpaddr = (signed short)fetch2();
226 sp = get_sp() - (pageZero ? 2 : 4);
228 store2(sp, PC&0xffff);
230 store2(sp+2, (PC>>16)&0xff);
233 PC = (PC + jmpaddr) & 0xfffffe;
238 sp = get_sp() - (pageZero ? 2 : 4);
240 store2(sp, PC&0xffff);
242 store2(sp+2, (PC>>16)&0xff);
244 jmpaddr = reg2(RI_07);
246 PC = (PC + jmpaddr) & 0xfffffe;
253 int cl_xa::inst_CJNE(uint code, int operands)
256 case REG_DIRECT_REL8:
259 if (code & 0x800) { // word op
261 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
262 int addr = (fetch1() * 2);
263 int dst = reg2(RI_F0);
266 flags &= ~BIT_ALL; /* clear these bits */
268 if (result == 0) flags |= BIT_Z;
269 if (result > 0xffff) flags |= BIT_C;
270 if (dst < src) flags |= BIT_N;
276 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
277 int addr = (fetch1() * 2);
278 int dst = reg1(RI_F0);
281 flags &= ~BIT_ALL; /* clear these bits */
283 if (result == 0) flags |= BIT_Z;
284 if (result > 0xff) flags |= BIT_C;
285 if (dst < src) flags |= BIT_N;
295 int daddr = ((code & 0x7) << 8) | fetch();
296 int addr = fetch() * 2;
298 if (code & 0x800) { // word op
299 unsigned short tmp = get_word_direct(daddr)-1;
300 set_word_direct(daddr, tmp);
304 unsigned char tmp = get_word_direct(daddr)-1;
305 set_byte_direct(daddr, tmp);
315 int cl_xa::inst_CLR(uint code, int operands)
317 unsigned short bitAddr = (code&0x03 << 8) + fetch();
323 int cl_xa::inst_CMP(uint code, int operands)
329 #include "inst_gen.cc"
332 int cl_xa::inst_CPL(uint code, int operands)
336 int cl_xa::inst_DA(uint code, int operands)
340 int cl_xa::inst_DIV(uint code, int operands)
345 int cl_xa::inst_DJNZ(uint code, int operands)
351 int addr = ( ((char)fetch1()) * 2);
352 if (code & 0x800) { // word op
353 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
354 set_reg2(RI_F0, tmp);
356 PC = (PC + addr) & 0xfffffe;
358 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
359 set_reg1(RI_F0, tmp);
361 PC = (PC + addr) & 0xfffffe;
368 int daddr = ((code & 0x7) << 8) | fetch();
369 int addr = fetch() * 2;
371 if (code & 0x800) { // word op
372 unsigned short tmp = get_word_direct(daddr)-1;
373 set_word_direct(daddr, tmp);
377 unsigned char tmp = get_word_direct(daddr)-1;
378 set_byte_direct(daddr, tmp);
389 int cl_xa::inst_FCALL(uint code, int operands)
394 int cl_xa::inst_FJMP(uint code, int operands)
399 int cl_xa::inst_JB(uint code, int operands)
401 short bitAddr=((code&0x3)<<8) + fetch1();
402 short jmpAddr = (fetch1() * 2);
403 if (get_bit(bitAddr)) {
404 PC = (PC+jmpAddr)&0xfffffe;
408 int cl_xa::inst_JBC(uint code, int operands)
412 int cl_xa::inst_JNB(uint code, int operands)
414 short bitAddr=((code&0x3)<<8) + fetch1();
415 short jmpAddr = (fetch1() * 2);
416 if (!get_bit(bitAddr)) {
417 PC = (PC+jmpAddr)&0xfffffe;
422 int cl_xa::inst_JMP(uint code, int operands)
429 jmpAddr = (signed short)fetch2()*2;
430 PC = (PC + jmpAddr) & 0xfffffe;
435 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
437 /* fixme 2 more... */
441 int cl_xa::inst_JNZ(uint code, int operands)
443 short saddr = (fetch1() * 2);
444 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
446 PC = (PC + saddr) & 0xfffffe;
450 int cl_xa::inst_JZ(uint code, int operands)
452 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
453 short saddr = (fetch1() * 2);
459 int cl_xa::inst_LEA(uint code, int operands)
463 int cl_xa::inst_LSR(uint code, int operands)
467 int cl_xa::inst_MOV(uint code, int operands)
473 #include "inst_gen.cc"
476 int cl_xa::inst_MOVC(uint code, int operands)
481 short srcreg = reg2(RI_07);
482 if (code & 0x0800) { /* word op */
495 if (operands == REG_IREGINC) {
496 set_reg2(RI_07, srcreg+1);
501 { /* R4l=ACC, R6=DPTR */
502 unsigned int addr = (PC & 0xff0000) | (reg1(4) + reg2(6));
503 unsigned short result;
507 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
508 result = getcode1(addr);
509 set_reg1( 4, result);
510 if (result == 0) flags |= BIT_Z;
511 if (result & 0x80) flags |= BIT_N;
516 { /* R4l=ACC, R6=DPTR */
517 unsigned int addr = (PC + reg1(4));
518 unsigned short result;
522 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
523 result = getcode1(addr);
524 set_reg1( 4, result);
525 if (result == 0) flags |= BIT_Z;
526 if (result & 0x80) flags |= BIT_N;
533 int cl_xa::inst_MOVS(uint code, int operands)
537 int cl_xa::inst_MOVX(uint code, int operands)
541 int cl_xa::inst_MUL(uint code, int operands)
545 int cl_xa::inst_NEG(uint code, int operands)
549 int cl_xa::inst_NOP(uint code, int operands)
553 int cl_xa::inst_NORM(uint code, int operands)
557 int cl_xa::inst_OR(uint code, int operands)
563 #include "inst_gen.cc"
567 int cl_xa::inst_ORL(uint code, int operands)
572 int cl_xa::inst_POP(uint code, int operands)
578 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
581 if (code & 0x0800) { /* word op */
582 set_word_direct(direct_addr, get2(sp) );
584 set_byte_direct(direct_addr, get2(sp) & 0xff );
592 unsigned char rlist = fetch();
593 rlist = rlist; //shutup compiler
599 int cl_xa::inst_PUSH(uint code, int operands)
605 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
609 if (code & 0x0800) { /* word op */
610 store2( sp, get_word_direct(direct_addr));
612 store2( sp, get_byte_direct(direct_addr));
619 unsigned char rlist = fetch();
620 rlist = rlist; //shutup compiler
626 int cl_xa::inst_RESET(uint code, int operands)
630 int cl_xa::inst_RET(uint code, int operands)
632 unsigned int retaddr;
634 bool pageZero=get_scr()&1;
639 retaddr |= get2(sp+2) << 16;
647 int cl_xa::inst_RETI(uint code, int operands)
649 unsigned int retaddr;
651 bool pageZero=get_scr()&1;
655 retaddr = get2(sp+2);
657 retaddr |= get2(sp+4) << 16;
665 int cl_xa::inst_RL(uint code, int operands)
669 int cl_xa::inst_RLC(uint code, int operands)
673 int cl_xa::inst_RR(uint code, int operands)
677 int cl_xa::inst_RRC(uint code, int operands)
681 int cl_xa::inst_SETB(uint code, int operands)
683 unsigned short bitAddr = (code&0x03 << 8) + fetch();
689 int cl_xa::inst_SEXT(uint code, int operands)
694 int cl_xa::inst_SUB(uint code, int operands)
700 #include "inst_gen.cc"
704 int cl_xa::inst_SUBB(uint code, int operands)
710 #include "inst_gen.cc"
713 int cl_xa::inst_TRAP(uint code, int operands)
717 int cl_xa::inst_XCH(uint code, int operands)
721 int cl_xa::inst_XOR(uint code, int operands)
727 #include "inst_gen.cc"
731 /* End of xa.src/inst.cc */