2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
9 * Johan Knol johan.knol@iduna.nl
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
40 #define NOTDONE_ASSERT { printf("**********Instr not done at %d!\n", __LINE__); }
42 void cl_xa::store1(t_addr addr, unsigned char val)
45 set_idata1(addr, val);
47 set_xdata1(addr, val);
51 void cl_xa::store2(t_addr addr, unsigned short val)
54 set_idata2(addr, val);
56 set_xdata2(addr, val);
60 unsigned char cl_xa::get1(t_addr addr)
63 return get_idata1(addr);
65 return get_xdata1(addr);
69 unsigned short cl_xa::get2(t_addr addr)
72 return get_idata2(addr);
74 return get_xdata2(addr);
78 int cl_xa::get_reg(int word_flag, unsigned int index)
83 result = get_word_direct(index);
86 result = get_byte_direct(index);
91 bool cl_xa::get_bit(int bit) {
100 result = get_byte_direct(offset + (bit/8)) & (1 << (bit%8));
104 void cl_xa::set_bit(int bit, int value) {
113 i = get_byte_direct(offset + (bit/8));
115 set_byte_direct(offset + (bit/8), i | (1 << (bit%8)) );
117 set_byte_direct(offset + (bit/8), i & ~(1 << (bit%8)) );
121 #define RI_F0 ((code >> 4) & 0xf)
122 #define RI_70 ((code >> 4) & 0x7)
123 #define RI_0F (code & 0xf)
124 #define RI_07 (code & 0x7)
126 int cl_xa::inst_ADD(uint code, int operands)
132 #include "inst_gen.cc"
137 int cl_xa::inst_ADDC(uint code, int operands)
143 #include "inst_gen.cc"
148 int cl_xa::inst_ADDS(uint code, int operands)
154 int cl_xa::inst_AND(uint code, int operands)
160 #include "inst_gen.cc"
164 /* logical AND bit with Carry flag */
165 int cl_xa::inst_ANL(uint code, int operands)
168 unsigned short bitAddr = (code&0x03 << 8) + fetch();
172 /* have work to do */
175 if (!get_bit(bitAddr)) {
176 set_psw(flags & ~BIT_C);
181 if (get_bit(bitAddr)) {
182 set_psw(flags & ~BIT_C);
191 /* arithmetic shift left */
192 int cl_xa::inst_ASL(uint code, int operands)
194 unsigned int dst, cnt;
199 C = dest.80H; dest <<= 1; if sign chg then set V=1
200 this is a confusing one...
204 flags &= ~BIT_ALL; /* clear these bits */
207 //{0,0xc150,0xf300,' ',2,ASL, REG_REG }, // ASL Rd, Rs 1 1 0 0 S S 0 1 d d d d s s s s
209 cnt = reg1(RI_0F) & 0x1f;
210 switch (code & 0xc00) {
217 if ((dst & 0xff) == 0)
226 if ((dst & 0xffff) == 0)
230 // not really sure about the encoding here..
235 dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
236 if ((cnt != 0) && (dst & (0x80000000 >> (cnt-1)))) {
240 set_reg2(RI_F0,dst & 0xffff);
241 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
250 switch (code & 0xc00) {
253 cnt = operands & 0x0f;
258 if ((dst & 0xff) == 0)
263 cnt = operands & 0x0f;
268 if ((dst & 0xffff) == 0)
272 // not really sure about the encoding here..
276 dst = reg1(RI_F0 & 0xe);
277 cnt = operands & 0x1f;
278 if ((cnt != 0) && (dst & (0x80000000 >> (cnt-1)))) {
282 set_reg2(RI_F0,dst & 0xffff);
283 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
295 /* arithmetic shift right */
296 int cl_xa::inst_ASR(uint code, int operands)
298 unsigned int dst, cnt;
303 C = dest.0; dest >>= 1;
304 this is a confusing one...
308 flags &= ~BIT_ALL; /* clear these bits */
312 cnt = reg1(RI_0F) & 0x1f;
313 switch (code & 0xc00) {
316 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
322 if ((dst & 0xff) == 0)
327 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
331 if ((dst & 0xffff) == 0)
335 // not really sure about the encoding here..
339 dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
340 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
343 set_reg2(RI_F0,dst & 0xffff);
344 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
353 switch (code & 0xc00) {
356 cnt = operands & 0x0f;
357 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
361 if ((dst & 0xff) == 0)
366 cnt = operands & 0x0f;
367 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
371 if ((dst & 0xffff) == 0)
375 // not really sure about the encoding here..
379 dst = reg1(RI_F0 & 0xe);
380 cnt = operands & 0x1f;
381 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
384 set_reg2(RI_F0,dst & 0xffff);
385 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
397 int cl_xa::inst_BCC(uint code, int operands)
399 short jmpAddr = fetch1()*2;
400 if (!(get_psw() & BIT_C)) {
401 PC=(PC+jmpAddr)&0xfffffe;
406 int cl_xa::inst_BCS(uint code, int operands)
408 short jmpAddr = fetch1()*2;
409 if (get_psw() & BIT_C) {
410 PC=(PC+jmpAddr)&0xfffffe;
415 int cl_xa::inst_BEQ(uint code, int operands)
417 short jmpAddr = fetch1()*2;
418 if (get_psw() & BIT_Z) {
419 PC=(PC+jmpAddr)&0xfffffe;
424 int cl_xa::inst_BG(uint code, int operands)
426 short jmpAddr = fetch1()*2;
427 short flags=get_psw();
428 bool Z=flags&BIT_Z, C=flags&BIT_C;
430 PC=(PC+jmpAddr)&0xfffffe;
434 int cl_xa::inst_BGE(uint code, int operands)
436 short jmpAddr = fetch1()*2;
437 short flags=get_psw();
438 bool N=flags&BIT_N, V=flags&BIT_V;
440 PC=(PC+jmpAddr)&0xfffffe;
444 int cl_xa::inst_BGT(uint code, int operands)
446 short jmpAddr = fetch1()*2;
447 short flags=get_psw();
448 bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
450 PC=(PC+jmpAddr)&0xfffffe;
454 int cl_xa::inst_BKPT(uint code, int operands)
459 int cl_xa::inst_BL(uint code, int operands)
461 short jmpAddr = fetch1()*2;
462 short flags=get_psw();
463 bool Z=flags&BIT_Z, C=flags&BIT_C;
465 PC=(PC+jmpAddr)&0xfffffe;
469 int cl_xa::inst_BLE(uint code, int operands)
471 short jmpAddr = fetch1()*2;
472 short flags=get_psw();
473 bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
475 PC=(PC+jmpAddr)&0xfffffe;
479 int cl_xa::inst_BLT(uint code, int operands)
481 short jmpAddr = fetch1()*2;
482 short flags=get_psw();
483 bool N=flags&BIT_N, V=flags&BIT_V;
485 PC=(PC+jmpAddr)&0xfffffe;
489 int cl_xa::inst_BMI(uint code, int operands)
491 short jmpAddr = fetch1()*2;
492 if (get_psw()&BIT_N) {
493 PC=(PC+jmpAddr)&0xfffffe;
497 int cl_xa::inst_BNE(uint code, int operands)
499 short jmpAddr = fetch1()*2;
500 if (!(get_psw()&BIT_Z)) {
501 PC=(PC+jmpAddr)&0xfffffe;
505 int cl_xa::inst_BNV(uint code, int operands)
507 short jmpAddr = fetch1()*2;
508 if (!(get_psw()&BIT_V)) {
509 PC=(PC+jmpAddr)&0xfffffe;
513 int cl_xa::inst_BOV(uint code, int operands)
515 short jmpAddr = fetch1()*2;
516 if (get_psw()&BIT_V) {
517 PC=(PC+jmpAddr)&0xfffffe;
521 int cl_xa::inst_BPL(uint code, int operands)
523 short jmpAddr = fetch1()*2;
524 if (!(get_psw()&BIT_N)) {
525 PC=(PC+jmpAddr)&0xfffffe;
530 int cl_xa::inst_BR(uint code, int operands)
532 short jmpAddr = fetch1()*2;
533 PC=(PC+jmpAddr)&0xfffffe;
537 int cl_xa::inst_CALL(uint code, int operands)
541 bool pageZero=get_scr()&1;
546 jmpaddr = (signed short)fetch2();
547 sp = get_sp() - (pageZero ? 2 : 4);
549 store2(sp, PC&0xffff);
551 store2(sp+2, (PC>>16)&0xff);
554 PC = (PC + jmpaddr) & 0xfffffe;
559 sp = get_sp() - (pageZero ? 2 : 4);
561 store2(sp, PC&0xffff);
563 store2(sp+2, (PC>>16)&0xff);
565 jmpaddr = reg2(RI_07);
567 PC = (PC + jmpaddr) & 0xfffffe;
574 int cl_xa::inst_CJNE(uint code, int operands)
577 case REG_DIRECT_REL8:
580 if (code & 0x800) { // word op
582 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
583 int addr = (fetch1() * 2);
584 int dst = reg2(RI_F0);
587 flags &= ~BIT_ALL; /* clear these bits */
589 if (result == 0) flags |= BIT_Z;
590 if (result > 0xffff) flags |= BIT_C;
591 if (dst < src) flags |= BIT_N;
597 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
598 int addr = (fetch1() * 2);
599 int dst = reg1(RI_F0);
602 flags &= ~BIT_ALL; /* clear these bits */
604 if (result == 0) flags |= BIT_Z;
605 if (result > 0xff) flags |= BIT_C;
606 if (dst < src) flags |= BIT_N;
616 int daddr = ((code & 0x7) << 8) | fetch();
617 int addr = fetch() * 2;
619 if (code & 0x800) { // word op
620 unsigned short tmp = get_word_direct(daddr)-1;
621 set_word_direct(daddr, tmp);
625 unsigned char tmp = get_word_direct(daddr)-1;
626 set_byte_direct(daddr, tmp);
636 int cl_xa::inst_CLR(uint code, int operands)
638 unsigned short bitAddr = (code&0x03 << 8) + fetch();
639 set_bit (bitAddr, 0);
643 int cl_xa::inst_CMP(uint code, int operands)
649 #include "inst_gen.cc"
652 int cl_xa::inst_CPL(uint code, int operands)
657 int cl_xa::inst_DA(uint code, int operands)
662 int cl_xa::inst_DIV(uint code, int operands)
668 int cl_xa::inst_DJNZ(uint code, int operands)
674 int addr = ( ((char)fetch1()) * 2);
675 if (code & 0x800) { // word op
676 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
677 set_reg2(RI_F0, tmp);
679 PC = (PC + addr) & 0xfffffe;
681 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
682 set_reg1(RI_F0, tmp);
684 PC = (PC + addr) & 0xfffffe;
691 int daddr = ((code & 0x7) << 8) | fetch();
692 int addr = fetch() * 2;
694 if (code & 0x800) { // word op
695 unsigned short tmp = get_word_direct(daddr)-1;
696 set_word_direct(daddr, tmp);
700 unsigned char tmp = get_word_direct(daddr)-1;
701 set_byte_direct(daddr, tmp);
712 int cl_xa::inst_FCALL(uint code, int operands)
718 int cl_xa::inst_FJMP(uint code, int operands)
724 int cl_xa::inst_JB(uint code, int operands)
726 short bitAddr=((code&0x3)<<8) + fetch1();
727 short jmpAddr = (fetch1() * 2);
728 if (get_bit(bitAddr)) {
729 PC = (PC+jmpAddr)&0xfffffe;
733 int cl_xa::inst_JBC(uint code, int operands)
735 short bitAddr=((code&0x3)<<8) + fetch1();
736 short jmpAddr = (fetch1() * 2);
737 if (get_bit(bitAddr)) {
738 PC = (PC+jmpAddr)&0xfffffe;
743 int cl_xa::inst_JNB(uint code, int operands)
745 short bitAddr=((code&0x3)<<8) + fetch1();
746 short jmpAddr = (fetch1() * 2);
747 if (!get_bit(bitAddr)) {
748 PC = (PC+jmpAddr)&0xfffffe;
752 int cl_xa::inst_JMP(uint code, int operands)
759 jmpAddr = (signed short)fetch2()*2;
760 PC = (PC + jmpAddr) & 0xfffffe;
765 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
767 /* fixme 2 more... */
771 int cl_xa::inst_JNZ(uint code, int operands)
773 short saddr = (fetch1() * 2);
774 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
776 PC = (PC + saddr) & 0xfffffe;
780 int cl_xa::inst_JZ(uint code, int operands)
782 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
783 short saddr = (fetch1() * 2);
789 int cl_xa::inst_LEA(uint code, int operands)
794 char offset=fetch1();
795 set_reg2(RI_70, reg2(RI_07)+offset);
800 short offset=fetch2();
801 set_reg2(RI_70, reg2(RI_07)+offset);
807 int cl_xa::inst_LSR(uint code, int operands)
812 int cl_xa::inst_MOV(uint code, int operands)
818 #include "inst_gen.cc"
821 int cl_xa::inst_MOVC(uint code, int operands)
826 short srcreg = reg2(RI_07);
827 if (code & 0x0800) { /* word op */
840 if (operands == REG_IREGINC) {
841 set_reg2(RI_07, srcreg+1);
846 { /* R4l=ACC, R6=DPTR */
847 unsigned int addr = (PC & 0xff0000) | (reg1(4) + reg2(6));
848 unsigned short result;
852 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
853 result = getcode1(addr);
854 set_reg1( 4, result);
855 if (result == 0) flags |= BIT_Z;
856 if (result & 0x80) flags |= BIT_N;
861 { /* R4l=ACC, R6=DPTR */
862 unsigned int addr = (PC + reg1(4));
863 unsigned short result;
867 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
868 result = getcode1(addr);
869 set_reg1( 4, result);
870 if (result == 0) flags |= BIT_Z;
871 if (result & 0x80) flags |= BIT_N;
878 int cl_xa::inst_MOVS(uint code, int operands)
883 int cl_xa::inst_MOVX(uint code, int operands)
888 int cl_xa::inst_MUL(uint code, int operands)
893 int cl_xa::inst_NEG(uint code, int operands)
898 int cl_xa::inst_NOP(uint code, int operands)
902 int cl_xa::inst_NORM(uint code, int operands)
907 int cl_xa::inst_OR(uint code, int operands)
913 #include "inst_gen.cc"
917 int cl_xa::inst_ORL(uint code, int operands)
923 int cl_xa::inst_POP(uint code, int operands)
925 unsigned short sp=get_sp();
929 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
931 if (code & 0x0800) { /* word op */
932 set_word_direct(direct_addr, get2(sp) );
934 set_byte_direct(direct_addr, get2(sp) & 0xff );
942 unsigned char rlist = fetch();
943 if (code & 0x0800) { // word op
944 if (code & 0x4000) { // R8-R15
945 if (rlist&0x01) { set_reg2(8, get2(sp)); sp+=2; }
946 if (rlist&0x02) { set_reg2(9, get2(sp)); sp+=2; }
947 if (rlist&0x04) { set_reg2(10, get2(sp)); sp+=2; }
948 if (rlist&0x08) { set_reg2(11, get2(sp)); sp+=2; }
949 if (rlist&0x10) { set_reg2(12, get2(sp)); sp+=2; }
950 if (rlist&0x20) { set_reg2(13, get2(sp)); sp+=2; }
951 if (rlist&0x40) { set_reg2(14, get2(sp)); sp+=2; }
952 if (rlist&0x80) { set_reg2(15, get2(sp)); sp+=2; }
954 if (rlist&0x01) { set_reg2(0, get2(sp)); sp+=2; }
955 if (rlist&0x02) { set_reg2(1, get2(sp)); sp+=2; }
956 if (rlist&0x04) { set_reg2(2, get2(sp)); sp+=2; }
957 if (rlist&0x08) { set_reg2(3, get2(sp)); sp+=2; }
958 if (rlist&0x10) { set_reg2(4, get2(sp)); sp+=2; }
959 if (rlist&0x20) { set_reg2(5, get2(sp)); sp+=2; }
960 if (rlist&0x40) { set_reg2(6, get2(sp)); sp+=2; }
961 if (rlist&0x80) { set_reg2(7, get2(sp)); sp+=2; }
964 if (code & 0x4000) { // R4l-R7h
965 if (rlist&0x01) { set_reg1(8, get1(sp)); sp+=2; }
966 if (rlist&0x02) { set_reg1(9, get1(sp)); sp+=2; }
967 if (rlist&0x04) { set_reg1(10, get1(sp)); sp+=2; }
968 if (rlist&0x08) { set_reg1(11, get1(sp)); sp+=2; }
969 if (rlist&0x10) { set_reg1(12, get1(sp)); sp+=2; }
970 if (rlist&0x20) { set_reg1(13, get1(sp)); sp+=2; }
971 if (rlist&0x40) { set_reg1(14, get1(sp)); sp+=2; }
972 if (rlist&0x80) { set_reg1(15, get1(sp)); sp+=2; }
974 if (rlist&0x01) { set_reg1(0, get1(sp)); sp+=2; }
975 if (rlist&0x02) { set_reg1(1, get1(sp)); sp+=2; }
976 if (rlist&0x04) { set_reg1(2, get1(sp)); sp+=2; }
977 if (rlist&0x08) { set_reg1(3, get1(sp)); sp+=2; }
978 if (rlist&0x10) { set_reg1(4, get1(sp)); sp+=2; }
979 if (rlist&0x20) { set_reg1(5, get1(sp)); sp+=2; }
980 if (rlist&0x40) { set_reg1(6, get1(sp)); sp+=2; }
981 if (rlist&0x80) { set_reg1(7, get1(sp)); sp+=2; }
990 int cl_xa::inst_PUSH(uint code, int operands)
996 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
1000 if (code & 0x0800) { /* word op */
1001 store2( sp, get_word_direct(direct_addr));
1003 store2( sp, get_byte_direct(direct_addr));
1010 unsigned short sp=get_sp();
1011 unsigned char rlist = fetch();
1012 if (code & 0x0800) { // word op
1013 if (code & 0x4000) { // R15-R8
1014 if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
1015 if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
1016 if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
1017 if (rlist&0x10) { sp-=2; store2(sp, reg2(12)); }
1018 if (rlist&0x08) { sp-=2; store2(sp, reg2(11)); }
1019 if (rlist&0x04) { sp-=2; store2(sp, reg2(10)); }
1020 if (rlist&0x02) { sp-=2; store2(sp, reg2(9)); }
1021 if (rlist&0x01) { sp-=2; store2(sp, reg2(8)); }
1023 if (rlist&0x80) { sp-=2; store2(sp, reg2(7)); }
1024 if (rlist&0x40) { sp-=2; store2(sp, reg2(6)); }
1025 if (rlist&0x20) { sp-=2; store2(sp, reg2(5)); }
1026 if (rlist&0x10) { sp-=2; store2(sp, reg2(4)); }
1027 if (rlist&0x08) { sp-=2; store2(sp, reg2(3)); }
1028 if (rlist&0x04) { sp-=2; store2(sp, reg2(2)); }
1029 if (rlist&0x02) { sp-=2; store2(sp, reg2(1)); }
1030 if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
1033 if (code & 0x4000) { // R7h-R4l
1034 if (rlist&0x80) { sp-=2; store2(sp, reg1(15)); }
1035 if (rlist&0x40) { sp-=2; store2(sp, reg1(14)); }
1036 if (rlist&0x20) { sp-=2; store2(sp, reg1(13)); }
1037 if (rlist&0x10) { sp-=2; store2(sp, reg1(12)); }
1038 if (rlist&0x08) { sp-=2; store2(sp, reg1(11)); }
1039 if (rlist&0x04) { sp-=2; store2(sp, reg1(10)); }
1040 if (rlist&0x02) { sp-=2; store2(sp, reg1(9)); }
1041 if (rlist&0x01) { sp-=2; store2(sp, reg1(8)); }
1043 if (rlist&0x80) { sp-=2; store2(sp, reg1(7)); }
1044 if (rlist&0x40) { sp-=2; store2(sp, reg1(6)); }
1045 if (rlist&0x20) { sp-=2; store2(sp, reg1(5)); }
1046 if (rlist&0x10) { sp-=2; store2(sp, reg1(4)); }
1047 if (rlist&0x08) { sp-=2; store2(sp, reg1(3)); }
1048 if (rlist&0x04) { sp-=2; store2(sp, reg1(2)); }
1049 if (rlist&0x02) { sp-=2; store2(sp, reg1(1)); }
1050 if (rlist&0x01) { sp-=2; store2(sp, reg1(0)); }
1059 int cl_xa::inst_RESET(uint code, int operands)
1064 int cl_xa::inst_RET(uint code, int operands)
1066 unsigned int retaddr;
1068 bool pageZero=get_scr()&1;
1073 retaddr |= get2(sp+2) << 16;
1081 int cl_xa::inst_RETI(uint code, int operands)
1083 unsigned int retaddr;
1085 bool pageZero=get_scr()&1;
1089 retaddr = get2(sp+2);
1091 retaddr |= get2(sp+4) << 16;
1099 int cl_xa::inst_RL(uint code, int operands)
1104 int cl_xa::inst_RLC(uint code, int operands)
1109 int cl_xa::inst_RR(uint code, int operands)
1114 int cl_xa::inst_RRC(uint code, int operands)
1119 int cl_xa::inst_SETB(uint code, int operands)
1121 unsigned short bitAddr = (code&0x03 << 8) + fetch();
1122 set_bit (bitAddr, 1);
1126 int cl_xa::inst_SEXT(uint code, int operands)
1128 bool neg=get_psw()&BIT_N;
1129 if (code & 0x0800) { // word op
1130 set_reg2(RI_F0, neg ? 0xffff : 0);
1132 set_reg1(RI_F0, neg ? 0xff : 0);
1137 int cl_xa::inst_SUB(uint code, int operands)
1143 #include "inst_gen.cc"
1147 int cl_xa::inst_SUBB(uint code, int operands)
1153 #include "inst_gen.cc"
1157 int cl_xa::inst_TRAP(uint code, int operands)
1159 // steal a few opcodes for simulator only putchar() and exit()
1160 // functions. Used in SDCC regression testing.
1161 switch (code & 0x0f) {
1163 // implement a simulator putchar() routine
1164 //printf("PUTCHAR-----> %xH\n", reg1(0));
1176 int cl_xa::inst_XCH(uint code, int operands)
1181 int cl_xa::inst_XOR(uint code, int operands)
1187 #include "inst_gen.cc"
1191 /* End of xa.src/inst.cc */