2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 int cl_xa::get_reg(int word_flag, unsigned int index)
40 //if (index < 3) { /* banked */
42 // return get_word_direct(0x400+index);
44 // return mem_direct[0x400+index];
45 //} else { /* non-banked */
47 return get_word_direct(index);
49 return mem_direct[index];
53 bool cl_xa::get_bit(int bit) {
60 return mem_direct[offset + (bit/8)] & (1 << (bit%8));
63 void cl_xa::set_bit(int bit, int value) {
71 mem_direct[offset + (bit/8)] |= (1 << (bit%8));
73 mem_direct[offset + (bit/8)] &= ~(1 << (bit%8));
77 #define RI_F0 ((code >> 4) & 0xf)
78 #define RI_70 ((code >> 4) & 0x7)
79 #define RI_0F (code & 0xf)
80 #define RI_07 (code & 0x7)
82 int cl_xa::inst_ADD(uint code, int operands)
88 #include "inst_gen.cc"
93 int cl_xa::inst_ADDC(uint code, int operands)
99 #include "inst_gen.cc"
104 int cl_xa::inst_ADDS(uint code, int operands)
109 int cl_xa::inst_AND(uint code, int operands)
115 #include "inst_gen.cc"
119 int cl_xa::inst_ANL(uint code, int operands)
124 int cl_xa::inst_ASL(uint code, int operands)
129 int cl_xa::inst_ASR(uint code, int operands)
134 int cl_xa::inst_BCC(uint code, int operands)
139 int cl_xa::inst_BCS(uint code, int operands)
144 int cl_xa::inst_BEQ(uint code, int operands)
146 short jmpAddr = fetch1()*2;
147 if (get_psw() & BIT_Z) {
148 PC=(PC+jmpAddr)&0xfffffffe;
153 int cl_xa::inst_BG(uint code, int operands)
157 int cl_xa::inst_BGE(uint code, int operands)
161 int cl_xa::inst_BGT(uint code, int operands)
165 int cl_xa::inst_BKPT(uint code, int operands)
169 int cl_xa::inst_BL(uint code, int operands)
173 int cl_xa::inst_BLE(uint code, int operands)
177 int cl_xa::inst_BLT(uint code, int operands)
181 int cl_xa::inst_BMI(uint code, int operands)
185 int cl_xa::inst_BNE(uint code, int operands)
189 int cl_xa::inst_BNV(uint code, int operands)
193 int cl_xa::inst_BOV(uint code, int operands)
197 int cl_xa::inst_BPL(uint code, int operands)
202 int cl_xa::inst_BR(uint code, int operands)
204 short jmpAddr = fetch1()*2;
205 PC=(PC+jmpAddr)&0xfffffffe;
209 int cl_xa::inst_CALL(uint code, int operands)
213 bool pageZero=get_scr()&1;
218 jmpaddr = (signed short)fetch2();
219 sp = get_sp() - (pageZero ? 2 : 4);
221 store2(sp, PC&0xffff);
223 store2(sp+2, (PC>>16)&0xff);
226 PC = (PC + jmpaddr) & 0xfffffe;
231 sp = get_sp() - (pageZero ? 2 : 4);
233 store2(sp, PC&0xffff);
235 store2(sp+2, (PC>>16)&0xff);
237 jmpaddr = reg2(RI_07);
239 PC = (PC + jmpaddr) & 0xfffffe;
246 int cl_xa::inst_CJNE(uint code, int operands)
249 case REG_DIRECT_REL8:
252 if (code & 0x800) { // word op
254 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
255 int addr = (fetch1() * 2);
256 int dst = reg2(RI_F0);
259 flags &= ~BIT_ALL; /* clear these bits */
261 if (result == 0) flags |= BIT_Z;
262 if (result > 0xffff) flags |= BIT_C;
263 if (dst < src) flags |= BIT_N;
269 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
270 int addr = (fetch1() * 2);
271 int dst = reg1(RI_F0);
274 flags &= ~BIT_ALL; /* clear these bits */
276 if (result == 0) flags |= BIT_Z;
277 if (result > 0xff) flags |= BIT_C;
278 if (dst < src) flags |= BIT_N;
288 int daddr = ((code & 0x7) << 8) | fetch();
289 int addr = fetch() * 2;
291 if (code & 0x800) { // word op
292 unsigned short tmp = get_word_direct(daddr)-1;
293 set_word_direct(daddr, tmp);
297 unsigned char tmp = get_word_direct(daddr)-1;
298 set_byte_direct(daddr, tmp);
308 int cl_xa::inst_CLR(uint code, int operands)
310 unsigned short bitAddr = (code&0x03 << 8) + fetch();
316 int cl_xa::inst_CMP(uint code, int operands)
322 #include "inst_gen.cc"
325 int cl_xa::inst_CPL(uint code, int operands)
329 int cl_xa::inst_DA(uint code, int operands)
333 int cl_xa::inst_DIV(uint code, int operands)
338 int cl_xa::inst_DJNZ(uint code, int operands)
344 int addr = ( ((char)fetch1()) * 2);
345 if (code & 0x800) { // word op
346 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
347 set_reg2(RI_F0, tmp);
349 PC = (PC + addr) & 0xfffffffe;
351 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
352 set_reg1(RI_F0, tmp);
354 PC = (PC + addr) & 0xfffffffe;
361 int daddr = ((code & 0x7) << 8) | fetch();
362 int addr = fetch() * 2;
364 if (code & 0x800) { // word op
365 unsigned short tmp = get_word_direct(daddr)-1;
366 set_word_direct(daddr, tmp);
370 unsigned char tmp = get_word_direct(daddr)-1;
371 set_byte_direct(daddr, tmp);
382 int cl_xa::inst_FCALL(uint code, int operands)
387 int cl_xa::inst_FJMP(uint code, int operands)
392 int cl_xa::inst_JB(uint code, int operands)
394 short bitAddr=((code&0x3)<<8) + fetch1();
395 short jmpAddr = (fetch1() * 2);
396 if (get_bit(bitAddr)) {
397 PC = (PC+jmpAddr)&0xfffffe;
401 int cl_xa::inst_JBC(uint code, int operands)
405 int cl_xa::inst_JNB(uint code, int operands)
407 short bitAddr=((code&0x3)<<8) + fetch1();
408 short jmpAddr = (fetch1() * 2);
409 if (!get_bit(bitAddr)) {
410 PC = (PC+jmpAddr)&0xfffffe;
415 int cl_xa::inst_JMP(uint code, int operands)
422 jmpAddr = (signed short)fetch2()*2;
423 PC = (PC + jmpAddr) & 0xfffffffe;
428 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
430 /* fixme 2 more... */
434 int cl_xa::inst_JNZ(uint code, int operands)
436 short saddr = (fetch1() * 2);
437 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
439 PC = (PC + saddr) & 0xfffffe;
443 int cl_xa::inst_JZ(uint code, int operands)
445 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
446 short saddr = (fetch1() * 2);
452 int cl_xa::inst_LEA(uint code, int operands)
456 int cl_xa::inst_LSR(uint code, int operands)
460 int cl_xa::inst_MOV(uint code, int operands)
466 #include "inst_gen.cc"
469 int cl_xa::inst_MOVC(uint code, int operands)
474 short srcreg = reg2(RI_07);
475 if (code & 0x0800) { /* word op */
488 if (operands == REG_IREGINC) {
489 set_reg2(RI_07, srcreg+1);
497 int cl_xa::inst_MOVS(uint code, int operands)
501 int cl_xa::inst_MOVX(uint code, int operands)
505 int cl_xa::inst_MUL(uint code, int operands)
509 int cl_xa::inst_NEG(uint code, int operands)
513 int cl_xa::inst_NOP(uint code, int operands)
517 int cl_xa::inst_NORM(uint code, int operands)
521 int cl_xa::inst_OR(uint code, int operands)
527 #include "inst_gen.cc"
531 int cl_xa::inst_ORL(uint code, int operands)
536 int cl_xa::inst_POP(uint code, int operands)
542 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
545 if (code & 0x0800) { /* word op */
546 set_word_direct(direct_addr, get2(sp) );
548 set_byte_direct(direct_addr, get2(sp) & 0xff );
556 unsigned char rlist = fetch();
557 rlist = rlist; //shutup compiler
563 int cl_xa::inst_PUSH(uint code, int operands)
569 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
573 if (code & 0x0800) { /* word op */
574 store2( sp, get_word_direct(direct_addr));
576 store2( sp, get_byte_direct(direct_addr));
583 unsigned char rlist = fetch();
584 rlist = rlist; //shutup compiler
590 int cl_xa::inst_RESET(uint code, int operands)
594 int cl_xa::inst_RET(uint code, int operands)
596 unsigned int retaddr;
598 bool pageZero=get_scr()&1;
603 retaddr |= get2(sp+2) << 16;
611 int cl_xa::inst_RETI(uint code, int operands)
613 unsigned int retaddr;
615 bool pageZero=get_scr()&1;
619 retaddr = get2(sp+2);
621 retaddr |= get2(sp+4) << 16;
629 int cl_xa::inst_RL(uint code, int operands)
633 int cl_xa::inst_RLC(uint code, int operands)
637 int cl_xa::inst_RR(uint code, int operands)
641 int cl_xa::inst_RRC(uint code, int operands)
645 int cl_xa::inst_SETB(uint code, int operands)
647 unsigned short bitAddr = (code&0x03 << 8) + fetch();
653 int cl_xa::inst_SEXT(uint code, int operands)
658 int cl_xa::inst_SUB(uint code, int operands)
664 #include "inst_gen.cc"
668 int cl_xa::inst_SUBB(uint code, int operands)
674 #include "inst_gen.cc"
677 int cl_xa::inst_TRAP(uint code, int operands)
681 int cl_xa::inst_XCH(uint code, int operands)
685 int cl_xa::inst_XOR(uint code, int operands)
691 #include "inst_gen.cc"
695 /* End of xa.src/inst.cc */