2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 int cl_xa::get_reg(int word_flag, unsigned int index)
40 //if (index < 3) { /* banked */
42 // return get_word_direct(0x400+index);
44 // return mem_direct[0x400+index];
45 //} else { /* non-banked */
47 return get_word_direct(0x400+index);
49 return mem_direct[0x400+index];
53 #define RI_F0 ((code >> 4) & 0xf)
54 #define RI_70 ((code >> 4) & 0x7)
55 #define RI_0F (code & 0xf)
56 #define RI_07 (code & 0x7)
58 int cl_xa::inst_ADD(uint code, int operands)
64 #include "inst_gen.cc"
69 int cl_xa::inst_ADDC(uint code, int operands)
75 #include "inst_gen.cc"
80 int cl_xa::inst_ADDS(uint code, int operands)
85 int cl_xa::inst_AND(uint code, int operands)
91 #include "inst_gen.cc"
95 int cl_xa::inst_ANL(uint code, int operands)
100 int cl_xa::inst_ASL(uint code, int operands)
105 int cl_xa::inst_ASR(uint code, int operands)
110 int cl_xa::inst_BCC(uint code, int operands)
115 int cl_xa::inst_BCS(uint code, int operands)
120 int cl_xa::inst_BEQ(uint code, int operands)
122 short jmpAddr = fetch1()*2;
123 if (get_psw() & BIT_Z) {
124 PC=(PC+jmpAddr)&0xfffffffe;
129 int cl_xa::inst_BG(uint code, int operands)
133 int cl_xa::inst_BGE(uint code, int operands)
137 int cl_xa::inst_BGT(uint code, int operands)
141 int cl_xa::inst_BKPT(uint code, int operands)
145 int cl_xa::inst_BL(uint code, int operands)
149 int cl_xa::inst_BLE(uint code, int operands)
153 int cl_xa::inst_BLT(uint code, int operands)
157 int cl_xa::inst_BMI(uint code, int operands)
161 int cl_xa::inst_BNE(uint code, int operands)
165 int cl_xa::inst_BNV(uint code, int operands)
169 int cl_xa::inst_BOV(uint code, int operands)
173 int cl_xa::inst_BPL(uint code, int operands)
178 int cl_xa::inst_BR(uint code, int operands)
180 short jmpAddr = fetch1()*2;
181 PC=(PC+jmpAddr)&0xfffffffe;
185 int cl_xa::inst_CALL(uint code, int operands)
193 jmpaddr = (signed short)fetch2();
197 store2(sp+2, 0); /* segment(not sure about ordering...) */
199 PC = (PC + jmpaddr) & 0xfffffffe;
207 #if 0 // only in huge model
210 jmpaddr = reg2(RI_07);
212 PC = (PC + jmpaddr) & 0xfffffffe;
215 /* fixme 2 more... */ /* johan: which ones? */
220 int cl_xa::inst_CJNE(uint code, int operands)
223 case REG_DIRECT_REL8:
226 if (code & 0x800) { // word op
228 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
229 int addr = (fetch1() * 2);
230 int dst = reg2(RI_F0);
233 flags &= ~BIT_ALL; /* clear these bits */
235 if (result == 0) flags |= BIT_Z;
236 if (result > 0xffff) flags |= BIT_C;
237 if (dst < src) flags |= BIT_N;
243 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
244 int addr = (fetch1() * 2);
245 int dst = reg1(RI_F0);
248 flags &= ~BIT_ALL; /* clear these bits */
250 if (result == 0) flags |= BIT_Z;
251 if (result > 0xff) flags |= BIT_C;
252 if (dst < src) flags |= BIT_N;
262 int daddr = ((code & 0x7) << 8) | fetch();
263 int addr = fetch() * 2;
265 if (code & 0x800) { // word op
266 unsigned short tmp = get_word_direct(daddr)-1;
267 set_word_direct(daddr, tmp);
271 unsigned char tmp = get_word_direct(daddr)-1;
272 set_byte_direct(daddr, tmp);
282 int cl_xa::inst_CLR(uint code, int operands)
284 unsigned short bitAddr = (code&0x03 << 8) + fetch();
290 int cl_xa::inst_CMP(uint code, int operands)
296 #include "inst_gen.cc"
299 int cl_xa::inst_CPL(uint code, int operands)
303 int cl_xa::inst_DA(uint code, int operands)
307 int cl_xa::inst_DIV(uint code, int operands)
312 int cl_xa::inst_DJNZ(uint code, int operands)
318 int addr = ( ((char)fetch1()) * 2);
319 if (code & 0x800) { // word op
320 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
321 set_reg2(RI_F0, tmp);
323 PC = (PC + addr) & 0xfffffffe;
325 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
326 set_reg1(RI_F0, tmp);
328 PC = (PC + addr) & 0xfffffffe;
335 int daddr = ((code & 0x7) << 8) | fetch();
336 int addr = fetch() * 2;
338 if (code & 0x800) { // word op
339 unsigned short tmp = get_word_direct(daddr)-1;
340 set_word_direct(daddr, tmp);
344 unsigned char tmp = get_word_direct(daddr)-1;
345 set_byte_direct(daddr, tmp);
356 int cl_xa::inst_FCALL(uint code, int operands)
361 int cl_xa::inst_FJMP(uint code, int operands)
366 int cl_xa::inst_JB(uint code, int operands)
368 short bitAddr=((code&0x3)<<8) + fetch1();
369 short jmpAddr = (fetch1() * 2);
370 if (get_bit(bitAddr)) {
371 PC = (PC+jmpAddr)&0xfffffe;
375 int cl_xa::inst_JBC(uint code, int operands)
379 int cl_xa::inst_JNB(uint code, int operands)
381 short bitAddr=((code&0x3)<<8) + fetch1();
382 short jmpAddr = (fetch1() * 2);
383 if (!get_bit(bitAddr)) {
384 PC = (PC+jmpAddr)&0xfffffe;
389 int cl_xa::inst_JMP(uint code, int operands)
396 jmpAddr = (signed short)fetch2()*2;
397 PC = (PC + jmpAddr) & 0xfffffffe;
402 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
404 /* fixme 2 more... */
408 int cl_xa::inst_JNZ(uint code, int operands)
410 short saddr = (fetch1() * 2);
411 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
413 PC = (PC + saddr) & 0xfffffe;
417 int cl_xa::inst_JZ(uint code, int operands)
419 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
420 short saddr = (fetch1() * 2);
426 int cl_xa::inst_LEA(uint code, int operands)
430 int cl_xa::inst_LSR(uint code, int operands)
434 int cl_xa::inst_MOV(uint code, int operands)
440 #include "inst_gen.cc"
443 int cl_xa::inst_MOVC(uint code, int operands)
448 short srcreg = reg2(RI_07);
449 if (code & 0x0800) { /* word op */
462 if (operands == REG_IREGINC) {
463 set_reg2(RI_07, srcreg+1);
471 int cl_xa::inst_MOVS(uint code, int operands)
475 int cl_xa::inst_MOVX(uint code, int operands)
479 int cl_xa::inst_MUL(uint code, int operands)
483 int cl_xa::inst_NEG(uint code, int operands)
487 int cl_xa::inst_NOP(uint code, int operands)
491 int cl_xa::inst_NORM(uint code, int operands)
495 int cl_xa::inst_OR(uint code, int operands)
501 #include "inst_gen.cc"
505 int cl_xa::inst_ORL(uint code, int operands)
510 int cl_xa::inst_POP(uint code, int operands)
516 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
519 if (code & 0x0800) { /* word op */
520 set_word_direct(direct_addr, get2(sp) );
522 set_byte_direct(direct_addr, get2(sp) & 0xff );
530 unsigned char rlist = fetch();
531 rlist = rlist; //shutup compiler
537 int cl_xa::inst_PUSH(uint code, int operands)
543 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
547 if (code & 0x0800) { /* word op */
548 store2( sp, get_word_direct(direct_addr));
550 store2( sp, get_byte_direct(direct_addr));
557 unsigned char rlist = fetch();
558 rlist = rlist; //shutup compiler
564 int cl_xa::inst_RESET(uint code, int operands)
568 int cl_xa::inst_RET(uint code, int operands)
570 unsigned int retaddr;
574 #if 0 // only in huge model
575 retaddr |= get2(sp+2) << 16;
581 int cl_xa::inst_RETI(uint code, int operands)
585 int cl_xa::inst_RL(uint code, int operands)
589 int cl_xa::inst_RLC(uint code, int operands)
593 int cl_xa::inst_RR(uint code, int operands)
597 int cl_xa::inst_RRC(uint code, int operands)
601 int cl_xa::inst_SETB(uint code, int operands)
603 unsigned short bitAddr = (code&0x03 << 8) + fetch();
609 int cl_xa::inst_SEXT(uint code, int operands)
614 int cl_xa::inst_SUB(uint code, int operands)
620 #include "inst_gen.cc"
624 int cl_xa::inst_SUBB(uint code, int operands)
630 #include "inst_gen.cc"
633 int cl_xa::inst_TRAP(uint code, int operands)
637 int cl_xa::inst_XCH(uint code, int operands)
641 int cl_xa::inst_XOR(uint code, int operands)
647 #include "inst_gen.cc"
651 /* End of xa.src/inst.cc */