2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
9 * Johan Knol johan.knol@iduna.nl
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #define NOTDONE_ASSERT { printf("**********Instr not done at %d!\n", __LINE__); }
40 void cl_xa::store1(t_addr addr, unsigned char val)
43 set_idata1(addr, val);
45 set_xdata1(addr, val);
49 void cl_xa::store2(t_addr addr, unsigned short val)
52 set_idata2(addr, val);
54 set_xdata2(addr, val);
58 unsigned char cl_xa::get1(t_addr addr)
61 return get_idata1(addr);
63 return get_xdata1(addr);
67 unsigned short cl_xa::get2(t_addr addr)
70 return get_idata2(addr);
72 return get_xdata2(addr);
76 int cl_xa::get_reg(int word_flag, unsigned int index)
81 result = get_word_direct(index);
84 result = get_byte_direct(index);
89 bool cl_xa::get_bit(int bit) {
98 result = get_byte_direct(offset + (bit/8)) & (1 << (bit%8));
102 void cl_xa::set_bit(int bit, int value) {
111 i = get_byte_direct(offset + (bit/8));
113 set_byte_direct(offset + (bit/8), i | (1 << (bit%8)) );
115 set_byte_direct(offset + (bit/8), i & ~(1 << (bit%8)) );
119 #define RI_F0 ((code >> 4) & 0xf)
120 #define RI_70 ((code >> 4) & 0x7)
121 #define RI_0F (code & 0xf)
122 #define RI_07 (code & 0x7)
124 int cl_xa::inst_ADD(uint code, int operands)
130 #include "inst_gen.cc"
135 int cl_xa::inst_ADDC(uint code, int operands)
141 #include "inst_gen.cc"
146 int cl_xa::inst_ADDS(uint code, int operands)
152 int cl_xa::inst_AND(uint code, int operands)
158 #include "inst_gen.cc"
162 /* logical AND bit with Carry flag */
163 int cl_xa::inst_ANL(uint code, int operands)
166 unsigned short bitAddr = (code&0x03 << 8) + fetch();
170 /* have work to do */
173 if (!get_bit(bitAddr)) {
174 set_psw(flags & ~BIT_C);
179 if (get_bit(bitAddr)) {
180 set_psw(flags & ~BIT_C);
189 /* arithmetic shift left */
190 int cl_xa::inst_ASL(uint code, int operands)
192 unsigned int dst, cnt;
197 C = dest.80H; dest <<= 1; if sign chg then set V=1
198 this is a confusing one...
202 flags &= ~BIT_ALL; /* clear these bits */
205 //{0,0xc150,0xf300,' ',2,ASL, REG_REG }, // ASL Rd, Rs 1 1 0 0 S S 0 1 d d d d s s s s
207 cnt = reg1(RI_0F) & 0x1f;
208 switch (code & 0xc00) {
215 if ((dst & 0xff) == 0)
224 if ((dst & 0xffff) == 0)
228 // not really sure about the encoding here..
233 dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
234 if ((cnt != 0) && (dst & (0x80000000 >> (cnt-1)))) {
238 set_reg2(RI_F0,dst & 0xffff);
239 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
248 switch (code & 0xc00) {
251 cnt = operands & 0x0f;
256 if ((dst & 0xff) == 0)
261 cnt = operands & 0x0f;
266 if ((dst & 0xffff) == 0)
270 // not really sure about the encoding here..
274 dst = reg1(RI_F0 & 0xe);
275 cnt = operands & 0x1f;
276 if ((cnt != 0) && (dst & (0x80000000 >> (cnt-1)))) {
280 set_reg2(RI_F0,dst & 0xffff);
281 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
293 /* arithmetic shift right */
294 int cl_xa::inst_ASR(uint code, int operands)
296 unsigned int dst, cnt;
301 C = dest.0; dest >>= 1;
302 this is a confusing one...
306 flags &= ~BIT_ALL; /* clear these bits */
310 cnt = reg1(RI_0F) & 0x1f;
311 switch (code & 0xc00) {
314 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
320 if ((dst & 0xff) == 0)
325 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
329 if ((dst & 0xffff) == 0)
333 // not really sure about the encoding here..
337 dst = reg2(RI_F0) | (reg2(RI_F0 + 2) << 16);
338 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
341 set_reg2(RI_F0,dst & 0xffff);
342 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
351 switch (code & 0xc00) {
354 cnt = operands & 0x0f;
355 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
359 if ((dst & 0xff) == 0)
364 cnt = operands & 0x0f;
365 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
369 if ((dst & 0xffff) == 0)
373 // not really sure about the encoding here..
377 dst = reg1(RI_F0 & 0xe);
378 cnt = operands & 0x1f;
379 if ((cnt != 0) && (dst & (0x00000001 << (cnt-1))))
382 set_reg2(RI_F0,dst & 0xffff);
383 set_reg2(RI_F0+2, (dst>>16) & 0xffff);
395 int cl_xa::inst_BCC(uint code, int operands)
397 short jmpAddr = fetch1()*2;
398 if (!(get_psw() & BIT_C)) {
399 PC=(PC+jmpAddr)&0xfffffe;
404 int cl_xa::inst_BCS(uint code, int operands)
406 short jmpAddr = fetch1()*2;
407 if (get_psw() & BIT_C) {
408 PC=(PC+jmpAddr)&0xfffffe;
413 int cl_xa::inst_BEQ(uint code, int operands)
415 short jmpAddr = fetch1()*2;
416 if (get_psw() & BIT_Z) {
417 PC=(PC+jmpAddr)&0xfffffe;
422 int cl_xa::inst_BG(uint code, int operands)
424 short jmpAddr = fetch1()*2;
425 short flags=get_psw();
426 bool Z=flags&BIT_Z, C=flags&BIT_C;
428 PC=(PC+jmpAddr)&0xfffffe;
432 int cl_xa::inst_BGE(uint code, int operands)
434 short jmpAddr = fetch1()*2;
435 short flags=get_psw();
436 bool N=flags&BIT_N, V=flags&BIT_V;
438 PC=(PC+jmpAddr)&0xfffffe;
442 int cl_xa::inst_BGT(uint code, int operands)
444 short jmpAddr = fetch1()*2;
445 short flags=get_psw();
446 bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
448 PC=(PC+jmpAddr)&0xfffffe;
452 int cl_xa::inst_BKPT(uint code, int operands)
457 int cl_xa::inst_BL(uint code, int operands)
459 short jmpAddr = fetch1()*2;
460 short flags=get_psw();
461 bool Z=flags&BIT_Z, C=flags&BIT_C;
463 PC=(PC+jmpAddr)&0xfffffe;
467 int cl_xa::inst_BLE(uint code, int operands)
469 short jmpAddr = fetch1()*2;
470 short flags=get_psw();
471 bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
473 PC=(PC+jmpAddr)&0xfffffe;
477 int cl_xa::inst_BLT(uint code, int operands)
479 short jmpAddr = fetch1()*2;
480 short flags=get_psw();
481 bool N=flags&BIT_N, V=flags&BIT_V;
483 PC=(PC+jmpAddr)&0xfffffe;
487 int cl_xa::inst_BMI(uint code, int operands)
489 short jmpAddr = fetch1()*2;
490 if (get_psw()&BIT_N) {
491 PC=(PC+jmpAddr)&0xfffffe;
495 int cl_xa::inst_BNE(uint code, int operands)
497 short jmpAddr = fetch1()*2;
498 if (!(get_psw()&BIT_Z)) {
499 PC=(PC+jmpAddr)&0xfffffe;
503 int cl_xa::inst_BNV(uint code, int operands)
505 short jmpAddr = fetch1()*2;
506 if (!(get_psw()&BIT_V)) {
507 PC=(PC+jmpAddr)&0xfffffe;
511 int cl_xa::inst_BOV(uint code, int operands)
513 short jmpAddr = fetch1()*2;
514 if (get_psw()&BIT_V) {
515 PC=(PC+jmpAddr)&0xfffffe;
519 int cl_xa::inst_BPL(uint code, int operands)
521 short jmpAddr = fetch1()*2;
522 if (!(get_psw()&BIT_N)) {
523 PC=(PC+jmpAddr)&0xfffffe;
528 int cl_xa::inst_BR(uint code, int operands)
530 short jmpAddr = fetch1()*2;
531 PC=(PC+jmpAddr)&0xfffffe;
535 int cl_xa::inst_CALL(uint code, int operands)
539 bool pageZero=get_scr()&1;
544 jmpaddr = (signed short)fetch2();
545 sp = get_sp() - (pageZero ? 2 : 4);
547 store2(sp, PC&0xffff);
549 store2(sp+2, (PC>>16)&0xff);
552 PC = (PC + jmpaddr) & 0xfffffe;
557 sp = get_sp() - (pageZero ? 2 : 4);
559 store2(sp, PC&0xffff);
561 store2(sp+2, (PC>>16)&0xff);
563 jmpaddr = reg2(RI_07);
565 PC = (PC + jmpaddr) & 0xfffffe;
572 int cl_xa::inst_CJNE(uint code, int operands)
575 case REG_DIRECT_REL8:
578 if (code & 0x800) { // word op
580 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
581 int addr = (fetch1() * 2);
582 int dst = reg2(RI_F0);
585 flags &= ~BIT_ALL; /* clear these bits */
587 if (result == 0) flags |= BIT_Z;
588 if (result > 0xffff) flags |= BIT_C;
589 if (dst < src) flags |= BIT_N;
595 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
596 int addr = (fetch1() * 2);
597 int dst = reg1(RI_F0);
600 flags &= ~BIT_ALL; /* clear these bits */
602 if (result == 0) flags |= BIT_Z;
603 if (result > 0xff) flags |= BIT_C;
604 if (dst < src) flags |= BIT_N;
614 int daddr = ((code & 0x7) << 8) | fetch();
615 int addr = fetch() * 2;
617 if (code & 0x800) { // word op
618 unsigned short tmp = get_word_direct(daddr)-1;
619 set_word_direct(daddr, tmp);
623 unsigned char tmp = get_word_direct(daddr)-1;
624 set_byte_direct(daddr, tmp);
634 int cl_xa::inst_CLR(uint code, int operands)
636 unsigned short bitAddr = (code&0x03 << 8) + fetch();
637 set_bit (bitAddr, 0);
641 int cl_xa::inst_CMP(uint code, int operands)
647 #include "inst_gen.cc"
650 int cl_xa::inst_CPL(uint code, int operands)
655 int cl_xa::inst_DA(uint code, int operands)
660 int cl_xa::inst_DIV(uint code, int operands)
666 int cl_xa::inst_DJNZ(uint code, int operands)
672 int addr = ( ((char)fetch1()) * 2);
673 if (code & 0x800) { // word op
674 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
675 set_reg2(RI_F0, tmp);
677 PC = (PC + addr) & 0xfffffe;
679 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
680 set_reg1(RI_F0, tmp);
682 PC = (PC + addr) & 0xfffffe;
689 int daddr = ((code & 0x7) << 8) | fetch();
690 int addr = fetch() * 2;
692 if (code & 0x800) { // word op
693 unsigned short tmp = get_word_direct(daddr)-1;
694 set_word_direct(daddr, tmp);
698 unsigned char tmp = get_word_direct(daddr)-1;
699 set_byte_direct(daddr, tmp);
710 int cl_xa::inst_FCALL(uint code, int operands)
716 int cl_xa::inst_FJMP(uint code, int operands)
722 int cl_xa::inst_JB(uint code, int operands)
724 short bitAddr=((code&0x3)<<8) + fetch1();
725 short jmpAddr = (fetch1() * 2);
726 if (get_bit(bitAddr)) {
727 PC = (PC+jmpAddr)&0xfffffe;
731 int cl_xa::inst_JBC(uint code, int operands)
733 short bitAddr=((code&0x3)<<8) + fetch1();
734 short jmpAddr = (fetch1() * 2);
735 if (get_bit(bitAddr)) {
736 PC = (PC+jmpAddr)&0xfffffe;
741 int cl_xa::inst_JNB(uint code, int operands)
743 short bitAddr=((code&0x3)<<8) + fetch1();
744 short jmpAddr = (fetch1() * 2);
745 if (!get_bit(bitAddr)) {
746 PC = (PC+jmpAddr)&0xfffffe;
750 int cl_xa::inst_JMP(uint code, int operands)
757 jmpAddr = (signed short)fetch2()*2;
758 PC = (PC + jmpAddr) & 0xfffffe;
763 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
765 /* fixme 2 more... */
769 int cl_xa::inst_JNZ(uint code, int operands)
771 short saddr = (fetch1() * 2);
772 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
774 PC = (PC + saddr) & 0xfffffe;
778 int cl_xa::inst_JZ(uint code, int operands)
780 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
781 short saddr = (fetch1() * 2);
787 int cl_xa::inst_LEA(uint code, int operands)
792 char offset=fetch1();
793 set_reg2(RI_70, reg2(RI_07)+offset);
798 short offset=fetch2();
799 set_reg2(RI_70, reg2(RI_07)+offset);
805 int cl_xa::inst_LSR(uint code, int operands)
810 int cl_xa::inst_MOV(uint code, int operands)
816 #include "inst_gen.cc"
819 int cl_xa::inst_MOVC(uint code, int operands)
824 short srcreg = reg2(RI_07);
825 if (code & 0x0800) { /* word op */
838 if (operands == REG_IREGINC) {
839 set_reg2(RI_07, srcreg+1);
844 { /* R4l=ACC, R6=DPTR */
845 unsigned int addr = (PC & 0xff0000) | (reg1(4) + reg2(6));
846 unsigned short result;
850 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
851 result = getcode1(addr);
852 set_reg1( 4, result);
853 if (result == 0) flags |= BIT_Z;
854 if (result & 0x80) flags |= BIT_N;
859 { /* R4l=ACC, R6=DPTR */
860 unsigned int addr = (PC + reg1(4));
861 unsigned short result;
865 flags &= ~(BIT_Z | BIT_N); /* clear these bits */
866 result = getcode1(addr);
867 set_reg1( 4, result);
868 if (result == 0) flags |= BIT_Z;
869 if (result & 0x80) flags |= BIT_N;
876 int cl_xa::inst_MOVS(uint code, int operands)
881 int cl_xa::inst_MOVX(uint code, int operands)
886 int cl_xa::inst_MUL(uint code, int operands)
891 int cl_xa::inst_NEG(uint code, int operands)
896 int cl_xa::inst_NOP(uint code, int operands)
900 int cl_xa::inst_NORM(uint code, int operands)
905 int cl_xa::inst_OR(uint code, int operands)
911 #include "inst_gen.cc"
915 int cl_xa::inst_ORL(uint code, int operands)
921 int cl_xa::inst_POP(uint code, int operands)
923 unsigned short sp=get_sp();
927 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
929 if (code & 0x0800) { /* word op */
930 set_word_direct(direct_addr, get2(sp) );
932 set_byte_direct(direct_addr, get2(sp) & 0xff );
940 unsigned char rlist = fetch();
941 if (code & 0x0800) { // word op
942 if (code & 0x4000) { // R8-R15
943 if (rlist&0x01) { set_reg2(8, get2(sp)); sp+=2; }
944 if (rlist&0x02) { set_reg2(9, get2(sp)); sp+=2; }
945 if (rlist&0x04) { set_reg2(10, get2(sp)); sp+=2; }
946 if (rlist&0x08) { set_reg2(11, get2(sp)); sp+=2; }
947 if (rlist&0x10) { set_reg2(12, get2(sp)); sp+=2; }
948 if (rlist&0x20) { set_reg2(13, get2(sp)); sp+=2; }
949 if (rlist&0x40) { set_reg2(14, get2(sp)); sp+=2; }
950 if (rlist&0x80) { set_reg2(15, get2(sp)); sp+=2; }
952 if (rlist&0x01) { set_reg2(0, get2(sp)); sp+=2; }
953 if (rlist&0x02) { set_reg2(1, get2(sp)); sp+=2; }
954 if (rlist&0x04) { set_reg2(2, get2(sp)); sp+=2; }
955 if (rlist&0x08) { set_reg2(3, get2(sp)); sp+=2; }
956 if (rlist&0x10) { set_reg2(4, get2(sp)); sp+=2; }
957 if (rlist&0x20) { set_reg2(5, get2(sp)); sp+=2; }
958 if (rlist&0x40) { set_reg2(6, get2(sp)); sp+=2; }
959 if (rlist&0x80) { set_reg2(7, get2(sp)); sp+=2; }
962 if (code & 0x4000) { // R4l-R7h
963 if (rlist&0x01) { set_reg1(8, get1(sp)); sp+=2; }
964 if (rlist&0x02) { set_reg1(9, get1(sp)); sp+=2; }
965 if (rlist&0x04) { set_reg1(10, get1(sp)); sp+=2; }
966 if (rlist&0x08) { set_reg1(11, get1(sp)); sp+=2; }
967 if (rlist&0x10) { set_reg1(12, get1(sp)); sp+=2; }
968 if (rlist&0x20) { set_reg1(13, get1(sp)); sp+=2; }
969 if (rlist&0x40) { set_reg1(14, get1(sp)); sp+=2; }
970 if (rlist&0x80) { set_reg1(15, get1(sp)); sp+=2; }
972 if (rlist&0x01) { set_reg1(0, get1(sp)); sp+=2; }
973 if (rlist&0x02) { set_reg1(1, get1(sp)); sp+=2; }
974 if (rlist&0x04) { set_reg1(2, get1(sp)); sp+=2; }
975 if (rlist&0x08) { set_reg1(3, get1(sp)); sp+=2; }
976 if (rlist&0x10) { set_reg1(4, get1(sp)); sp+=2; }
977 if (rlist&0x20) { set_reg1(5, get1(sp)); sp+=2; }
978 if (rlist&0x40) { set_reg1(6, get1(sp)); sp+=2; }
979 if (rlist&0x80) { set_reg1(7, get1(sp)); sp+=2; }
988 int cl_xa::inst_PUSH(uint code, int operands)
994 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
998 if (code & 0x0800) { /* word op */
999 store2( sp, get_word_direct(direct_addr));
1001 store2( sp, get_byte_direct(direct_addr));
1008 unsigned short sp=get_sp();
1009 unsigned char rlist = fetch();
1010 if (code & 0x0800) { // word op
1011 if (code & 0x4000) { // R15-R8
1012 if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
1013 if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
1014 if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
1015 if (rlist&0x10) { sp-=2; store2(sp, reg2(12)); }
1016 if (rlist&0x08) { sp-=2; store2(sp, reg2(11)); }
1017 if (rlist&0x04) { sp-=2; store2(sp, reg2(10)); }
1018 if (rlist&0x02) { sp-=2; store2(sp, reg2(9)); }
1019 if (rlist&0x01) { sp-=2; store2(sp, reg2(8)); }
1021 if (rlist&0x80) { sp-=2; store2(sp, reg2(7)); }
1022 if (rlist&0x40) { sp-=2; store2(sp, reg2(6)); }
1023 if (rlist&0x20) { sp-=2; store2(sp, reg2(5)); }
1024 if (rlist&0x10) { sp-=2; store2(sp, reg2(4)); }
1025 if (rlist&0x08) { sp-=2; store2(sp, reg2(3)); }
1026 if (rlist&0x04) { sp-=2; store2(sp, reg2(2)); }
1027 if (rlist&0x02) { sp-=2; store2(sp, reg2(1)); }
1028 if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
1031 if (code & 0x4000) { // R7h-R4l
1032 if (rlist&0x80) { sp-=2; store2(sp, reg1(15)); }
1033 if (rlist&0x40) { sp-=2; store2(sp, reg1(14)); }
1034 if (rlist&0x20) { sp-=2; store2(sp, reg1(13)); }
1035 if (rlist&0x10) { sp-=2; store2(sp, reg1(12)); }
1036 if (rlist&0x08) { sp-=2; store2(sp, reg1(11)); }
1037 if (rlist&0x04) { sp-=2; store2(sp, reg1(10)); }
1038 if (rlist&0x02) { sp-=2; store2(sp, reg1(9)); }
1039 if (rlist&0x01) { sp-=2; store2(sp, reg1(8)); }
1041 if (rlist&0x80) { sp-=2; store2(sp, reg1(7)); }
1042 if (rlist&0x40) { sp-=2; store2(sp, reg1(6)); }
1043 if (rlist&0x20) { sp-=2; store2(sp, reg1(5)); }
1044 if (rlist&0x10) { sp-=2; store2(sp, reg1(4)); }
1045 if (rlist&0x08) { sp-=2; store2(sp, reg1(3)); }
1046 if (rlist&0x04) { sp-=2; store2(sp, reg1(2)); }
1047 if (rlist&0x02) { sp-=2; store2(sp, reg1(1)); }
1048 if (rlist&0x01) { sp-=2; store2(sp, reg1(0)); }
1057 int cl_xa::inst_RESET(uint code, int operands)
1062 int cl_xa::inst_RET(uint code, int operands)
1064 unsigned int retaddr;
1066 bool pageZero=get_scr()&1;
1071 retaddr |= get2(sp+2) << 16;
1079 int cl_xa::inst_RETI(uint code, int operands)
1081 unsigned int retaddr;
1083 bool pageZero=get_scr()&1;
1087 retaddr = get2(sp+2);
1089 retaddr |= get2(sp+4) << 16;
1097 int cl_xa::inst_RL(uint code, int operands)
1102 int cl_xa::inst_RLC(uint code, int operands)
1107 int cl_xa::inst_RR(uint code, int operands)
1112 int cl_xa::inst_RRC(uint code, int operands)
1117 int cl_xa::inst_SETB(uint code, int operands)
1119 unsigned short bitAddr = (code&0x03 << 8) + fetch();
1120 set_bit (bitAddr, 1);
1124 int cl_xa::inst_SEXT(uint code, int operands)
1126 bool neg=get_psw()&BIT_N;
1127 if (code & 0x0800) { // word op
1128 set_reg2(RI_F0, neg ? 0xffff : 0);
1130 set_reg1(RI_F0, neg ? 0xff : 0);
1135 int cl_xa::inst_SUB(uint code, int operands)
1141 #include "inst_gen.cc"
1145 int cl_xa::inst_SUBB(uint code, int operands)
1151 #include "inst_gen.cc"
1155 int cl_xa::inst_TRAP(uint code, int operands)
1157 // steal a few opcodes for simulator only putchar() and exit()
1158 // functions. Used in SDCC regression testing.
1159 switch (code & 0x0f) {
1161 // implement a simulator putchar() routine
1162 //printf("PUTCHAR-----> %xH\n", reg1(0));
1174 int cl_xa::inst_XCH(uint code, int operands)
1179 int cl_xa::inst_XOR(uint code, int operands)
1185 #include "inst_gen.cc"
1189 /* End of xa.src/inst.cc */