2 * Simulator of microcontrollers (stypes.h)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
34 typedef unsigned char uchar;
35 typedef unsigned int uint;
36 typedef unsigned long ulong;
37 typedef TYPE_DWORD t_addr; /* 32 bit max */
38 typedef TYPE_UWORD t_mem; /* 16 bit max */
39 typedef TYPE_WORD t_smem; /* signed 16 bit memory */
44 const char *id_string;
53 // table of dissassembled instructions
62 // table entry of SFR and BIT names
82 #define CPU_51R 0x0010
83 #define CPU_89C51R 0x0020
84 #define CPU_251 0x0040
85 #define CPU_DS390 0x0080
86 #define CPU_DS390F 0x0100
87 #define CPU_ALL_51 (CPU_51|CPU_31)
88 #define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|CPU_DS390|CPU_DS390F)
90 #define CPU_AVR 0x0001
91 #define CPU_ALL_AVR (CPU_AVR)
93 #define CPU_Z80 0x0001
94 #define CPU_ALL_Z80 (CPU_Z80)
97 #define CPU_ALL_XA (CPU_XA)
99 #define CPU_HC08 0x0001
100 #define CPU_ALL_HC08 (CPU_HC08)
102 #define CPU_CMOS 0x0001
103 #define CPU_HMOS 0x0002
105 /* Classes of memories, this is index on the list */
117 #define MEM_ROM_ID "rom"
118 #define MEM_SFR_ID "sfr"
119 #define MEM_XRAM_ID "xram"
120 #define MEM_IXRAM_ID "ixram"
121 #define MEM_IRAM_ID "iram"
123 // States of simulator
125 #define SIM_GO 0x01 // Processor is running
126 #define SIM_QUIT 0x02 // Program must exit
129 #define stGO 0 /* Normal state */
130 #define stIDLE 1 /* Idle mode is active */
131 #define stPD 2 /* Power Down mode is active */
133 /* Result of instruction simulation */
134 #define resGO 0 /* OK, go on */
135 #define resWDTRESET 1 /* Reseted by WDT */
136 #define resINTERRUPT 2 /* Interrupt accepted */
137 #define resSTOP 100 /* Stop if result greather then this */
138 #define resHALT 101 /* Serious error, halt CPU */
139 #define resINV_ADDR 102 /* Invalid indirect address */
140 #define resSTACK_OV 103 /* Stack overflow */
141 #define resBREAKPOINT 104 /* Breakpoint */
142 #define resUSER 105 /* Stopped by user */
143 #define resINV_INST 106 /* Invalid instruction */
144 #define resBITADDR 107 /* Bit address is uninterpretable */
145 #define resERROR 108 /* Error happened during instruction exec */
147 #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
149 //#define IRAM_SIZE 256 /* Size of Internal RAM */
150 //#define SFR_SIZE 256 /* Size of SFR area */
151 //#define SFR_START 128 /* Start address of SFR area */
152 //#define ERAM_SIZE 256 /* Size of ERAM in 51R */
153 //#define XRAM_SIZE 0x10000 /* Size of External RAM */
154 //#define IROM_SIZE 0x1000 /* Size of Internal ROM */
155 //#define EROM_SIZE 0x10000 /* Size of External ROM */
158 /* Type of breakpoints */
188 // t_addr wx; /* write to XRAM at this address, else -1 */
189 // t_addr rx; /* read from XRAM at this address, else -1 */
190 // t_addr wi; /* write to IRAM at this address, else -1 */
191 // t_addr ri; /* read from IRAM at this address, else -1 */
192 // t_addr ws; /* write to SFR at this address, else -1 */
193 // t_addr rs; /* read from SFR at this address, else -1 */
194 // t_addr rc; /* read from ROM at this address, else -1 */
197 /* Interrupt levels */
198 //#define IT_NO -1 /* not in interroupt service */
199 #define IT_LOW 1 /* low level interrupt service */
200 #define IT_HIGH 2 /* service of high priority interrupt */
202 /* cathegories of hw elements (peripherials) */
209 HW_INTERRUPT = 0x0020,
213 // Events that can happen in peripherals
222 #define HWF_INSIDE 0x0001
223 #define HWF_OUTSIDE 0x0002
224 #define HWF_MISC 0x0004
229 case_upper, /* all is upper case */
230 case_lower, /* all is lower case */
231 case_case /* first letter is upper, others are lower case */
237 /* End of stypes.h */