2 * Simulator of microcontrollers (stypes.h)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
34 typedef unsigned char uchar;
35 typedef unsigned int uint;
36 typedef unsigned long ulong;
37 typedef TYPE_UDWORD t_addr; /* 32 bit max */
38 typedef TYPE_UWORD t_mem; /* 16 bit max */
39 typedef TYPE_WORD t_smem; /* signed 16 bit memory */
47 // table of dissassembled instructions
56 // table entry of SFR and BIT names
76 #define CPU_51R 0x0010
77 #define CPU_89C51R 0x0020
78 #define CPU_251 0x0040
79 #define CPU_DS390 0x0080
80 #define CPU_DS390F 0x0100
81 #define CPU_ALL_51 (CPU_51|CPU_31)
82 #define CPU_ALL_52 (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|CPU_DS390|CPU_DS390F)
84 #define CPU_AVR 0x0001
85 #define CPU_ALL_AVR (CPU_AVR)
87 #define CPU_Z80 0x0001
88 #define CPU_ALL_Z80 (CPU_Z80)
91 #define CPU_ALL_XA (CPU_XA)
93 #define CPU_CMOS 0x0001
94 #define CPU_HMOS 0x0002
96 /* Classes of memories, this is index on the list */
108 // States of simulator
110 #define SIM_GO 0x01 // Processor is running
111 #define SIM_QUIT 0x02 // Program must exit
114 #define stGO 0 /* Normal state */
115 #define stIDLE 1 /* Idle mode is active */
116 #define stPD 2 /* Power Down mode is active */
118 /* Result of instruction simulation */
119 #define resGO 0 /* OK, go on */
120 #define resWDTRESET 1 /* Reseted by WDT */
121 #define resINTERRUPT 2 /* Interrupt accepted */
122 #define resSTOP 100 /* Stop if result greather then this */
123 #define resHALT 101 /* Serious error, halt CPU */
124 #define resINV_ADDR 102 /* Invalid indirect address */
125 #define resSTACK_OV 103 /* Stack overflow */
126 #define resBREAKPOINT 104 /* Breakpoint */
127 #define resUSER 105 /* Stopped by user */
128 #define resINV_INST 106 /* Invalid instruction */
129 #define resBITADDR 107 /* Bit address is uninterpretable */
131 #define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
133 #define IRAM_SIZE 256 /* Size of Internal RAM */
134 #define SFR_SIZE 256 /* Size of SFR area */
135 #define SFR_START 128 /* Start address of SFR area */
136 #define ERAM_SIZE 256 /* Size of ERAM in 51R */
137 #define XRAM_SIZE 0x10000 /* Size of External RAM */
138 //#define IROM_SIZE 0x1000 /* Size of Internal ROM */
139 #define EROM_SIZE 0x10000 /* Size of External ROM */
142 /* Type of breakpoints */
172 // t_addr wx; /* write to XRAM at this address, else -1 */
173 // t_addr rx; /* read from XRAM at this address, else -1 */
174 // t_addr wi; /* write to IRAM at this address, else -1 */
175 // t_addr ri; /* read from IRAM at this address, else -1 */
176 // t_addr ws; /* write to SFR at this address, else -1 */
177 // t_addr rs; /* read from SFR at this address, else -1 */
178 // t_addr rc; /* read from ROM at this address, else -1 */
181 /* Interrupt levels */
182 //#define IT_NO -1 /* not in interroupt service */
183 #define IT_LOW 1 /* low level interrupt service */
184 #define IT_HIGH 2 /* service of high priority interrupt */
186 /* cathegories of hw elements (peripherials) */
193 HW_INTERRUPT = 0x0020,
197 // Events that can happen in peripherals
206 #define HWF_INSIDE 0x0001
207 #define HWF_OUTSIDE 0x0002
208 #define HWF_MISC 0x0004
213 /* End of stypes.h */