2 * Simulator of microcontrollers (uc89c51r.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
33 #include "uc89c51rcl.h"
38 t_uc89c51r::t_uc89c51r(int Itype, int Itech, class cl_sim *asim):
39 t_uc51r(Itype, Itech, asim)
41 /*it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF4, 0x0033, false,
43 it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF3, 0x0033, false,
45 it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF2, 0x0033, false,
47 it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF1, 0x0033, false,
49 it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCCF0, 0x0033, false,
51 it_sources->add_at(4, new cl_it_src(bmEC, CCON, bmCF, 0x0033, false,
58 t_uc89c51r::reset(void)
61 mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
62 mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
63 mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
64 mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
65 mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
67 dpl0= dph0= dpl1= dph1= 0;
68 set_mem(MEM_SFR, IPH, 0);
72 t_uc89c51r::proc_write(uchar *addr)
74 t_uc89c51r::mk_hw_elements(void)
78 t_uc51r::proc_write(addr);
80 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP0L]))
81 mem(MEM_SFR)->set_bit0(CCAPM0, bmECOM);
82 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP0H]))
83 mem(MEM_SFR)->set_bit1(CCAPM0, bmECOM);
85 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP1L]))
86 mem(MEM_SFR)->set_bit0(CCAPM1, bmECOM);
87 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP1H]))
88 mem(MEM_SFR)->set_bit1(CCAPM1, bmECOM);
90 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP2L]))
91 mem(MEM_SFR)->set_bit0(CCAPM2, bmECOM);
92 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP2H]))
93 mem(MEM_SFR)->set_bit1(CCAPM2, bmECOM);
95 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP3L]))
96 mem(MEM_SFR)->set_bit0(CCAPM3, bmECOM);
97 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP3H]))
98 mem(MEM_SFR)->set_bit1(CCAPM3, bmECOM);
100 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP4L]))
101 mem(MEM_SFR)->set_bit0(CCAPM4, bmECOM);
102 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[CCAP4H]))
103 mem(MEM_SFR)->set_bit1(CCAPM4, bmECOM);
109 if (addr == &(/*MEM(MEM_SFR)*/sfr->umem8[AUXR]))
110 mem(MEM_SFR)->set_bit0(AUXR, 0x04);
112 t_uc51r::mk_hw_elements();
113 hws->add(h= new cl_pca(this, 0));
115 /*hws->add(h= new cl_pca(this, 1));
117 hws->add(h= new cl_pca(this, 2));
119 hws->add(h= new cl_pca(this, 3));
121 hws->add(h= new cl_pca(this, 4));
123 hws->add(h= new cl_89c51r_dummy_hw(this));
130 t_uc89c51r::reset(void)
133 sfr->set_bit1(CCAPM0, bmECOM);
134 sfr->set_bit1(CCAPM1, bmECOM);
135 sfr->set_bit1(CCAPM2, bmECOM);
136 sfr->set_bit1(CCAPM3, bmECOM);
137 sfr->set_bit1(CCAPM4, bmECOM);
139 dpl0= dph0= dpl1= dph1= 0;
144 t_uc89c51r::it_priority(uchar ie_mask)
148 l= sfr->get(IP) & ie_mask;
149 h= sfr->get(IPH) & ie_mask;
162 t_uc89c51r::pre_inst(void)
164 if (sfr->get(AUXR1) & bmDPS)
178 t_uc89c51r::post_inst(void)
180 if (sfr->get(AUXR1) & bmDPS)
190 t_uc51r::post_inst();
198 * Calling inherited method to simulate timer #0, #1, #2 and then
199 * simulating Programmable Counter Array
205 t_uc89c51r::do_timers(int cycles)
210 if ((res= t_uc51r::do_timers(cycles)) != resGO)
212 return(do_pca(cycles));
215 cl_89c51r_dummy_hw::cl_89c51r_dummy_hw(class cl_uc *auc):
216 cl_hw(auc, HW_DUMMY, 0, "_89c51r_dummy")
222 t_uc89c51r::t0_overflow(void)
224 cl_89c51r_dummy_hw::init(void)
228 uchar cmod= get_mem(MEM_SFR, CMOD) & (bmCPS0|bmCPS1);
237 * Simulating Programmable Counter Array
241 t_uc89c51r::do_pca(int cycles)
244 uint ccon= get_mem(MEM_SFR, CCON);
248 if (state == stIDLE &&
252 switch (get_mem(MEM_SFR, CMOD) & (bmCPS1|bmCPS0))
255 ret= do_pca_counter(cycles);
258 ret= do_pca_counter(cycles*3);
261 ret= do_pca_counter(t0_overflows);
264 case (bmCPS0|bmCPS1):
265 if ((prev_p1 & bmECI) != 0 &
266 (get_mem(MEM_SFR, P1) & bmECI) == 0)
274 t_uc89c51r::do_pca_counter(int cycles)
278 class cl_mem *sfr= uc->mem(MEM_SFR);
282 fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
284 //auxr= sfr->register_hw(AUXR, this, 0);
285 register_cell(sfr, AUXR, &auxr, wtd_restore);
290 cl_89c51r_dummy_hw::write(class cl_cell *cell, t_mem *val)
293 auxr->set_bit0(0x04);
297 /* End of s51.src/uc89c51r.cc */