2 * Simulator of microcontrollers (uc89c51r.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
34 #include "uc89c51rcl.h"
40 cl_uc89c51r::cl_uc89c51r(int Itype, int Itech, class cl_sim *asim):
41 cl_uc51r(Itype, Itech, asim)
47 cl_uc89c51r::mk_hw_elements(void)
51 cl_uc52::mk_hw_elements();
52 hws->add(h= new cl_wdt(this, 0x3fff));
54 hws->add(h= new cl_pca(this, 0));
56 hws->add(h= new cl_89c51r_dummy_hw(this));
61 cl_uc89c51r::make_memories(void)
63 cl_uc52::make_memories();
68 cl_uc89c51r::reset(void)
71 sfr->set_bit1(CCAPM0, bmECOM);
72 sfr->set_bit1(CCAPM1, bmECOM);
73 sfr->set_bit1(CCAPM2, bmECOM);
74 sfr->set_bit1(CCAPM3, bmECOM);
75 sfr->set_bit1(CCAPM4, bmECOM);
77 dpl0= dph0= dpl1= dph1= 0;
82 cl_uc89c51r::it_priority(uchar ie_mask)
86 l= sfr->get(IP) & ie_mask;
87 h= sfr->get(IPH) & ie_mask;
100 cl_uc89c51r::pre_inst(void)
102 //printf("pre dptr0:%02X%02X dptr1:%02X%02X\n", dph0, dpl0, dph1, dpl1);
103 dps = (sfr->get(AUXR1) & bmDPS);
114 cl_uc51r::pre_inst();
118 cl_uc89c51r::post_inst(void)
130 dps = (sfr->get(AUXR1) & bmDPS);
141 //printf("post dptr0:%02X%02X dptr1:%02X%02X\n", dph0, dpl0, dph1, dpl1);
142 cl_uc51r::post_inst();
147 cl_uc89c51r::print_regs(class cl_console_base *con)
150 uchar data, acc, dps;
152 start= psw->get() & 0x18;
153 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
154 iram->dump(start, start+7, 8, con);
155 start= psw->get() & 0x18;
156 data= iram->get(iram->get(start));
157 con->dd_printf("%06x %02x %c",
158 iram->get(start), data, isprint(data)?data:'.');
161 con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x", acc, acc,
162 isprint(acc)?(acc):'.', sfr->get(B));
164 dps = sfr->get(AUXR1) & bmDPS;
165 data= xram->get(dph0*256+dpl0);
166 con->dd_printf(" %cDPTR0= 0x%02x%02x @DPTR0= 0x%02x %3d %c",
167 dps?' ':'*', dph0, dpl0,
168 data, data, isprint(data)?data:'.');
169 data= xram->get(dph1*256+dpl1);
170 con->dd_printf(" %cDPTR1= 0x%02x%02x @DPTR1= 0x%02x %3d %c\n",
171 dps?'*':' ', dph1, dpl1,
172 data, data, isprint(data)?data:'.');
174 data= iram->get(iram->get(start+1));
175 con->dd_printf("%06x %02x %c", iram->get(start+1), data,
176 isprint(data)?data:'.');
178 con->dd_printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
179 (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
180 (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
182 print_disass(PC, con);
189 cl_89c51r_dummy_hw::cl_89c51r_dummy_hw(class cl_uc *auc):
190 cl_hw(auc, HW_DUMMY, 0, "_89c51r_dummy")
194 cl_89c51r_dummy_hw::init(void)
196 class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
199 fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
201 //auxr= sfr->register_hw(AUXR, this, 0);
202 register_cell(sfr, AUXR1, &auxr1, wtd_restore);
207 cl_89c51r_dummy_hw::write(class cl_memory_cell *cell, t_mem *val)
210 auxr1->set_bit0(0x04);
214 /* End of s51.src/uc89c51r.cc */