2 * Simulator of microcontrollers (uc52.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 * Making an 8052 CPU object
42 t_uc52::t_uc52(int Itype, int Itech, class cl_sim *asim):
43 t_uc51(Itype, Itech, asim)
45 it_sources->add(new cl_it_src(bmET2, T2CON, bmTF2, 0x002b, false,
47 exf2it= new cl_it_src(bmET2, T2CON, bmEXF2, 0x002b, false,
49 it_sources->add(exf2it);
54 t_uc52::mk_hw_elements(void)
58 t_uc51::mk_hw_elements();
59 hws->add(h= new cl_timer2(this));
65 * Calculating address of indirectly addressed IRAM cell
67 * If CPU is 8051 and addr is over 127, it must be illegal! But in 52
73 t_uc52::get_indirect(uchar addr, int *res)
76 return(&(MEM(MEM_IRAM)[addr]));
83 * Calling inherited method to simulate timer #0 and #1 and then
84 * simulating timer #2.
89 t_uc52::do_timers(int cycles)
93 if ((res= t_uc51::do_timers(cycles)) != resGO)
95 return(do_timer2(cycles));
104 t_uc52::do_timer2(int cycles)
107 uint t2con= get_mem(MEM_SFR, T2CON);
110 if (!(t2con & bmTR2))
114 if (t2con & (bmRCLK | bmTCLK))
115 return(do_t2_baud(cycles));
117 /* Determining nr of input clocks */
118 if (!(t2con & bmTR2))
119 nocount= TRUE; // Timer OFF
123 // Counter mode, falling edge on P1.0 (T2)
124 if ((prev_p1 & bmT2) &&
125 !(get_mem(MEM_SFR, P1) & port_pins[1] & bmT2))
133 if (t2con & bmCP_RL2)
134 do_t2_capture(&cycles, nocount);
136 do_t2_reload(&cycles, nocount);
144 * Baud rate generator mode of Timer #2
148 t_uc52::do_t2_baud(int cycles)
150 uint t2con= get_mem(MEM_SFR, T2CON);
151 uint p1= get_mem(MEM_SFR, P1);
153 /* Baud Rate Generator */
154 if ((prev_p1 & bmT2EX) &&
155 !(p1 & port_pins[1] & bmT2EX) &&
157 mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
160 if ((prev_p1 & bmT2) &&
161 !(p1 & port_pins[1] & bmT2))
171 if (!++(MEM(MEM_SFR)[TL2]))
172 if (!++(MEM(MEM_SFR)[TH2]))
174 MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H];
175 MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L];
185 * Capture function of Timer #2
189 t_uc52::do_t2_capture(int *cycles, bool nocount)
191 uint p1= get_mem(MEM_SFR, P1);
192 uint t2con= get_mem(MEM_SFR, T2CON);
199 if (!++(MEM(MEM_SFR)[TL2]))
201 if (!++(MEM(MEM_SFR)[TH2]))
202 mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
206 if ((prev_p1 & bmT2EX) &&
207 !(p1 & port_pins[1] & bmT2EX) &&
210 MEM(MEM_SFR)[RCAP2H]= MEM(MEM_SFR)[TH2];
211 MEM(MEM_SFR)[RCAP2L]= MEM(MEM_SFR)[TL2];
212 mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
213 prev_p1&= ~bmT2EX; // Falling edge has been handled
219 * Auto Reload mode of Timer #2, counting UP
223 t_uc52::do_t2_reload(int *cycles, bool nocount)
228 /* Auto-Relode mode */
234 if (!++(MEM(MEM_SFR)[TL2]))
236 if (!++(MEM(MEM_SFR)[TH2]))
238 mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
244 if ((prev_p1 & bmT2EX) &&
245 !(get_mem(MEM_SFR, P1) & port_pins[1] & bmT2EX) &&
246 (get_mem(MEM_SFR, T2CON) & bmEXEN2))
249 mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
250 prev_p1&= ~bmT2EX; // Falling edge has been handled
255 MEM(MEM_SFR)[TH2]= MEM(MEM_SFR)[RCAP2H];
256 MEM(MEM_SFR)[TL2]= MEM(MEM_SFR)[RCAP2L];
266 t_uc52::serial_bit_cnt(int mode)
269 int *tr_src= 0, *rec_src= 0;
276 rec_src= &s_rec_tick;
280 divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
281 tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1);
282 rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1);
285 divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
287 rec_src= &s_rec_tick;
292 while (*tr_src >= divby)
300 while (*rec_src >= divby)
310 /* End of s51.src/uc52.cc */