2 * Simulator of microcontrollers (uc51.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
37 #include <sys/types.h>
56 #include "interruptcl.h"
60 * Making a new micro-controller and reset it
63 t_uc51::t_uc51(int Itype, int Itech, class cl_sim *asim):
72 debug= asim->get_iarg('V', 0);
74 options->add(new cl_bool_opt(&debug, "verbose", "Verbose flag."));
75 options->add(new cl_bool_opt(&stop_at_it, "stopit",
76 "Stop if interrupt accepted."));
77 options->add(new cl_cons_debug_opt(asim, "debug",
78 "Debug messages appears on this console."));
80 serial_in = (FILE*)asim->get_parg(0, "Ser_in");
81 serial_out= (FILE*)asim->get_parg(0, "Ser_out");
84 // making `serial' unbuffered
85 if (setvbuf(serial_in, NULL, _IONBF, 0))
86 perror("Unbuffer serial input channel");
88 if ((i= fcntl(fileno(serial_in), F_GETFL, 0)) < 0)
89 perror("Get flags of serial input");
91 if (fcntl(fileno(serial_in), F_SETFL, i) < 0)
92 perror("Set flags of serial input");
93 // switching terminal to noncanonical mode
94 if (isatty(fileno(serial_in)))
96 tcgetattr(fileno(serial_in), &saved_attributes_in);
97 tcgetattr(fileno(serial_in), &tattr);
98 tattr.c_lflag&= ~(ICANON|ECHO);
100 tattr.c_cc[VTIME]= 0;
101 tcsetattr(fileno(serial_in), TCSAFLUSH, &tattr);
104 fprintf(stderr, "Warning: serial input interface connected to a "
105 "non-terminal file.\n");
109 // making `serial' unbuffered
110 if (setvbuf(serial_out, NULL, _IONBF, 0))
111 perror("Unbuffer serial output channel");
112 // setting O_NONBLOCK
113 if ((i= fcntl(fileno(serial_out), F_GETFL, 0)) < 0)
114 perror("Get flags of serial output");
116 if (fcntl(fileno(serial_out), F_SETFL, i) < 0)
117 perror("Set flags of serial output");
118 // switching terminal to noncanonical mode
119 if (isatty(fileno(serial_out)))
121 tcgetattr(fileno(serial_out), &saved_attributes_out);
122 tcgetattr(fileno(serial_out), &tattr);
123 tattr.c_lflag&= ~(ICANON|ECHO);
124 tattr.c_cc[VMIN] = 1;
125 tattr.c_cc[VTIME]= 0;
126 tcsetattr(fileno(serial_out), TCSAFLUSH, &tattr);
129 fprintf(stderr, "Warning: serial output interface connected to a "
130 "non-terminal file.\n");
133 for (i= 0; i < 4; i++)
135 it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true,
137 it_sources->add(new cl_it_src(bmET0, TCON, bmTF0, 0x000b, true,
139 it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true,
141 it_sources->add(new cl_it_src(bmET1, TCON, bmTF1, 0x001b, true,
143 it_sources->add(new cl_it_src(bmES , SCON, bmTI , 0x0023, false,
145 it_sources->add(new cl_it_src(bmES , SCON, bmRI , 0x0023, false,
151 * Initializing. Virtual calls go here
152 * This method must be called first after object creation.
163 static char id_string_51[100];
166 t_uc51::id_string(void)
170 for (i= 0; cpus_51[i].type_str != NULL && cpus_51[i].type != type; i++) ;
171 sprintf(id_string_51, "%s %s",
172 cpus_51[i].type_str?cpus_51[i].type_str:"51",
173 (technology==CPU_HMOS)?"HMOS":"CMOS");
174 return(id_string_51);
178 t_uc51::mk_hw_elements(void)
182 hws->add(h= new cl_timer0(this));
184 hws->add(h= new cl_timer1(this));
186 hws->add(h= new cl_serial(this));
188 hws->add(h= new cl_port(this, 0));
190 hws->add(h= new cl_port(this, 1));
192 hws->add(h= new cl_port(this, 2));
194 hws->add(h= new cl_port(this, 3));
196 hws->add(h= new cl_interrupt(this));
201 t_uc51::mk_mem(enum mem_class type)
203 class cl_mem *m= cl_uc::mk_mem(type);
206 if (type == MEM_IRAM)
213 * Destroying the micro-controller object
216 t_uc51::~t_uc51(void)
220 if (isatty(fileno(serial_out)))
221 tcsetattr(fileno(serial_out), TCSANOW, &saved_attributes_out);
226 if (isatty(fileno(serial_in)))
227 tcsetattr(fileno(serial_in), TCSANOW, &saved_attributes_in);
234 * Writing data to EROM
238 t_uc51::write_rom(uint addr, ulong data)
240 if (addr < EROM_SIZE)
241 set_mem(MEM_ROM, addr, data);
246 * Disassembling an instruction
250 t_uc51::dis_tbl(void)
256 t_uc51::sfr_tbl(void)
262 t_uc51::bit_tbl(void)
268 t_uc51::disass(uint addr, char *sep)
270 char work[256], temp[20], c[2];
271 char *buf, *p, *b, *t;
272 uint code= get_mem(MEM_ROM, addr);
275 b= dis_tbl()[code].mnemonic;
283 case 'A': // absolute address
284 sprintf(temp, "%04lx",
286 (((code>>5)&0x07)*256 +
287 get_mem(MEM_ROM, addr+1)));
289 case 'l': // long address
290 sprintf(temp, "%04lx",
291 get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2));
293 case 'a': // addr8 (direct address) at 2nd byte
294 if (!get_name(get_mem(MEM_ROM, addr+1), sfr_tbl(), temp))
295 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
297 case '8': // addr8 (direct address) at 3rd byte
298 if (!get_name(get_mem(MEM_ROM, addr+2), sfr_tbl(), temp))
299 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
300 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2));
302 case 'b': // bitaddr at 2nd byte
303 if (get_name(get_mem(MEM_ROM, addr+1), bit_tbl(), temp))
305 if (get_name(get_bitidx(get_mem(MEM_ROM, addr+1)),
309 sprintf(c, "%1ld", get_mem(MEM_ROM, addr+1)&0x07);
313 sprintf(temp, "%02x.%ld",
314 get_bitidx(get_mem(MEM_ROM, addr+1)),
315 get_mem(MEM_ROM, addr+1)&0x07);
317 case 'r': // rel8 address at 2nd byte
318 sprintf(temp, "%04x",
319 addr+2+(signed char)(get_mem(MEM_ROM, addr+1)));
321 case 'R': // rel8 address at 3rd byte
322 sprintf(temp, "%04x",
323 addr+3+(signed char)(get_mem(MEM_ROM, addr+2)));
325 case 'd': // data8 at 2nd byte
326 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
328 case 'D': // data8 at 3rd byte
329 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2));
331 case '6': // data16 at 2nd(H)-3rd(L) byte
332 sprintf(temp, "%04lx",
333 get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2));
348 p= strchr(work, ' ');
355 buf= (char *)malloc(6+strlen(p)+1);
357 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
358 for (p= work, b= buf; *p != ' '; p++, b++)
364 while (strlen(buf) < 6)
374 t_uc51::print_disass(uint addr, class cl_console *con)
379 uint code= get_mem(MEM_ROM, addr);
382 dis= disass(addr, NULL);
384 con->printf("%c", (b->perm == brkFIX)?'F':'D');
387 con->printf("%c %06x %02x",
388 inst_at(addr)?' ':'*',
390 for (i= 1; i < inst_length(code); i++)
391 con->printf(" %02x", get_mem(MEM_ROM, addr+i));
397 con->printf(" %s\n", dis);
402 t_uc51::print_regs(class cl_console *con)
407 start= sfr->get(PSW) & 0x18;
408 dump_memory(iram, &start, start+7, 8, sim->cmd_out(), sim);
409 start= sfr->get(PSW) & 0x18;
410 data= iram->get(iram->get(start));
411 con->printf("%06x %02x %c",
412 iram->get(start), data, isprint(data)?data:'.');
414 con->printf(" ACC= 0x%02x %3d %c B= 0x%02x", sfr->get(ACC), sfr->get(ACC),
415 isprint(sfr->get(ACC))?(sfr->get(ACC)):'.', sfr->get(B));
417 data= get_mem(MEM_XRAM, sfr->get(DPH)*256+sfr->get(DPL));
418 con->printf(" DPTR= 0x%02x%02x @DPTR= 0x%02x %3d %c\n", sfr->get(DPH),
419 sfr->get(DPL), data, data, isprint(data)?data:'.');
421 data= iram->get(iram->get(start+1));
422 con->printf("%06x %02x %c", iram->get(start+1), data,
423 isprint(data)?data:'.');
425 con->printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
426 (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
427 (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
429 print_disass(PC, con);
434 * Resetting the micro-controller
454 s_sending = DD_FALSE;
455 s_receiving= DD_FALSE;
462 * Setting up SFR area to reset value
466 t_uc51::clear_sfr(void)
470 for (i= 0; i < SFR_SIZE; i++)
477 prev_p1= port_pins[1] & sfr->get(P1);
478 prev_p3= port_pins[3] & sfr->get(P3);
483 * Analyzing code and settig up instruction map
487 t_uc51::analyze(uint addr)
490 struct dis_entry *tabl;
492 code= get_mem(MEM_ROM, addr);
493 tabl= &(dis_tbl()[code]);
494 while (!inst_at(addr) &&
495 code != 0xa5 /* break point */)
498 switch (tabl->branch)
501 analyze((addr & 0xf800)|
502 ((get_mem(MEM_ROM, addr+1)&0x07)*256+
503 get_mem(MEM_ROM, addr+2)));
504 analyze(addr+tabl->length);
507 addr= (addr & 0xf800)|
508 ((get_mem(MEM_ROM, addr+1) & 0x07)*256 + get_mem(MEM_ROM, addr+2));
511 analyze(get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2));
512 analyze(addr+tabl->length);
515 addr= get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2);
517 case 'r': // reljmp (2nd byte)
518 analyze((addr + (signed char)(get_mem(MEM_ROM, addr+1))) &
520 analyze(addr+tabl->length);
522 case 'R': // reljmp (3rd byte)
524 (signed char)(get_mem(MEM_ROM, addr+2)))&(EROM_SIZE-1));
525 analyze(addr+tabl->length);
530 target= get_mem(MEM_ROM, addr+1);
532 addr= (addr+target)&(EROM_SIZE-1);
538 addr= (addr+tabl->length) & (EROM_SIZE - 1);
541 code= get_mem(MEM_ROM, addr);
542 tabl= &(dis_tbl()[code]);
548 * Inform hardware elements that `cycles' machine cycles have elapsed
552 t_uc51::tick(int cycles)
558 s_tr_tick+= (l= cycles * clock_per_cycle());
565 * Correcting direct address
567 * This function returns address of addressed element which can be an IRAM
572 t_uc51::get_direct(t_mem addr, t_addr *ev_i, t_addr *ev_s)
574 if (addr < SFR_START)
575 return(&(MEM(MEM_IRAM)[*ev_i= addr]));
577 return(&(MEM(MEM_SFR)[*ev_s= addr]));
581 * Calculating address of indirectly addressed IRAM cell
582 * If CPU is 8051 and addr is over 127, it must be illegal!
586 t_uc51::get_indirect(uchar addr, int *res)
588 if (addr >= SFR_START)
592 return(&(MEM(MEM_IRAM)[addr]));
597 * Calculating address of specified register cell in IRAM
601 t_uc51::get_reg(uchar regnum)
603 return(&(MEM(MEM_IRAM)[(sfr->get(PSW) & (bmRS0|bmRS1)) |
608 t_uc51::get_reg(uchar regnum, t_addr *event)
610 return(&(MEM(MEM_IRAM)[*event= (sfr->get(PSW) & (bmRS0|bmRS1)) |
616 * Calculating address of IRAM or SFR cell which contains addressed bit
617 * Next function returns index of cell which contains addressed bit.
621 t_uc51::get_bit(uchar bitaddr)
624 return(&(MEM(MEM_IRAM)[(bitaddr/8)+32]));
625 return(&(MEM(MEM_SFR)[bitaddr & 0xf8]));
629 t_uc51::get_bit(uchar bitaddr, t_addr *ev_i, t_addr *ev_s)
632 return(&(MEM(MEM_IRAM)[*ev_i= (bitaddr/8)+32]));
633 return(&(MEM(MEM_SFR)[*ev_s= bitaddr & 0xf8]));
637 t_uc51::get_bitidx(uchar bitaddr)
640 return((bitaddr/8)+32);
641 return(bitaddr & 0xf8);
646 * Processing write operation to IRAM
648 * It starts serial transmition if address is in SFR and it is
649 * SBUF. Effect on IE is also checked.
653 t_uc51::proc_write(uchar *addr)
655 if (addr == &((sfr->umem8)[SBUF]))
657 s_out= sfr->get(SBUF);
663 if (addr == &((sfr->umem8)[IE]))
668 t_uc51::proc_write_sp(uchar val)
672 sp_avg= (sp_avg+val)/2;
677 * Reading IRAM or SFR, but if address points to a port, it reads
678 * port pins instead of port latches
682 t_uc51::read(uchar *addr)
684 if (addr == &(MEM(MEM_SFR)[P0]))
685 return(get_mem(MEM_SFR, P0) & port_pins[0]);
686 if (addr == &(MEM(MEM_SFR)[P1]))
687 return(get_mem(MEM_SFR, P1) & port_pins[1]);
688 if (addr == &(MEM(MEM_SFR)[P2]))
689 return(get_mem(MEM_SFR, P2) & port_pins[2]);
690 if (addr == &(MEM(MEM_SFR)[P3]))
691 return(get_mem(MEM_SFR, P3) & port_pins[3]);
697 * Fetching one instruction and executing it
701 t_uc51::pre_inst(void)
703 event_at.wi= (t_addr)-1;
704 event_at.ri= (t_addr)-1;
705 event_at.wx= (t_addr)-1;
706 event_at.rx= (t_addr)-1;
707 event_at.ws= (t_addr)-1;
708 event_at.rs= (t_addr)-1;
709 event_at.rc= (t_addr)-1;
713 t_uc51::exec_inst(void)
720 return(resBREAKPOINT);
724 case 0x00: res= inst_nop(code); break;
725 case 0x01: case 0x21: case 0x41: case 0x61:
726 case 0x81: case 0xa1: case 0xc1: case 0xe1:res=inst_ajmp_addr(code);break;
727 case 0x02: res= inst_ljmp(code); break;
728 case 0x03: res= inst_rr(code); break;
729 case 0x04: res= inst_inc_a(code); break;
730 case 0x05: res= inst_inc_addr(code); break;
731 case 0x06: case 0x07: res= inst_inc_$ri(code); break;
732 case 0x08: case 0x09: case 0x0a: case 0x0b:
733 case 0x0c: case 0x0d: case 0x0e: case 0x0f: res= inst_inc_rn(code); break;
734 case 0x10: res= inst_jbc_bit_addr(code); break;
735 case 0x11: case 0x31: case 0x51: case 0x71:
736 case 0x91: case 0xb1: case 0xd1: case 0xf1:res=inst_acall_addr(code);break;
737 case 0x12: res= inst_lcall(code, 0); break;
738 case 0x13: res= inst_rrc(code); break;
739 case 0x14: res= inst_dec_a(code); break;
740 case 0x15: res= inst_dec_addr(code); break;
741 case 0x16: case 0x17: res= inst_dec_$ri(code); break;
742 case 0x18: case 0x19: case 0x1a: case 0x1b:
743 case 0x1c: case 0x1d: case 0x1e: case 0x1f: res= inst_dec_rn(code); break;
744 case 0x20: res= inst_jb_bit_addr(code); break;
745 case 0x22: res= inst_ret(code); break;
746 case 0x23: res= inst_rl(code); break;
747 case 0x24: res= inst_add_a_$data(code); break;
748 case 0x25: res= inst_add_a_addr(code); break;
749 case 0x26: case 0x27: res= inst_add_a_$ri(code); break;
750 case 0x28: case 0x29: case 0x2a: case 0x2b:
751 case 0x2c: case 0x2d: case 0x2e: case 0x2f:res= inst_add_a_rn(code);break;
752 case 0x30: res= inst_jnb_bit_addr(code); break;
753 case 0x32: res= inst_reti(code); break;
754 case 0x33: res= inst_rlc(code); break;
755 case 0x34: res= inst_addc_a_$data(code); break;
756 case 0x35: res= inst_addc_a_addr(code); break;
757 case 0x36: case 0x37: res= inst_addc_a_$ri(code); break;
758 case 0x38: case 0x39: case 0x3a: case 0x3b:
759 case 0x3c: case 0x3d: case 0x3e: case 0x3f:res= inst_addc_a_rn(code);break;
760 case 0x40: res= inst_jc_addr(code); break;
761 case 0x42: res= inst_orl_addr_a(code); break;
762 case 0x43: res= inst_orl_addr_$data(code); break;
763 case 0x44: res= inst_orl_a_$data(code); break;
764 case 0x45: res= inst_orl_a_addr(code); break;
765 case 0x46: case 0x47: res= inst_orl_a_$ri(code); break;
766 case 0x48: case 0x49: case 0x4a: case 0x4b:
767 case 0x4c: case 0x4d: case 0x4e: case 0x4f: res= inst_orl_a_rn(code);break;
768 case 0x50: res= inst_jnc_addr(code); break;
769 case 0x52: res= inst_anl_addr_a(code); break;
770 case 0x53: res= inst_anl_addr_$data(code); break;
771 case 0x54: res= inst_anl_a_$data(code); break;
772 case 0x55: res= inst_anl_a_addr(code); break;
773 case 0x56: case 0x57: res= inst_anl_a_$ri(code); break;
774 case 0x58: case 0x59: case 0x5a: case 0x5b:
775 case 0x5c: case 0x5d: case 0x5e: case 0x5f: res= inst_anl_a_rn(code);break;
776 case 0x60: res= inst_jz_addr(code); break;
777 case 0x62: res= inst_xrl_addr_a(code); break;
778 case 0x63: res= inst_xrl_addr_$data(code); break;
779 case 0x64: res= inst_xrl_a_$data(code); break;
780 case 0x65: res= inst_xrl_a_addr(code); break;
781 case 0x66: case 0x67: res= inst_xrl_a_$ri(code); break;
782 case 0x68: case 0x69: case 0x6a: case 0x6b:
783 case 0x6c: case 0x6d: case 0x6e: case 0x6f: res= inst_xrl_a_rn(code);break;
784 case 0x70: res= inst_jnz_addr(code); break;
785 case 0x72: res= inst_orl_c_bit(code); break;
786 case 0x73: res= inst_jmp_$a_dptr(code); break;
787 case 0x74: res= inst_mov_a_$data(code); break;
788 case 0x75: res= inst_mov_addr_$data(code); break;
789 case 0x76: case 0x77: res= inst_mov_$ri_$data(code); break;
790 case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c:
791 case 0x7d: case 0x7e: case 0x7f: res=inst_mov_rn_$data(code); break;
792 case 0x80: res= inst_sjmp(code); break;
793 case 0x82: res= inst_anl_c_bit(code); break;
794 case 0x83: res= inst_movc_a_$a_pc(code); break;
795 case 0x84: res= inst_div_ab(code); break;
796 case 0x85: res= inst_mov_addr_addr(code); break;
797 case 0x86: case 0x87: res= inst_mov_addr_$ri(code); break;
798 case 0x88: case 0x89: case 0x8a: case 0x8b:
799 case 0x8c: case 0x8d: case 0x8e: case 0x8f:res=inst_mov_addr_rn(code);break;
800 case 0x90: res= inst_mov_dptr_$data(code); break;
801 case 0x92: res= inst_mov_bit_c(code); break;
802 case 0x93: res= inst_movc_a_$a_dptr(code); break;
803 case 0x94: res= inst_subb_a_$data(code); break;
804 case 0x95: res= inst_subb_a_addr(code); break;
805 case 0x96: case 0x97: res= inst_subb_a_$ri(code); break;
806 case 0x98: case 0x99: case 0x9a: case 0x9b:
807 case 0x9c: case 0x9d: case 0x9e: case 0x9f:res= inst_subb_a_rn(code);break;
808 case 0xa2: res= inst_mov_c_bit(code); break;
809 case 0xa3: res= inst_inc_dptr(code); break;
810 case 0xa4: res= inst_mul_ab(code); break;
811 case 0xa5: res= inst_unknown(code); break;
812 case 0xa6: case 0xa7: res= inst_mov_$ri_addr(code); break;
813 case 0xa8: case 0xa9: case 0xaa: case 0xab:
814 case 0xac: case 0xad: case 0xae: case 0xaf:res=inst_mov_rn_addr(code);break;
815 case 0xb0: res= inst_anl_c_$bit(code); break;
816 case 0xb2: res= inst_cpl_bit(code); break;
817 case 0xb3: res= inst_cpl_c(code); break;
818 case 0xb4: res= inst_cjne_a_$data_addr(code); break;
819 case 0xb5: res= inst_cjne_a_addr_addr(code); break;
820 case 0xb6: case 0xb7: res= inst_cjne_$ri_$data_addr(code); break;
821 case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc:
822 case 0xbd: case 0xbe: case 0xbf: res=inst_cjne_rn_$data_addr(code); break;
823 case 0xc0: res= inst_push(code); break;
824 case 0xc2: res= inst_clr_bit(code); break;
825 case 0xc3: res= inst_clr_c(code); break;
826 case 0xc4: res= inst_swap(code); break;
827 case 0xc5: res= inst_xch_a_addr(code); break;
828 case 0xc6: case 0xc7: res= inst_xch_a_$ri(code); break;
829 case 0xc8: case 0xc9: case 0xca: case 0xcb:
830 case 0xcc: case 0xcd: case 0xce: case 0xcf: res= inst_xch_a_rn(code);break;
831 case 0xd0: res= inst_pop(code); break;
832 case 0xd2: res= inst_setb_bit(code); break;
833 case 0xd3: res= inst_setb_c(code); break;
834 case 0xd4: res= inst_da_a(code); break;
835 case 0xd5: res= inst_djnz_addr_addr(code); break;
836 case 0xd6: case 0xd7: res= inst_xchd_a_$ri(code); break;
837 case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc:
838 case 0xdd: case 0xde: case 0xdf: res=inst_djnz_rn_addr(code); break;
839 case 0xe0: res= inst_movx_a_$dptr(code); break;
840 case 0xe2: case 0xe3: res= inst_movx_a_$ri(code); break;
841 case 0xe4: res= inst_clr_a(code); break;
842 case 0xe5: res= inst_mov_a_addr(code); break;
843 case 0xe6: case 0xe7: res= inst_mov_a_$ri(code); break;
844 case 0xe8: case 0xe9: case 0xea: case 0xeb:
845 case 0xec: case 0xed: case 0xee: case 0xef: res= inst_mov_a_rn(code);break;
846 case 0xf0: res= inst_movx_$dptr_a(code); break;
847 case 0xf2: case 0xf3: res= inst_movx_$ri_a(code); break;
848 case 0xf4: res= inst_cpl_a(code); break;
849 case 0xf5: res= inst_mov_addr_a(code); break;
850 case 0xf6: case 0xf7: res= inst_mov_$ri_a(code); break;
851 case 0xf8: case 0xf9: case 0xfa: case 0xfb:
852 case 0xfc: case 0xfd: case 0xfe: case 0xff: res= inst_mov_rn_a(code);break;
854 res= inst_unknown(code);
863 * Simulating execution of next instruction
865 * This is an endless loop if requested number of steps is negative.
866 * In this case execution is stopped if an instruction results other
867 * status than GO. Execution can be stopped if `cmd_in' is not NULL
868 * and there is input available on that file. It is usefull if the
869 * command console is on a terminal. If input is available then a
870 * complete line is read and dropped out because input is buffered
871 * (inp_avail will be TRUE if ENTER is pressed) and it can confuse
872 * command interepter.
876 t_uc51::do_inst(int step)
879 while ((result == resGO) &&
892 result= check_events();
896 // tick hw in idle state
903 if ((res= do_interrupt()) != resGO)
909 ((ticks->ticks % 100000) < 50))
911 if (sim->cmd->input_avail_on_frozen())
916 if (sim->cmd->input_avail())
919 if (((result == resINTERRUPT) &&
929 //FIXME: tick outsiders eg. watchdog
930 if (sim->cmd->input_avail_on_frozen())
932 //fprintf(stderr,"uc: inp avail in PD mode, user stop\n");
941 t_uc51::post_inst(void)
943 uint tcon= sfr->get(TCON);
944 uint p3= sfr->get(P3);
948 // Read of SBUF must be serial input data
949 sfr->set(SBUF, s_in);
951 // Setting up external interrupt request bits (IEx)
954 // IE0 edge triggered
955 if ((prev_p3 & bm_INT0) &&
956 !(p3 & port_pins[3] & bm_INT0))
957 // falling edge on INT0
959 sim->cmd->debug("%g sec (%d clks): "
960 "Falling edge detected on INT0 (P3.2)\n",
961 get_rtime(), ticks->ticks);
962 sfr->set_bit1(TCON, bmIE0);
967 // IE0 level triggered
968 if (p3 & port_pins[3] & bm_INT0)
969 sfr->set_bit0(TCON, bmIE0);
971 sfr->set_bit1(TCON, bmIE0);
975 // IE1 edge triggered
976 if ((prev_p3 & bm_INT1) &&
977 !(p3 & port_pins[3] & bm_INT1))
978 // falling edge on INT1
979 sfr->set_bit1(TCON, bmIE1);
983 // IE1 level triggered
984 if (p3 & port_pins[3] & bm_INT1)
985 sfr->set_bit0(TCON, bmIE1);
987 sfr->set_bit1(TCON, bmIE1);
989 prev_p3= p3 & port_pins[3];
990 prev_p1= p3 & port_pins[1];
995 * Setting up parity flag
999 t_uc51::set_p_flag(void)
1007 for (i= 0; i < 8; i++)
1013 SET_BIT(p, PSW, bmP);
1017 * Simulating hardware elements
1021 t_uc51::do_hardware(int cycles)
1025 if ((res= do_timers(cycles)) != resGO)
1027 if ((res= do_serial(cycles)) != resGO)
1029 return(do_wdt(cycles));
1038 t_uc51::serial_bit_cnt(int mode)
1040 int /*mode,*/ divby= 12;
1041 int *tr_src= 0, *rec_src= 0;
1043 //mode= sfr->get(SCON) >> 6;
1048 tr_src = &s_tr_tick;
1049 rec_src= &s_rec_tick;
1053 divby = (sfr->get(PCON)&bmSMOD)?16:32;
1058 divby = (sfr->get(PCON)&bmSMOD)?16:32;
1059 tr_src = &s_tr_tick;
1060 rec_src= &s_rec_tick;
1065 while (*tr_src >= divby)
1073 while (*rec_src >= divby)
1084 * Simulating serial line
1088 t_uc51::do_serial(int cycles)
1092 uint scon= sfr->get(SCON);
1108 serial_bit_cnt(mode);
1112 s_sending= DD_FALSE;
1113 sfr->set_bit1(SCON, bmTI);
1116 putc(s_out, serial_out);
1121 if ((scon & bmREN) &&
1125 fd_set set; static struct timeval timeout= {0,0};
1127 FD_SET(fileno(serial_in), &set);
1128 int i= select(fileno(serial_in)+1, &set, NULL, NULL, &timeout);
1130 FD_ISSET(fileno(serial_in), &set))
1132 s_receiving= DD_TRUE;
1134 s_rec_tick= s_rec_t1= 0;
1138 (s_rec_bit >= bits))
1140 if (::read(fileno(serial_in), &c, 1) == 1)
1143 sfr->set(SBUF, s_in);
1146 s_receiving= DD_FALSE;
1153 t_uc51::received(int c)
1155 sfr->set_bit1(SCON, bmRI);
1164 t_uc51::do_timers(int cycles)
1168 if ((res= do_timer0(cycles)) != resGO)
1170 return(do_timer1(cycles));
1175 * Simulating timer 0
1179 t_uc51::do_timer0(int cycles)
1181 uint tmod= sfr->get(TMOD);
1182 uint tcon= sfr->get(TCON);
1183 uint p3= sfr->get(P3);
1185 if (((tmod & bmGATE0) &&
1186 (p3 & port_pins[3] & bm_INT0)) ||
1189 if (!(tmod & bmC_T0) ||
1190 ((prev_p3 & bmT0) &&
1191 !(p3 & port_pins[3] & bmT0)))
1193 if (!(tmod & bmM00) &&
1200 // mod 0, TH= 8 bit t/c, TL= 5 bit precounter
1201 (MEM(MEM_SFR)[TL0])++;
1202 if (sfr->get(TL0) > 0x1f)
1204 sfr->set_bit0(TL0, ~0x1f);
1205 if (!++(MEM(MEM_SFR)[TH0]))
1207 sfr->set_bit1(TCON, bmTF0);
1213 else if ((tmod & bmM00) &&
1220 // mod 1 TH+TL= 16 bit t/c
1221 if (!++(MEM(MEM_SFR)[TL0]))
1223 if (!++(MEM(MEM_SFR)[TH0]))
1225 sfr->set_bit1(TCON, bmTF0);
1231 else if (!(tmod & bmM00) &&
1238 // mod 2 TL= 8 bit t/c auto reload from TH
1239 if (!++(MEM(MEM_SFR)[TL0]))
1241 sfr->set(TL0, sfr->get(TH0));
1242 sfr->set_bit1(TCON, bmTF0);
1249 // mod 3 TL= 8 bit t/c
1250 // TH= 8 bit timer controlled with T1's bits
1251 if (!++(MEM(MEM_SFR)[TL0]))
1253 sfr->set_bit1(TCON, bmTF0);
1259 if ((tmod & bmM00) &&
1262 if (((tmod & bmGATE1) &&
1263 (p3 & port_pins[3] & bm_INT1)) ||
1266 if (!++(MEM(MEM_SFR)[TH0]))
1268 sfr->set_bit1(TCON, bmTF1);
1279 * Called every time when T0 overflows
1283 t_uc51::t0_overflow(void)
1290 * Simulating timer 1
1294 t_uc51::do_timer1(int cycles)
1296 uint tmod= sfr->get(TMOD);
1297 uint tcon= sfr->get(TCON);
1298 uint p3= sfr->get(P3);
1300 if (((tmod & bmGATE1) &&
1301 (p3 & port_pins[3] & bm_INT1)) ||
1304 if (!(tmod & bmC_T1) ||
1305 ((prev_p3 & bmT1) &&
1306 !(p3 & port_pins[3] & bmT1)))
1308 if (!(tmod & bmM01) &&
1315 // mod 0, TH= 8 bit t/c, TL= 5 bit precounter
1316 if (++(MEM(MEM_SFR)[TL1]) > 0x1f)
1318 sfr->set_bit0(TL1, ~0x1f);
1319 if (!++(MEM(MEM_SFR)[TH1]))
1321 sfr->set_bit1(TCON, bmTF1);
1328 else if ((tmod & bmM01) &&
1335 // mod 1 TH+TL= 16 bit t/c
1336 if (!++(MEM(MEM_SFR)[TL1]))
1337 if (!++(MEM(MEM_SFR)[TH1]))
1339 sfr->set_bit1(TCON, bmTF1);
1345 else if (!(tmod & bmM01) &&
1352 // mod 2 TL= 8 bit t/c auto reload from TH
1353 if (!++(MEM(MEM_SFR)[TL1]))
1355 sfr->set(TL1, sfr->get(TH1));
1356 sfr->set_bit1(TCON, bmTF1);
1372 * Abstract method to handle WDT
1376 t_uc51::do_wdt(int cycles)
1383 * Checking for interrupt requests and accept one if needed
1387 t_uc51::do_interrupt(void)
1396 if (!((ie= sfr->get(IE)) & bmEA))
1398 class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
1399 for (i= 0; i < it_sources->count; i++)
1401 class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
1402 if (is->is_active() &&
1403 (ie & is->ie_mask) &&
1404 (sfr->get(is->src_reg) & is->src_mask))
1406 int pr= it_priority(is->ie_mask);
1407 if (il->level >= 0 &&
1410 if (state == stIDLE)
1413 sfr->set_bit0(PCON, bmIDL);
1418 sfr->set_bit0(is->src_reg, is->src_mask);
1419 sim->cmd->debug("%g sec (%d clks): "
1420 "Accepting interrupt `%s' PC= 0x%06x\n",
1421 get_rtime(), ticks->ticks, is->name, PC);
1422 IL= new it_level(pr, is->addr, PC, is);
1423 return(accept_it(IL));
1430 t_uc51::it_priority(uchar ie_mask)
1432 if (sfr->get(IP) & ie_mask)
1439 * Accept an interrupt
1443 t_uc51::accept_it(class it_level *il)
1446 sfr->set_bit0(PCON, bmIDL);
1447 it_levels->push(il);
1449 int res= inst_lcall(0, il->addr);
1453 return(resINTERRUPT);
1458 * Checking if Idle or PowerDown mode should be activated
1462 t_uc51::idle_pd(void)
1464 uint pcon= sfr->get(PCON);
1466 if (technology != CPU_CMOS)
1470 if (state != stIDLE)
1471 sim->cmd->debug("%g sec (%d clks): CPU in Idle mode\n",
1472 get_rtime(), ticks->ticks);
1479 sim->cmd->debug("%g sec (%d clks): CPU in PowerDown mode\n",
1480 get_rtime(), ticks->ticks);
1488 * Checking if EVENT break happened
1492 t_uc51::check_events(void)
1495 class cl_ev_brk *eb;
1499 for (i= 0; i < ebrk->count; i++)
1501 eb= (class cl_ev_brk *)(ebrk->at(i));
1502 if (eb->match(&event_at))
1503 return(resBREAKPOINT);
1510 * Simulating an unknown instruction
1512 * Normally this function is called for unimplemented instructions, because
1513 * every instruction must be known!
1517 t_uc51::inst_unknown(uchar code)
1520 if (1)//debug)// && sim->cmd_out())
1521 sim->cmd->debug("Unknown instruction %02x at %06x\n", code, PC);
1531 t_uc51::inst_nop(uchar code)
1542 t_uc51::inst_clr_a(uchar code)
1546 sfr->write(ACC, &d);
1556 t_uc51::inst_swap(uchar code)
1560 temp= (sfr->read(ACC) >> 4) & 0x0f;
1561 sfr->set(ACC, (sfr->get(ACC) << 4) | temp);
1566 /* End of s51.src/uc51.cc */