2 * Simulator of microcontrollers (uc51.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
41 #include <sys/types.h>
66 #include "interruptcl.h"
74 cl_irq_stop_option::cl_irq_stop_option(class cl_51core *the_uc51):
81 cl_irq_stop_option::init(void)
84 create(uc51, bool_opt, "irq_stop", "Stop when IRQ accepted");
89 cl_irq_stop_option::option_changed(void)
94 option->get_value(&b);
100 * Making a new micro-controller and reset it
103 cl_51core::cl_51core(int Itype, int Itech, class cl_sim *asim):
109 irq_stop_option= new cl_irq_stop_option(this);
110 stop_at_it= DD_FALSE;
115 * Initializing. Virtual calls go here
116 * This method must be called first after object creation.
120 cl_51core::init(void)
122 irq_stop_option->init();
124 set_name("mcs51_controller");
129 static char id_string_51[100];
132 cl_51core::id_string(void)
136 for (i= 0; cpus_51[i].type_str != NULL && cpus_51[i].type != type; i++) ;
137 sprintf(id_string_51, "%s %s",
138 cpus_51[i].type_str?cpus_51[i].type_str:"51",
139 (technology==CPU_HMOS)?"HMOS":"CMOS");
140 return(id_string_51);
144 cl_51core::mk_hw_elements(void)
148 acc= sfr->get_cell(ACC);
149 psw= sfr->get_cell(PSW);
151 hws->add(h= new cl_timer0(this, 0, "timer0"));
153 hws->add(h= new cl_timer1(this, 1, "timer1"));
155 #ifdef HAVE_TERMIOS_H
156 hws->add(h= new cl_serial(this));
159 hws->add(h= new cl_port(this, 0));
161 hws->add(h= new cl_port(this, 1));
163 hws->add(h= new cl_port(this, 2));
165 hws->add(h= new cl_port(this, 3));
167 hws->add(interrupt= new cl_interrupt(this));
169 hws->add(h= new cl_uc51_dummy_hw(this));
172 acc= sfr->get_cell(ACC);
173 psw= sfr->get_cell(PSW);
178 cl_51core::build_cmdset(class cl_cmdset *cmdset)
181 //class cl_super_cmd *super_cmd;
182 //class cl_cmdset *cset;
184 cl_uc::build_cmdset(cmdset);
186 cmdset->add(cmd= new cl_di_cmd("di", DD_TRUE,
187 "di [start [stop]] Dump Internal RAM",
191 cmdset->add(cmd= new cl_dx_cmd("dx", DD_TRUE,
192 "dx [start [stop]] Dump External RAM",
196 cmdset->add(cmd= new cl_ds_cmd("ds", DD_TRUE,
197 "ds [start [stop]] Dump SFR",
204 cl_51core::mk_mem(enum mem_class type, char *class_name)
206 class cl_address_space *m= cl_uc::mk_mem(type, class_name);
209 if (type == MEM_IRAM)
216 cl_51core::make_memories(void)
218 class cl_address_space *as;
220 rom= as= new cl_address_space(MEM_ROM_ID/*"rom"*/, 0, 0x10000, 8);
222 address_spaces->add(as);
223 iram= as= new cl_address_space(MEM_IRAM_ID/*"iram"*/, 0, 0x80, 8);
225 address_spaces->add(as);
226 sfr= as= new cl_address_space(MEM_SFR_ID/*"sfr"*/, 0x80, 0x80, 8);
228 address_spaces->add(as);
229 xram= as= new cl_address_space(MEM_XRAM_ID/*"xram"*/, 0, 0x10000, 8);
231 address_spaces->add(as);
233 class cl_address_decoder *ad;
234 class cl_memory_chip *chip;
236 chip= new cl_memory_chip("rom_chip", 0x10000, 8/*, 0xff*/);
239 ad= new cl_address_decoder(as= rom/*address_space(MEM_ROM_ID)*/,
242 as->decoders->add(ad);
245 chip= new cl_memory_chip("iram_chip", 0x80, 8);
248 ad= new cl_address_decoder(as= iram/*address_space(MEM_IRAM_ID)*/,
251 as->decoders->add(ad);
254 chip= new cl_memory_chip("xram_chip", 0x10000, 8);
257 ad= new cl_address_decoder(as= xram/*address_space(MEM_XRAM_ID)*/,
260 as->decoders->add(ad);
263 chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
266 ad= new cl_address_decoder(as= sfr/*address_space(MEM_SFR_ID)*/,
267 chip, 0x80, 0xff, 0);
269 as->decoders->add(ad);
272 acc= sfr->get_cell(ACC);
273 psw= sfr->get_cell(PSW);
278 * Destroying the micro-controller object
281 cl_51core::~cl_51core(void)
286 if (isatty(fileno(serial_out)))
287 tcsetattr(fileno(serial_out), TCSANOW, &saved_attributes_out);
292 if (isatty(fileno(serial_in)))
293 tcsetattr(fileno(serial_in), TCSANOW, &saved_attributes_in);
297 delete irq_stop_option;
302 * Disassembling an instruction
306 cl_51core::dis_tbl(void)
312 cl_51core::sfr_tbl(void)
318 cl_51core::bit_tbl(void)
324 cl_51core::disass(t_addr addr, char *sep)
326 char work[256], temp[20], c[2];
327 char *buf, *p, *b, *t;
328 t_mem code= rom->get(addr);
331 b= dis_tbl()[code].mnemonic;
339 case 'A': // absolute address
340 sprintf(temp, "%04"_A_"x",
341 t_addr((addr&0xf800)|
342 (((code>>5)&0x07)*256 +
345 case 'l': // long address
346 sprintf(temp, "%04"_A_"x",
347 t_addr(rom->get(addr+1)*256 +
350 case 'a': // addr8 (direct address) at 2nd byte
351 if (!get_name(rom->get(addr+1), sfr_tbl(), temp))
352 sprintf(temp, "%02"_M_"x", rom->get(addr+1));
354 case '8': // addr8 (direct address) at 3rd byte
355 if (!get_name(rom->get(addr+2), sfr_tbl(), temp))
356 sprintf(temp, "%02"_M_"x", rom->get(addr+2));
357 //sprintf(temp, "%02"_M_"x", rom->get(addr+2));
359 case 'b': // bitaddr at 2nd byte
361 t_addr ba= rom->get(addr+1);
362 if (get_name(ba, bit_tbl(), temp))
364 if (get_name((ba<128)?((ba/8)+32):(ba&0xf8), sfr_tbl(), temp))
367 sprintf(c, "%1"_M_"d", ba & 0x07);
371 sprintf(temp, "%02x.%"_M_"d", (ba<128)?((ba/8)+32):(ba&0xf8),
375 case 'r': // rel8 address at 2nd byte
376 sprintf(temp, "%04"_A_"x",
377 t_addr(addr+2+(signed char)(rom->get(addr+1))));
379 case 'R': // rel8 address at 3rd byte
380 sprintf(temp, "%04"_A_"x",
381 t_addr(addr+3+(signed char)(rom->get(addr+2))));
383 case 'd': // data8 at 2nd byte
384 sprintf(temp, "%02"_M_"x", rom->get(addr+1));
386 case 'D': // data8 at 3rd byte
387 sprintf(temp, "%02"_M_"x", rom->get(addr+2));
389 case '6': // data16 at 2nd(H)-3rd(L) byte
390 sprintf(temp, "%04"_A_"x",
391 t_addr(rom->get(addr+1)*256 +
407 p= strchr(work, ' ');
414 buf= (char *)malloc(6+strlen(p)+1);
416 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
417 for (p= work, b= buf; *p != ' '; p++, b++)
423 while (strlen(buf) < 6)
434 cl_51core::print_regs(class cl_console *con)
439 start= psw->get() & 0x18;
440 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
441 iram->dump(start, start+7, 8, con);
442 start= psw->get() & 0x18;
443 data= iram->get(iram->get(start));
444 con->dd_printf("%06x %02x %c",
445 iram->get(start), data, isprint(data)?data:'.');
447 con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x", sfr->get(ACC), sfr->get(ACC),
448 isprint(sfr->get(ACC))?(sfr->get(ACC)):'.', sfr->get(B));
450 data= xram->get(sfr->get(DPH)*256+sfr->get(DPL));
451 con->dd_printf(" DPTR= 0x%02x%02x @DPTR= 0x%02x %3d %c\n", sfr->get(DPH),
452 sfr->get(DPL), data, data, isprint(data)?data:'.');
454 data= iram->get(iram->get(start+1));
455 con->dd_printf("%06x %02x %c", iram->get(start+1), data,
456 isprint(data)?data:'.');
458 con->dd_printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
459 (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
460 (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
462 print_disass(PC, con);
467 * Converting bit address into real memory
470 class cl_address_space *
471 cl_51core::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
473 class cl_address_space *m;
480 ma= bitaddr/8 + 0x20;
490 *bitmask= 1 << (bitaddr & 0x7);
495 cl_51core::bit_address(class cl_memory *mem,
496 t_addr mem_address, int bit_number)
498 if (bit_number < 0 ||
502 class cl_memory *sfrchip= memory("sfr_chip");
506 mem_address+= sfr->start_address;
510 if (mem_address < 128 ||
511 mem_address % 8 != 0 ||
514 return(128 + (mem_address-128) + bit_number);
518 if (mem_address < 0x20 ||
519 mem_address >= 0x20+32)
521 return((mem_address-0x20)*8 + bit_number);
528 * Resetting the micro-controller
532 cl_51core::reset(void)
540 //was_reti= DD_FALSE;
545 * Setting up SFR area to reset value
549 cl_51core::clear_sfr(void)
553 for (i= 0x80; i <= 0xff; i++)
555 sfr->/*set*/write(P0, 0xff);
556 sfr->/*set*/write(P1, 0xff);
557 sfr->/*set*/write(P2, 0xff);
558 sfr->/*set*/write(P3, 0xff);
559 prev_p1= /*port_pins[1] &*/ sfr->/*get*/read(P1);
560 prev_p3= /*port_pins[3] &*/ sfr->/*get*/read(P3);
578 sfr->set_nuof_writes(0);
579 sfr->set_nuof_reads(0);
584 * Analyzing code and settig up instruction map
588 cl_51core::analyze(t_addr addr)
591 struct dis_entry *tabl;
593 code= rom->get(addr);
594 tabl= &(dis_tbl()[code]);
595 while (!inst_at(addr) &&
596 code != 0xa5 /* break point */)
599 switch (tabl->branch)
602 analyze((addr & 0xf800)|
603 ((rom->get(addr+1)&0x07)*256+
605 analyze(addr+tabl->length);
608 addr= (addr & 0xf800)|
609 ((rom->get(addr+1) & 0x07)*256 + rom->get(addr+2));
612 analyze(rom->get(addr+1)*256 + rom->get(addr+2));
613 analyze(addr+tabl->length);
616 addr= rom->get(addr+1)*256 + rom->get(addr+2);
618 case 'r': // reljmp (2nd byte)
619 analyze(rom->validate_address(addr+(signed char)(rom->get(addr+1))));
620 analyze(addr+tabl->length);
622 case 'R': // reljmp (3rd byte)
623 analyze(rom->validate_address(addr+(signed char)(rom->get(addr+2))));
624 analyze(addr+tabl->length);
629 target= rom->get(addr+1);
631 addr= rom->validate_address(addr+target);
637 addr= rom->validate_address(addr+tabl->length);
640 code= rom->get(addr);
641 tabl= &(dis_tbl()[code]);
647 * Inform hardware elements that `cycles' machine cycles have elapsed
651 cl_51core::tick_hw(int cycles)
653 cl_uc::tick_hw(cycles);
654 //do_hardware(cycles);
659 cl_51core::tick(int cycles)
662 //do_hardware(cycles);
668 * Correcting direct address
670 * This function returns address of addressed element which can be an IRAM
674 class cl_memory_cell *
675 cl_51core::get_direct(t_mem addr)
677 if (addr < sfr->start_address)
678 return(iram->get_cell(addr));
680 return(sfr->get_cell(addr));
685 * Calculating address of specified register cell in IRAM
688 class cl_memory_cell *
689 cl_51core::get_reg(uchar regnum)
691 t_addr a= (psw->get() & (bmRS0|bmRS1)) | (regnum & 0x07);
692 return(iram->get_cell(a));
697 * Fetching one instruction and executing it
701 cl_51core::exec_inst(void)
709 return(resBREAKPOINT);
714 case 0x00: res= inst_nop(code); break;
715 case 0x01: case 0x21: case 0x41: case 0x61:
716 case 0x81: case 0xa1: case 0xc1: case 0xe1:res=inst_ajmp_addr(code);break;
717 case 0x02: res= inst_ljmp(code); break;
718 case 0x03: res= inst_rr(code); break;
719 case 0x04: res= inst_inc_a(code); break;
720 case 0x05: res= inst_inc_addr(code); break;
721 case 0x06: case 0x07: res= inst_inc_Sri(code); break;
722 case 0x08: case 0x09: case 0x0a: case 0x0b:
723 case 0x0c: case 0x0d: case 0x0e: case 0x0f: res= inst_inc_rn(code); break;
724 case 0x10: res= inst_jbc_bit_addr(code); break;
725 case 0x11: case 0x31: case 0x51: case 0x71:
726 case 0x91: case 0xb1: case 0xd1: case 0xf1:res=inst_acall_addr(code);break;
727 case 0x12: res= inst_lcall(code, 0, DD_FALSE); break;
728 case 0x13: res= inst_rrc(code); break;
729 case 0x14: res= inst_dec_a(code); break;
730 case 0x15: res= inst_dec_addr(code); break;
731 case 0x16: case 0x17: res= inst_dec_Sri(code); break;
732 case 0x18: case 0x19: case 0x1a: case 0x1b:
733 case 0x1c: case 0x1d: case 0x1e: case 0x1f: res= inst_dec_rn(code); break;
734 case 0x20: res= inst_jb_bit_addr(code); break;
735 case 0x22: res= inst_ret(code); break;
736 case 0x23: res= inst_rl(code); break;
737 case 0x24: res= inst_add_a_Sdata(code); break;
738 case 0x25: res= inst_add_a_addr(code); break;
739 case 0x26: case 0x27: res= inst_add_a_Sri(code); break;
740 case 0x28: case 0x29: case 0x2a: case 0x2b:
741 case 0x2c: case 0x2d: case 0x2e: case 0x2f:res= inst_add_a_rn(code);break;
742 case 0x30: res= inst_jnb_bit_addr(code); break;
743 case 0x32: res= inst_reti(code); break;
744 case 0x33: res= inst_rlc(code); break;
745 case 0x34: res= inst_addc_a_Sdata(code); break;
746 case 0x35: res= inst_addc_a_addr(code); break;
747 case 0x36: case 0x37: res= inst_addc_a_Sri(code); break;
748 case 0x38: case 0x39: case 0x3a: case 0x3b:
749 case 0x3c: case 0x3d: case 0x3e: case 0x3f:res= inst_addc_a_rn(code);break;
750 case 0x40: res= inst_jc_addr(code); break;
751 case 0x42: res= inst_orl_addr_a(code); break;
752 case 0x43: res= inst_orl_addr_Sdata(code); break;
753 case 0x44: res= inst_orl_a_Sdata(code); break;
754 case 0x45: res= inst_orl_a_addr(code); break;
755 case 0x46: case 0x47: res= inst_orl_a_Sri(code); break;
756 case 0x48: case 0x49: case 0x4a: case 0x4b:
757 case 0x4c: case 0x4d: case 0x4e: case 0x4f: res= inst_orl_a_rn(code);break;
758 case 0x50: res= inst_jnc_addr(code); break;
759 case 0x52: res= inst_anl_addr_a(code); break;
760 case 0x53: res= inst_anl_addr_Sdata(code); break;
761 case 0x54: res= inst_anl_a_Sdata(code); break;
762 case 0x55: res= inst_anl_a_addr(code); break;
763 case 0x56: case 0x57: res= inst_anl_a_Sri(code); break;
764 case 0x58: case 0x59: case 0x5a: case 0x5b:
765 case 0x5c: case 0x5d: case 0x5e: case 0x5f: res= inst_anl_a_rn(code);break;
766 case 0x60: res= inst_jz_addr(code); break;
767 case 0x62: res= inst_xrl_addr_a(code); break;
768 case 0x63: res= inst_xrl_addr_Sdata(code); break;
769 case 0x64: res= inst_xrl_a_Sdata(code); break;
770 case 0x65: res= inst_xrl_a_addr(code); break;
771 case 0x66: case 0x67: res= inst_xrl_a_Sri(code); break;
772 case 0x68: case 0x69: case 0x6a: case 0x6b:
773 case 0x6c: case 0x6d: case 0x6e: case 0x6f: res= inst_xrl_a_rn(code);break;
774 case 0x70: res= inst_jnz_addr(code); break;
775 case 0x72: res= inst_orl_c_bit(code); break;
776 case 0x73: res= inst_jmp_Sa_dptr(code); break;
777 case 0x74: res= inst_mov_a_Sdata(code); break;
778 case 0x75: res= inst_mov_addr_Sdata(code); break;
779 case 0x76: case 0x77: res= inst_mov_Sri_Sdata(code); break;
780 case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c:
781 case 0x7d: case 0x7e: case 0x7f: res=inst_mov_rn_Sdata(code); break;
782 case 0x80: res= inst_sjmp(code); break;
783 case 0x82: res= inst_anl_c_bit(code); break;
784 case 0x83: res= inst_movc_a_Sa_pc(code); break;
785 case 0x84: res= inst_div_ab(code); break;
786 case 0x85: res= inst_mov_addr_addr(code); break;
787 case 0x86: case 0x87: res= inst_mov_addr_Sri(code); break;
788 case 0x88: case 0x89: case 0x8a: case 0x8b:
789 case 0x8c: case 0x8d: case 0x8e: case 0x8f:res=inst_mov_addr_rn(code);break;
790 case 0x90: res= inst_mov_dptr_Sdata(code); break;
791 case 0x92: res= inst_mov_bit_c(code); break;
792 case 0x93: res= inst_movc_a_Sa_dptr(code); break;
793 case 0x94: res= inst_subb_a_Sdata(code); break;
794 case 0x95: res= inst_subb_a_addr(code); break;
795 case 0x96: case 0x97: res= inst_subb_a_Sri(code); break;
796 case 0x98: case 0x99: case 0x9a: case 0x9b:
797 case 0x9c: case 0x9d: case 0x9e: case 0x9f:res= inst_subb_a_rn(code);break;
798 case 0xa0: res= inst_orl_c_Sbit(code); break;
799 case 0xa2: res= inst_mov_c_bit(code); break;
800 case 0xa3: res= inst_inc_dptr(code); break;
801 case 0xa4: res= inst_mul_ab(code); break;
802 case 0xa5: res= inst_unknown(); break;
803 case 0xa6: case 0xa7: res= inst_mov_Sri_addr(code); break;
804 case 0xa8: case 0xa9: case 0xaa: case 0xab:
805 case 0xac: case 0xad: case 0xae: case 0xaf:res=inst_mov_rn_addr(code);break;
806 case 0xb0: res= inst_anl_c_Sbit(code); break;
807 case 0xb2: res= inst_cpl_bit(code); break;
808 case 0xb3: res= inst_cpl_c(code); break;
809 case 0xb4: res= inst_cjne_a_Sdata_addr(code); break;
810 case 0xb5: res= inst_cjne_a_addr_addr(code); break;
811 case 0xb6: case 0xb7: res= inst_cjne_Sri_Sdata_addr(code); break;
812 case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc:
813 case 0xbd: case 0xbe: case 0xbf: res=inst_cjne_rn_Sdata_addr(code); break;
814 case 0xc0: res= inst_push(code); break;
815 case 0xc2: res= inst_clr_bit(code); break;
816 case 0xc3: res= inst_clr_c(code); break;
817 case 0xc4: res= inst_swap(code); break;
818 case 0xc5: res= inst_xch_a_addr(code); break;
819 case 0xc6: case 0xc7: res= inst_xch_a_Sri(code); break;
820 case 0xc8: case 0xc9: case 0xca: case 0xcb:
821 case 0xcc: case 0xcd: case 0xce: case 0xcf: res= inst_xch_a_rn(code);break;
822 case 0xd0: res= inst_pop(code); break;
823 case 0xd2: res= inst_setb_bit(code); break;
824 case 0xd3: res= inst_setb_c(code); break;
825 case 0xd4: res= inst_da_a(code); break;
826 case 0xd5: res= inst_djnz_addr_addr(code); break;
827 case 0xd6: case 0xd7: res= inst_xchd_a_Sri(code); break;
828 case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc:
829 case 0xdd: case 0xde: case 0xdf: res=inst_djnz_rn_addr(code); break;
830 case 0xe0: res= inst_movx_a_Sdptr(code); break;
831 case 0xe2: case 0xe3: res= inst_movx_a_Sri(code); break;
832 case 0xe4: res= inst_clr_a(code); break;
833 case 0xe5: res= inst_mov_a_addr(code); break;
834 case 0xe6: case 0xe7: res= inst_mov_a_Sri(code); break;
835 case 0xe8: case 0xe9: case 0xea: case 0xeb:
836 case 0xec: case 0xed: case 0xee: case 0xef: res= inst_mov_a_rn(code);break;
837 case 0xf0: res= inst_movx_Sdptr_a(code); break;
838 case 0xf2: case 0xf3: res= inst_movx_Sri_a(code); break;
839 case 0xf4: res= inst_cpl_a(code); break;
840 case 0xf5: res= inst_mov_addr_a(code); break;
841 case 0xf6: case 0xf7: res= inst_mov_Sri_a(code); break;
842 case 0xf8: case 0xf9: case 0xfa: case 0xfb:
843 case 0xfc: case 0xfd: case 0xfe: case 0xff: res= inst_mov_rn_a(code);break;
854 * Simulating execution of next instruction
856 * This is an endless loop if requested number of steps is negative.
857 * In this case execution is stopped if an instruction results other
858 * status than GO. Execution can be stopped if `cmd_in' is not NULL
859 * and there is input available on that file. It is usefull if the
860 * command console is on a terminal. If input is available then a
861 * complete line is read and dropped out because input is buffered
862 * (inp_avail will be TRUE if ENTER is pressed) and it can confuse
863 * command interepter.
865 //static class cl_console *c= NULL;
867 cl_51core::do_inst(int step)
870 while ((result == resGO) &&
878 interrupt->was_reti= DD_FALSE;
888 if (sim->app->get_commander()==NULL)
889 printf("no commander PC=0x%x\n",PC);
891 if (sim->app->get_commander()->frozen_console==NULL)
892 printf("no frozen console PC=0x%x\n",PC);
894 c= sim->app->get_commander()->frozen_console;
898 printf("no console PC=0x%x\n",PC);
902 /*if (result == resGO)
903 result= check_events();*/
907 // tick hw in idle state
915 if ((res= do_interrupt()) != resGO)
921 ((ticks->ticks % 100000) < 50))
923 if (sim->app->get_commander()->input_avail_on_frozen())
928 if (sim->app->get_commander()->input_avail())
931 if (((result == resINTERRUPT) &&
941 //FIXME: tick outsiders eg. watchdog
942 if (sim->app->get_commander()->input_avail_on_frozen())
944 //fprintf(stderr,"uc: inp avail in PD mode, user stop\n");
953 cl_51core::post_inst(void)
955 //uint tcon= sfr->get(TCON);
956 //uint p3= sfr->read(P3);
958 //cl_uc::post_inst();
961 // Setting up external interrupt request bits (IEx)
962 /*if ((tcon & bmIT0))
964 // IE0 edge triggered
967 // falling edge on INT0
968 sim->app->get_commander()->
969 debug("%g sec (%d clks): Falling edge detected on INT0 (P3.2)\n",
970 get_rtime(), ticks->ticks);
971 sfr->set_bit1(TCON, bmIE0);
977 // IE0 level triggered
979 sfr->set_bit0(TCON, bmIE0);
981 sfr->set_bit1(TCON, bmIE0);
985 // IE1 edge triggered
988 // falling edge on INT1
989 sfr->set_bit1(TCON, bmIE1);
995 // IE1 level triggered
997 sfr->set_bit0(TCON, bmIE1);
999 sfr->set_bit1(TCON, bmIE1);
1001 //prev_p3= p3 & port_pins[3];
1002 //prev_p1= p3 & port_pins[1];
1007 * Abstract method to handle WDT
1011 cl_51core::do_wdt(int cycles)
1018 * Checking for interrupt requests and accept one if needed
1022 cl_51core::do_interrupt(void)
1026 if (interrupt->was_reti)
1028 interrupt->was_reti= DD_FALSE;
1031 if (!((ie= sfr->get(IE)) & bmEA))
1033 class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
1034 for (i= 0; i < it_sources->count; i++)
1036 class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
1037 if (is->is_active() &&
1038 (ie & is->ie_mask) &&
1039 (sfr->get(is->src_reg) & is->src_mask))
1041 int pr= it_priority(is->ie_mask);
1042 if (il->level >= 0 &&
1045 if (state == stIDLE)
1048 sfr->set_bit0(PCON, bmIDL);
1049 interrupt->was_reti= DD_TRUE;
1053 sfr->set_bit0(is->src_reg, is->src_mask);
1054 sim->app->get_commander()->
1055 debug("%g sec (%d clks): Accepting interrupt `%s' PC= 0x%06x\n",
1056 get_rtime(), ticks->ticks, object_name(is), PC);
1057 IL= new it_level(pr, is->addr, PC, is);
1058 return(accept_it(IL));
1065 cl_51core::it_priority(uchar ie_mask)
1067 if (sfr->get(IP) & ie_mask)
1074 * Accept an interrupt
1078 cl_51core::accept_it(class it_level *il)
1081 sfr->set_bit0(PCON, bmIDL);
1082 it_levels->push(il);
1084 int res= inst_lcall(0, il->addr, DD_TRUE);
1088 return(resINTERRUPT);
1093 * Checking if Idle or PowerDown mode should be activated
1097 cl_51core::idle_pd(void)
1099 uint pcon= sfr->get(PCON);
1101 if (technology != CPU_CMOS)
1105 if (state != stIDLE)
1106 sim->app->get_commander()->
1107 debug("%g sec (%d clks): CPU in Idle mode (PC=0x%x, PCON=0x%x)\n",
1108 get_rtime(), ticks->ticks, PC, pcon);
1115 sim->app->get_commander()->
1116 debug("%g sec (%d clks): CPU in PowerDown mode\n",
1117 get_rtime(), ticks->ticks);
1125 * Checking if EVENT break happened
1129 cl_51core::check_events(void)
1132 class cl_ev_brk *eb;
1136 for (i= 0; i < ebrk->count; i++)
1138 eb= (class cl_ev_brk *)(ebrk->at(i));
1139 if (eb->match(&event_at))
1140 return(resBREAKPOINT);
1151 cl_51core::mem_cell_changed(class cl_m *mem, t_addr addr)
1156 case ACC: acc= mem->get_cell(ACC); break;
1157 case PSW: psw= mem->get_cell(PSW); break;
1159 cl_uc::mem_cell_changed(mem, addr);
1165 * Simulating an unknown instruction
1167 * Normally this function is called for unimplemented instructions, because
1168 * every instruction must be known!
1172 cl_51core::inst_unknown(void)
1175 class cl_error_unknown_code *e= new cl_error_unknown_code(this);
1186 cl_51core::inst_nop(uchar code)
1197 cl_51core::inst_clr_a(uchar code)
1209 cl_51core::inst_swap(uchar code)
1213 temp= (acc->read() >> 4) & 0x0f;
1214 sfr->write(ACC, (acc->get() << 4) | temp);
1222 cl_uc51_dummy_hw::cl_uc51_dummy_hw(class cl_uc *auc):
1223 cl_hw(auc, HW_DUMMY, 0, "_51_dummy")
1225 //uc51= (class cl_51core *)uc;
1229 cl_uc51_dummy_hw::init(void)
1231 class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
1234 fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
1236 //acc= sfr->register_hw(ACC, this, 0);
1237 //sp = sfr->register_hw(SP , this, 0);
1238 use_cell(sfr, PSW, &cell_psw, wtd_restore);
1239 register_cell(sfr, ACC, &cell_acc, wtd_restore_write);
1240 register_cell(sfr, SP , &cell_sp , wtd_restore);
1241 //register_cell(sfr, PCON, &cell_pcon, wtd_restore);
1246 cl_uc51_dummy_hw::write(class cl_memory_cell *cell, t_mem *val)
1248 if (cell == cell_acc)
1256 for (i= 0; i < 8; i++)
1263 cell_psw->set_bit1(bmP);
1265 cell_psw->set_bit0(bmP);
1267 else if (cell == cell_sp)
1269 if (*val > uc->sp_max)
1271 uc->sp_avg= (uc->sp_avg+(*val))/2;
1273 /*else if (cell == cell_pcon)
1275 printf("PCON write 0x%x (PC=0x%x)\n", *val, uc->PC);
1281 cl_uc51_dummy_hw::happen(class cl_hw *where, enum hw_event he, void *params)
1283 struct ev_port_changed *ep= (struct ev_port_changed *)params;
1285 if (where->cathegory == HW_PORT &&
1286 he == EV_PORT_CHANGED &&
1289 t_mem p3o= ep->pins & ep->prev_value;
1290 t_mem p3n= ep->new_pins & ep->new_value;
1291 if ((p3o & bm_INT0) &&
1293 uc51->p3_int0_edge++;
1294 if ((p3o & bm_INT1) &&
1296 uc51->p3_int1_edge++;
1301 /* End of s51.src/uc51.cc */