2 * Simulator of microcontrollers (uc51.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
37 #include <sys/types.h>
62 #include "interruptcl.h"
70 cl_irq_stop_option::cl_irq_stop_option(class cl_51core *the_uc51):
77 cl_irq_stop_option::init(void)
80 create(uc51, bool_opt, "irq_stop", "Stop when IRQ accepted");
85 cl_irq_stop_option::option_changed(void)
90 option->get_value(&b);
96 * Making a new micro-controller and reset it
99 cl_51core::cl_51core(int Itype, int Itech, class cl_sim *asim):
105 irq_stop_option= new cl_irq_stop_option(this);
106 stop_at_it= DD_FALSE;
111 * Initializing. Virtual calls go here
112 * This method must be called first after object creation.
116 cl_51core::init(void)
118 irq_stop_option->init();
120 set_name("mcs51_controller");
125 static char id_string_51[100];
128 cl_51core::id_string(void)
132 for (i= 0; cpus_51[i].type_str != NULL && cpus_51[i].type != type; i++) ;
133 sprintf(id_string_51, "%s %s",
134 cpus_51[i].type_str?cpus_51[i].type_str:"51",
135 (technology==CPU_HMOS)?"HMOS":"CMOS");
136 return(id_string_51);
140 cl_51core::mk_hw_elements(void)
144 acc= sfr->get_cell(ACC);
145 psw= sfr->get_cell(PSW);
147 hws->add(h= new cl_timer0(this, 0, "timer0"));
149 hws->add(h= new cl_timer1(this, 1, "timer1"));
151 hws->add(h= new cl_serial(this));
153 hws->add(h= new cl_port(this, 0));
155 hws->add(h= new cl_port(this, 1));
157 hws->add(h= new cl_port(this, 2));
159 hws->add(h= new cl_port(this, 3));
161 hws->add(interrupt= new cl_interrupt(this));
163 hws->add(h= new cl_uc51_dummy_hw(this));
166 acc= sfr->get_cell(ACC);
167 psw= sfr->get_cell(PSW);
172 cl_51core::build_cmdset(class cl_cmdset *cmdset)
175 //class cl_super_cmd *super_cmd;
176 //class cl_cmdset *cset;
178 cl_uc::build_cmdset(cmdset);
180 cmdset->add(cmd= new cl_di_cmd("di", DD_TRUE,
181 "di [start [stop]] Dump Internal RAM",
185 cmdset->add(cmd= new cl_dx_cmd("dx", DD_TRUE,
186 "dx [start [stop]] Dump External RAM",
190 cmdset->add(cmd= new cl_ds_cmd("ds", DD_TRUE,
191 "ds [start [stop]] Dump SFR",
198 cl_51core::mk_mem(enum mem_class type, char *class_name)
200 class cl_address_space *m= cl_uc::mk_mem(type, class_name);
203 if (type == MEM_IRAM)
210 cl_51core::make_memories(void)
212 class cl_address_space *as;
214 rom= as= new cl_address_space(MEM_ROM_ID/*"rom"*/, 0, 0x10000, 8);
216 address_spaces->add(as);
217 iram= as= new cl_address_space(MEM_IRAM_ID/*"iram"*/, 0, 0x80, 8);
219 address_spaces->add(as);
220 sfr= as= new cl_address_space(MEM_SFR_ID/*"sfr"*/, 0x80, 0x80, 8);
222 address_spaces->add(as);
223 xram= as= new cl_address_space(MEM_XRAM_ID/*"xram"*/, 0, 0x10000, 8);
225 address_spaces->add(as);
227 class cl_address_decoder *ad;
228 class cl_memory_chip *chip;
230 chip= new cl_memory_chip("rom_chip", 0x10000, 8/*, 0xff*/);
233 ad= new cl_address_decoder(as= rom/*address_space(MEM_ROM_ID)*/,
236 as->decoders->add(ad);
239 chip= new cl_memory_chip("iram_chip", 0x80, 8);
242 ad= new cl_address_decoder(as= iram/*address_space(MEM_IRAM_ID)*/,
245 as->decoders->add(ad);
248 chip= new cl_memory_chip("xram_chip", 0x10000, 8);
251 ad= new cl_address_decoder(as= xram/*address_space(MEM_XRAM_ID)*/,
254 as->decoders->add(ad);
257 chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
260 ad= new cl_address_decoder(as= sfr/*address_space(MEM_SFR_ID)*/,
261 chip, 0x80, 0xff, 0);
263 as->decoders->add(ad);
266 acc= sfr->get_cell(ACC);
267 psw= sfr->get_cell(PSW);
272 * Destroying the micro-controller object
275 cl_51core::~cl_51core(void)
280 if (isatty(fileno(serial_out)))
281 tcsetattr(fileno(serial_out), TCSANOW, &saved_attributes_out);
286 if (isatty(fileno(serial_in)))
287 tcsetattr(fileno(serial_in), TCSANOW, &saved_attributes_in);
291 delete irq_stop_option;
296 * Disassembling an instruction
300 cl_51core::dis_tbl(void)
306 cl_51core::sfr_tbl(void)
312 cl_51core::bit_tbl(void)
318 cl_51core::disass(t_addr addr, char *sep)
320 char work[256], temp[20], c[2];
321 char *buf, *p, *b, *t;
322 t_mem code= rom->get(addr);
325 b= dis_tbl()[code].mnemonic;
333 case 'A': // absolute address
334 sprintf(temp, "%04"_A_"x",
335 t_addr((addr&0xf800)|
336 (((code>>5)&0x07)*256 +
339 case 'l': // long address
340 sprintf(temp, "%04"_A_"x",
341 t_addr(rom->get(addr+1)*256 +
344 case 'a': // addr8 (direct address) at 2nd byte
345 if (!get_name(rom->get(addr+1), sfr_tbl(), temp))
346 sprintf(temp, "%02"_M_"x", rom->get(addr+1));
348 case '8': // addr8 (direct address) at 3rd byte
349 if (!get_name(rom->get(addr+2), sfr_tbl(), temp))
350 sprintf(temp, "%02"_M_"x", rom->get(addr+2));
351 //sprintf(temp, "%02"_M_"x", rom->get(addr+2));
353 case 'b': // bitaddr at 2nd byte
355 t_addr ba= rom->get(addr+1);
356 if (get_name(ba, bit_tbl(), temp))
358 if (get_name((ba<128)?((ba/8)+32):(ba&0xf8), sfr_tbl(), temp))
361 sprintf(c, "%1"_M_"d", ba & 0x07);
365 sprintf(temp, "%02x.%"_M_"d", (ba<128)?((ba/8)+32):(ba&0xf8),
369 case 'r': // rel8 address at 2nd byte
370 sprintf(temp, "%04"_A_"x",
371 t_addr(addr+2+(signed char)(rom->get(addr+1))));
373 case 'R': // rel8 address at 3rd byte
374 sprintf(temp, "%04"_A_"x",
375 t_addr(addr+3+(signed char)(rom->get(addr+2))));
377 case 'd': // data8 at 2nd byte
378 sprintf(temp, "%02"_M_"x", rom->get(addr+1));
380 case 'D': // data8 at 3rd byte
381 sprintf(temp, "%02"_M_"x", rom->get(addr+2));
383 case '6': // data16 at 2nd(H)-3rd(L) byte
384 sprintf(temp, "%04"_A_"x",
385 t_addr(rom->get(addr+1)*256 +
401 p= strchr(work, ' ');
408 buf= (char *)malloc(6+strlen(p)+1);
410 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
411 for (p= work, b= buf; *p != ' '; p++, b++)
417 while (strlen(buf) < 6)
428 cl_51core::print_regs(class cl_console *con)
433 start= psw->get() & 0x18;
434 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
435 iram->dump(start, start+7, 8, con);
436 start= psw->get() & 0x18;
437 data= iram->get(iram->get(start));
438 con->dd_printf("%06x %02x %c",
439 iram->get(start), data, isprint(data)?data:'.');
441 con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x", sfr->get(ACC), sfr->get(ACC),
442 isprint(sfr->get(ACC))?(sfr->get(ACC)):'.', sfr->get(B));
444 data= xram->get(sfr->get(DPH)*256+sfr->get(DPL));
445 con->dd_printf(" DPTR= 0x%02x%02x @DPTR= 0x%02x %3d %c\n", sfr->get(DPH),
446 sfr->get(DPL), data, data, isprint(data)?data:'.');
448 data= iram->get(iram->get(start+1));
449 con->dd_printf("%06x %02x %c", iram->get(start+1), data,
450 isprint(data)?data:'.');
452 con->dd_printf(" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
453 (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
454 (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
456 print_disass(PC, con);
461 * Converting bit address into real memory
464 class cl_address_space *
465 cl_51core::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
467 class cl_address_space *m;
474 ma= bitaddr/8 + 0x20;
484 *bitmask= 1 << (bitaddr & 0x7);
489 cl_51core::bit_address(class cl_memory *mem,
490 t_addr mem_address, int bit_number)
492 if (bit_number < 0 ||
496 class cl_memory *sfrchip= memory("sfr_chip");
500 mem_address+= sfr->start_address;
504 if (mem_address < 128 ||
505 mem_address % 8 != 0 ||
508 return(128 + (mem_address-128) + bit_number);
512 if (mem_address < 0x20 ||
513 mem_address >= 0x20+32)
515 return((mem_address-0x20)*8 + bit_number);
522 * Resetting the micro-controller
526 cl_51core::reset(void)
534 //was_reti= DD_FALSE;
539 * Setting up SFR area to reset value
543 cl_51core::clear_sfr(void)
547 for (i= 0x80; i <= 0xff; i++)
549 sfr->/*set*/write(P0, 0xff);
550 sfr->/*set*/write(P1, 0xff);
551 sfr->/*set*/write(P2, 0xff);
552 sfr->/*set*/write(P3, 0xff);
553 prev_p1= /*port_pins[1] &*/ sfr->/*get*/read(P1);
554 prev_p3= /*port_pins[3] &*/ sfr->/*get*/read(P3);
572 sfr->set_nuof_writes(0);
573 sfr->set_nuof_reads(0);
578 * Analyzing code and settig up instruction map
582 cl_51core::analyze(t_addr addr)
585 struct dis_entry *tabl;
587 code= rom->get(addr);
588 tabl= &(dis_tbl()[code]);
589 while (!inst_at(addr) &&
590 code != 0xa5 /* break point */)
593 switch (tabl->branch)
596 analyze((addr & 0xf800)|
597 ((rom->get(addr+1)&0x07)*256+
599 analyze(addr+tabl->length);
602 addr= (addr & 0xf800)|
603 ((rom->get(addr+1) & 0x07)*256 + rom->get(addr+2));
606 analyze(rom->get(addr+1)*256 + rom->get(addr+2));
607 analyze(addr+tabl->length);
610 addr= rom->get(addr+1)*256 + rom->get(addr+2);
612 case 'r': // reljmp (2nd byte)
613 analyze(rom->validate_address(addr+(signed char)(rom->get(addr+1))));
614 analyze(addr+tabl->length);
616 case 'R': // reljmp (3rd byte)
617 analyze(rom->validate_address(addr+(signed char)(rom->get(addr+2))));
618 analyze(addr+tabl->length);
623 target= rom->get(addr+1);
625 addr= rom->validate_address(addr+target);
631 addr= rom->validate_address(addr+tabl->length);
634 code= rom->get(addr);
635 tabl= &(dis_tbl()[code]);
641 * Inform hardware elements that `cycles' machine cycles have elapsed
645 cl_51core::tick_hw(int cycles)
647 cl_uc::tick_hw(cycles);
648 //do_hardware(cycles);
653 cl_51core::tick(int cycles)
656 //do_hardware(cycles);
662 * Correcting direct address
664 * This function returns address of addressed element which can be an IRAM
668 class cl_memory_cell *
669 cl_51core::get_direct(t_mem addr)
671 if (addr < sfr->start_address)
672 return(iram->get_cell(addr));
674 return(sfr->get_cell(addr));
679 * Calculating address of specified register cell in IRAM
682 class cl_memory_cell *
683 cl_51core::get_reg(uchar regnum)
685 t_addr a= (psw->get() & (bmRS0|bmRS1)) | (regnum & 0x07);
686 return(iram->get_cell(a));
691 * Fetching one instruction and executing it
695 cl_51core::exec_inst(void)
703 return(resBREAKPOINT);
708 case 0x00: res= inst_nop(code); break;
709 case 0x01: case 0x21: case 0x41: case 0x61:
710 case 0x81: case 0xa1: case 0xc1: case 0xe1:res=inst_ajmp_addr(code);break;
711 case 0x02: res= inst_ljmp(code); break;
712 case 0x03: res= inst_rr(code); break;
713 case 0x04: res= inst_inc_a(code); break;
714 case 0x05: res= inst_inc_addr(code); break;
715 case 0x06: case 0x07: res= inst_inc_Sri(code); break;
716 case 0x08: case 0x09: case 0x0a: case 0x0b:
717 case 0x0c: case 0x0d: case 0x0e: case 0x0f: res= inst_inc_rn(code); break;
718 case 0x10: res= inst_jbc_bit_addr(code); break;
719 case 0x11: case 0x31: case 0x51: case 0x71:
720 case 0x91: case 0xb1: case 0xd1: case 0xf1:res=inst_acall_addr(code);break;
721 case 0x12: res= inst_lcall(code, 0, DD_FALSE); break;
722 case 0x13: res= inst_rrc(code); break;
723 case 0x14: res= inst_dec_a(code); break;
724 case 0x15: res= inst_dec_addr(code); break;
725 case 0x16: case 0x17: res= inst_dec_Sri(code); break;
726 case 0x18: case 0x19: case 0x1a: case 0x1b:
727 case 0x1c: case 0x1d: case 0x1e: case 0x1f: res= inst_dec_rn(code); break;
728 case 0x20: res= inst_jb_bit_addr(code); break;
729 case 0x22: res= inst_ret(code); break;
730 case 0x23: res= inst_rl(code); break;
731 case 0x24: res= inst_add_a_Sdata(code); break;
732 case 0x25: res= inst_add_a_addr(code); break;
733 case 0x26: case 0x27: res= inst_add_a_Sri(code); break;
734 case 0x28: case 0x29: case 0x2a: case 0x2b:
735 case 0x2c: case 0x2d: case 0x2e: case 0x2f:res= inst_add_a_rn(code);break;
736 case 0x30: res= inst_jnb_bit_addr(code); break;
737 case 0x32: res= inst_reti(code); break;
738 case 0x33: res= inst_rlc(code); break;
739 case 0x34: res= inst_addc_a_Sdata(code); break;
740 case 0x35: res= inst_addc_a_addr(code); break;
741 case 0x36: case 0x37: res= inst_addc_a_Sri(code); break;
742 case 0x38: case 0x39: case 0x3a: case 0x3b:
743 case 0x3c: case 0x3d: case 0x3e: case 0x3f:res= inst_addc_a_rn(code);break;
744 case 0x40: res= inst_jc_addr(code); break;
745 case 0x42: res= inst_orl_addr_a(code); break;
746 case 0x43: res= inst_orl_addr_Sdata(code); break;
747 case 0x44: res= inst_orl_a_Sdata(code); break;
748 case 0x45: res= inst_orl_a_addr(code); break;
749 case 0x46: case 0x47: res= inst_orl_a_Sri(code); break;
750 case 0x48: case 0x49: case 0x4a: case 0x4b:
751 case 0x4c: case 0x4d: case 0x4e: case 0x4f: res= inst_orl_a_rn(code);break;
752 case 0x50: res= inst_jnc_addr(code); break;
753 case 0x52: res= inst_anl_addr_a(code); break;
754 case 0x53: res= inst_anl_addr_Sdata(code); break;
755 case 0x54: res= inst_anl_a_Sdata(code); break;
756 case 0x55: res= inst_anl_a_addr(code); break;
757 case 0x56: case 0x57: res= inst_anl_a_Sri(code); break;
758 case 0x58: case 0x59: case 0x5a: case 0x5b:
759 case 0x5c: case 0x5d: case 0x5e: case 0x5f: res= inst_anl_a_rn(code);break;
760 case 0x60: res= inst_jz_addr(code); break;
761 case 0x62: res= inst_xrl_addr_a(code); break;
762 case 0x63: res= inst_xrl_addr_Sdata(code); break;
763 case 0x64: res= inst_xrl_a_Sdata(code); break;
764 case 0x65: res= inst_xrl_a_addr(code); break;
765 case 0x66: case 0x67: res= inst_xrl_a_Sri(code); break;
766 case 0x68: case 0x69: case 0x6a: case 0x6b:
767 case 0x6c: case 0x6d: case 0x6e: case 0x6f: res= inst_xrl_a_rn(code);break;
768 case 0x70: res= inst_jnz_addr(code); break;
769 case 0x72: res= inst_orl_c_bit(code); break;
770 case 0x73: res= inst_jmp_Sa_dptr(code); break;
771 case 0x74: res= inst_mov_a_Sdata(code); break;
772 case 0x75: res= inst_mov_addr_Sdata(code); break;
773 case 0x76: case 0x77: res= inst_mov_Sri_Sdata(code); break;
774 case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c:
775 case 0x7d: case 0x7e: case 0x7f: res=inst_mov_rn_Sdata(code); break;
776 case 0x80: res= inst_sjmp(code); break;
777 case 0x82: res= inst_anl_c_bit(code); break;
778 case 0x83: res= inst_movc_a_Sa_pc(code); break;
779 case 0x84: res= inst_div_ab(code); break;
780 case 0x85: res= inst_mov_addr_addr(code); break;
781 case 0x86: case 0x87: res= inst_mov_addr_Sri(code); break;
782 case 0x88: case 0x89: case 0x8a: case 0x8b:
783 case 0x8c: case 0x8d: case 0x8e: case 0x8f:res=inst_mov_addr_rn(code);break;
784 case 0x90: res= inst_mov_dptr_Sdata(code); break;
785 case 0x92: res= inst_mov_bit_c(code); break;
786 case 0x93: res= inst_movc_a_Sa_dptr(code); break;
787 case 0x94: res= inst_subb_a_Sdata(code); break;
788 case 0x95: res= inst_subb_a_addr(code); break;
789 case 0x96: case 0x97: res= inst_subb_a_Sri(code); break;
790 case 0x98: case 0x99: case 0x9a: case 0x9b:
791 case 0x9c: case 0x9d: case 0x9e: case 0x9f:res= inst_subb_a_rn(code);break;
792 case 0xa0: res= inst_orl_c_Sbit(code); break;
793 case 0xa2: res= inst_mov_c_bit(code); break;
794 case 0xa3: res= inst_inc_dptr(code); break;
795 case 0xa4: res= inst_mul_ab(code); break;
796 case 0xa5: res= inst_unknown(); break;
797 case 0xa6: case 0xa7: res= inst_mov_Sri_addr(code); break;
798 case 0xa8: case 0xa9: case 0xaa: case 0xab:
799 case 0xac: case 0xad: case 0xae: case 0xaf:res=inst_mov_rn_addr(code);break;
800 case 0xb0: res= inst_anl_c_Sbit(code); break;
801 case 0xb2: res= inst_cpl_bit(code); break;
802 case 0xb3: res= inst_cpl_c(code); break;
803 case 0xb4: res= inst_cjne_a_Sdata_addr(code); break;
804 case 0xb5: res= inst_cjne_a_addr_addr(code); break;
805 case 0xb6: case 0xb7: res= inst_cjne_Sri_Sdata_addr(code); break;
806 case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc:
807 case 0xbd: case 0xbe: case 0xbf: res=inst_cjne_rn_Sdata_addr(code); break;
808 case 0xc0: res= inst_push(code); break;
809 case 0xc2: res= inst_clr_bit(code); break;
810 case 0xc3: res= inst_clr_c(code); break;
811 case 0xc4: res= inst_swap(code); break;
812 case 0xc5: res= inst_xch_a_addr(code); break;
813 case 0xc6: case 0xc7: res= inst_xch_a_Sri(code); break;
814 case 0xc8: case 0xc9: case 0xca: case 0xcb:
815 case 0xcc: case 0xcd: case 0xce: case 0xcf: res= inst_xch_a_rn(code);break;
816 case 0xd0: res= inst_pop(code); break;
817 case 0xd2: res= inst_setb_bit(code); break;
818 case 0xd3: res= inst_setb_c(code); break;
819 case 0xd4: res= inst_da_a(code); break;
820 case 0xd5: res= inst_djnz_addr_addr(code); break;
821 case 0xd6: case 0xd7: res= inst_xchd_a_Sri(code); break;
822 case 0xd8: case 0xd9: case 0xda: case 0xdb: case 0xdc:
823 case 0xdd: case 0xde: case 0xdf: res=inst_djnz_rn_addr(code); break;
824 case 0xe0: res= inst_movx_a_Sdptr(code); break;
825 case 0xe2: case 0xe3: res= inst_movx_a_Sri(code); break;
826 case 0xe4: res= inst_clr_a(code); break;
827 case 0xe5: res= inst_mov_a_addr(code); break;
828 case 0xe6: case 0xe7: res= inst_mov_a_Sri(code); break;
829 case 0xe8: case 0xe9: case 0xea: case 0xeb:
830 case 0xec: case 0xed: case 0xee: case 0xef: res= inst_mov_a_rn(code);break;
831 case 0xf0: res= inst_movx_Sdptr_a(code); break;
832 case 0xf2: case 0xf3: res= inst_movx_Sri_a(code); break;
833 case 0xf4: res= inst_cpl_a(code); break;
834 case 0xf5: res= inst_mov_addr_a(code); break;
835 case 0xf6: case 0xf7: res= inst_mov_Sri_a(code); break;
836 case 0xf8: case 0xf9: case 0xfa: case 0xfb:
837 case 0xfc: case 0xfd: case 0xfe: case 0xff: res= inst_mov_rn_a(code);break;
848 * Simulating execution of next instruction
850 * This is an endless loop if requested number of steps is negative.
851 * In this case execution is stopped if an instruction results other
852 * status than GO. Execution can be stopped if `cmd_in' is not NULL
853 * and there is input available on that file. It is usefull if the
854 * command console is on a terminal. If input is available then a
855 * complete line is read and dropped out because input is buffered
856 * (inp_avail will be TRUE if ENTER is pressed) and it can confuse
857 * command interepter.
859 //static class cl_console *c= NULL;
861 cl_51core::do_inst(int step)
864 while ((result == resGO) &&
872 interrupt->was_reti= DD_FALSE;
882 if (sim->app->get_commander()==NULL)
883 printf("no commander PC=0x%x\n",PC);
885 if (sim->app->get_commander()->frozen_console==NULL)
886 printf("no frozen console PC=0x%x\n",PC);
888 c= sim->app->get_commander()->frozen_console;
892 printf("no console PC=0x%x\n",PC);
896 /*if (result == resGO)
897 result= check_events();*/
901 // tick hw in idle state
909 if ((res= do_interrupt()) != resGO)
915 ((ticks->ticks % 100000) < 50))
917 if (sim->app->get_commander()->input_avail_on_frozen())
922 if (sim->app->get_commander()->input_avail())
925 if (((result == resINTERRUPT) &&
935 //FIXME: tick outsiders eg. watchdog
936 if (sim->app->get_commander()->input_avail_on_frozen())
938 //fprintf(stderr,"uc: inp avail in PD mode, user stop\n");
947 cl_51core::post_inst(void)
949 //uint tcon= sfr->get(TCON);
950 //uint p3= sfr->read(P3);
952 //cl_uc::post_inst();
955 // Setting up external interrupt request bits (IEx)
956 /*if ((tcon & bmIT0))
958 // IE0 edge triggered
961 // falling edge on INT0
962 sim->app->get_commander()->
963 debug("%g sec (%d clks): Falling edge detected on INT0 (P3.2)\n",
964 get_rtime(), ticks->ticks);
965 sfr->set_bit1(TCON, bmIE0);
971 // IE0 level triggered
973 sfr->set_bit0(TCON, bmIE0);
975 sfr->set_bit1(TCON, bmIE0);
979 // IE1 edge triggered
982 // falling edge on INT1
983 sfr->set_bit1(TCON, bmIE1);
989 // IE1 level triggered
991 sfr->set_bit0(TCON, bmIE1);
993 sfr->set_bit1(TCON, bmIE1);
995 //prev_p3= p3 & port_pins[3];
996 //prev_p1= p3 & port_pins[1];
1001 * Abstract method to handle WDT
1005 cl_51core::do_wdt(int cycles)
1012 * Checking for interrupt requests and accept one if needed
1016 cl_51core::do_interrupt(void)
1020 if (interrupt->was_reti)
1022 interrupt->was_reti= DD_FALSE;
1025 if (!((ie= sfr->get(IE)) & bmEA))
1027 class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
1028 for (i= 0; i < it_sources->count; i++)
1030 class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
1031 if (is->is_active() &&
1032 (ie & is->ie_mask) &&
1033 (sfr->get(is->src_reg) & is->src_mask))
1035 int pr= it_priority(is->ie_mask);
1036 if (il->level >= 0 &&
1039 if (state == stIDLE)
1042 sfr->set_bit0(PCON, bmIDL);
1043 interrupt->was_reti= DD_TRUE;
1047 sfr->set_bit0(is->src_reg, is->src_mask);
1048 sim->app->get_commander()->
1049 debug("%g sec (%d clks): Accepting interrupt `%s' PC= 0x%06x\n",
1050 get_rtime(), ticks->ticks, object_name(is), PC);
1051 IL= new it_level(pr, is->addr, PC, is);
1052 return(accept_it(IL));
1059 cl_51core::it_priority(uchar ie_mask)
1061 if (sfr->get(IP) & ie_mask)
1068 * Accept an interrupt
1072 cl_51core::accept_it(class it_level *il)
1075 sfr->set_bit0(PCON, bmIDL);
1076 it_levels->push(il);
1078 int res= inst_lcall(0, il->addr, DD_TRUE);
1082 return(resINTERRUPT);
1087 * Checking if Idle or PowerDown mode should be activated
1091 cl_51core::idle_pd(void)
1093 uint pcon= sfr->get(PCON);
1095 if (technology != CPU_CMOS)
1099 if (state != stIDLE)
1100 sim->app->get_commander()->
1101 debug("%g sec (%d clks): CPU in Idle mode (PC=0x%x, PCON=0x%x)\n",
1102 get_rtime(), ticks->ticks, PC, pcon);
1109 sim->app->get_commander()->
1110 debug("%g sec (%d clks): CPU in PowerDown mode\n",
1111 get_rtime(), ticks->ticks);
1119 * Checking if EVENT break happened
1123 cl_51core::check_events(void)
1126 class cl_ev_brk *eb;
1130 for (i= 0; i < ebrk->count; i++)
1132 eb= (class cl_ev_brk *)(ebrk->at(i));
1133 if (eb->match(&event_at))
1134 return(resBREAKPOINT);
1145 cl_51core::mem_cell_changed(class cl_m *mem, t_addr addr)
1150 case ACC: acc= mem->get_cell(ACC); break;
1151 case PSW: psw= mem->get_cell(PSW); break;
1153 cl_uc::mem_cell_changed(mem, addr);
1159 * Simulating an unknown instruction
1161 * Normally this function is called for unimplemented instructions, because
1162 * every instruction must be known!
1166 cl_51core::inst_unknown(void)
1169 class cl_error_unknown_code *e= new cl_error_unknown_code(this);
1180 cl_51core::inst_nop(uchar code)
1191 cl_51core::inst_clr_a(uchar code)
1203 cl_51core::inst_swap(uchar code)
1207 temp= (acc->read() >> 4) & 0x0f;
1208 sfr->write(ACC, (acc->get() << 4) | temp);
1216 cl_uc51_dummy_hw::cl_uc51_dummy_hw(class cl_uc *auc):
1217 cl_hw(auc, HW_DUMMY, 0, "_51_dummy")
1219 //uc51= (class cl_51core *)uc;
1223 cl_uc51_dummy_hw::init(void)
1225 class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
1228 fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
1230 //acc= sfr->register_hw(ACC, this, 0);
1231 //sp = sfr->register_hw(SP , this, 0);
1232 use_cell(sfr, PSW, &cell_psw, wtd_restore);
1233 register_cell(sfr, ACC, &cell_acc, wtd_restore_write);
1234 register_cell(sfr, SP , &cell_sp , wtd_restore);
1235 //register_cell(sfr, PCON, &cell_pcon, wtd_restore);
1240 cl_uc51_dummy_hw::write(class cl_memory_cell *cell, t_mem *val)
1242 if (cell == cell_acc)
1250 for (i= 0; i < 8; i++)
1257 cell_psw->set_bit1(bmP);
1259 cell_psw->set_bit0(bmP);
1261 else if (cell == cell_sp)
1263 if (*val > uc->sp_max)
1265 uc->sp_avg= (uc->sp_avg+(*val))/2;
1267 /*else if (cell == cell_pcon)
1269 printf("PCON write 0x%x (PC=0x%x)\n", *val, uc->PC);
1275 cl_uc51_dummy_hw::happen(class cl_hw *where, enum hw_event he, void *params)
1277 struct ev_port_changed *ep= (struct ev_port_changed *)params;
1279 if (where->cathegory == HW_PORT &&
1280 he == EV_PORT_CHANGED &&
1283 t_mem p3o= ep->pins & ep->prev_value;
1284 t_mem p3n= ep->new_pins & ep->new_value;
1285 if ((p3o & bm_INT0) &&
1287 uc51->p3_int0_edge++;
1288 if ((p3o & bm_INT1) &&
1290 uc51->p3_int1_edge++;
1295 /* End of s51.src/uc51.cc */