2 * Simulator of microcontrollers (uc390.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
8 * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
11 /* This file is part of microcontroller simulator: ucsim.
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
30 // Bernhard's ToDo list:
32 // - implement math accelerator
33 // - consider ACON bits
34 // - proc_write_sp (*aof_SP) / resSTACK_OV / event_at: insert this at the appropriate places
35 // - buy some memory to run s51 with 2*4 Meg ROM/XRAM
37 // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
38 // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
53 * Names of instructions
56 struct dis_entry disass_390f[] = {
57 { 0x00, 0xff, ' ', 1, "NOP"},
58 { 0x01, 0xff, 'A', 3, "AJMP %A"},
59 { 0x02, 0xff, 'L', 4, "LJMP %l"},
60 { 0x03, 0xff, ' ', 1, "RR A"},
61 { 0x04, 0xff, ' ', 1, "INC A"},
62 { 0x05, 0xff, ' ', 2, "INC %a"},
63 { 0x06, 0xff, ' ', 1, "INC @R0"},
64 { 0x07, 0xff, ' ', 1, "INC @R1"},
65 { 0x08, 0xff, ' ', 1, "INC R0"},
66 { 0x09, 0xff, ' ', 1, "INC R1"},
67 { 0x0a, 0xff, ' ', 1, "INC R2"},
68 { 0x0b, 0xff, ' ', 1, "INC R3"},
69 { 0x0c, 0xff, ' ', 1, "INC R4"},
70 { 0x0d, 0xff, ' ', 1, "INC R5"},
71 { 0x0e, 0xff, ' ', 1, "INC R6"},
72 { 0x0f, 0xff, ' ', 1, "INC R7"},
73 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
74 { 0x11, 0xff, 'a', 3, "ACALL %A"},
75 { 0x12, 0xff, 'l', 4, "LCALL %l"},
76 { 0x13, 0xff, ' ', 1, "RRC A"},
77 { 0x14, 0xff, ' ', 1, "DEC A"},
78 { 0x15, 0xff, ' ', 2, "DEC %a"},
79 { 0x16, 0xff, ' ', 1, "DEC @R0"},
80 { 0x17, 0xff, ' ', 1, "DEC @R1"},
81 { 0x18, 0xff, ' ', 1, "DEC R0"},
82 { 0x19, 0xff, ' ', 1, "DEC R1"},
83 { 0x1a, 0xff, ' ', 1, "DEC R2"},
84 { 0x1b, 0xff, ' ', 1, "DEC R3"},
85 { 0x1c, 0xff, ' ', 1, "DEC R4"},
86 { 0x1d, 0xff, ' ', 1, "DEC R5"},
87 { 0x1e, 0xff, ' ', 1, "DEC R6"},
88 { 0x1f, 0xff, ' ', 1, "DEC R7"},
89 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
90 { 0x21, 0xff, 'A', 3, "AJMP %A"},
91 { 0x22, 0xff, '_', 1, "RET"},
92 { 0x23, 0xff, ' ', 1, "RL A"},
93 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
94 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
95 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
96 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
97 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
98 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
99 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
100 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
101 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
102 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
103 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
104 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
105 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
106 { 0x31, 0xff, 'a', 3, "ACALL %A"},
107 { 0x32, 0xff, '_', 1, "RETI"},
108 { 0x33, 0xff, ' ', 1, "RLC A"},
109 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
110 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
111 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
112 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
113 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
114 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
115 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
116 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
117 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
118 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
119 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
120 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
121 { 0x40, 0xff, 'r', 2, "JC %r"},
122 { 0x41, 0xff, 'A', 3, "AJMP %A"},
123 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
124 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
125 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
126 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
127 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
128 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
129 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
130 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
131 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
132 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
133 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
134 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
135 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
136 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
137 { 0x50, 0xff, 'r', 2, "JNC %r"},
138 { 0x51, 0xff, 'a', 3, "ACALL %A"},
139 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
140 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
141 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
142 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
143 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
144 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
145 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
146 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
147 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
148 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
149 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
150 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
151 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
152 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
153 { 0x60, 0xff, 'r', 2, "JZ %r"},
154 { 0x61, 0xff, 'A', 3, "AJMP %A"},
155 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
156 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
157 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
158 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
159 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
160 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
161 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
162 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
163 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
164 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
165 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
166 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
167 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
168 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
169 { 0x70, 0xff, 'r', 2, "JNZ %r"},
170 { 0x71, 0xff, 'a', 3, "ACALL %A"},
171 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
172 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
173 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
174 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
175 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
176 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
177 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
178 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
179 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
180 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
181 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
182 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
183 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
184 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
185 { 0x80, 0xff, 's', 2, "SJMP %r"},
186 { 0x81, 0xff, 'A', 3, "AJMP %A"},
187 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
188 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
189 { 0x84, 0xff, ' ', 1, "DIV AB"},
190 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
191 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
192 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
193 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
194 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
195 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
196 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
197 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
198 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
199 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
200 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
201 { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
202 { 0x91, 0xff, 'a', 3, "ACALL %A"},
203 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
204 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
205 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
206 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
207 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
208 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
209 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
210 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
211 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
212 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
213 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
214 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
215 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
216 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
217 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
218 { 0xa1, 0xff, 'A', 3, "AJMP %A"},
219 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
220 { 0xa3, 0xff, ' ', 1, "INC DPTR"},
221 { 0xa4, 0xff, ' ', 1, "MUL AB"},
222 { 0xa5, 0xff, '_', 1, "-"},
223 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
224 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
225 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
226 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
227 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
228 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
229 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
230 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
231 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
232 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
233 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
234 { 0xb1, 0xff, 'a', 3, "ACALL %A"},
235 { 0xb2, 0xff, ' ', 2, "CPL %b"},
236 { 0xb3, 0xff, ' ', 1, "CPL C"},
237 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
238 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
239 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
240 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
241 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
242 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
243 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
244 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
245 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
246 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
247 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
248 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
249 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
250 { 0xc1, 0xff, 'A', 3, "AJMP %A"},
251 { 0xc2, 0xff, ' ', 2, "CLR %b"},
252 { 0xc3, 0xff, ' ', 1, "CLR C"},
253 { 0xc4, 0xff, ' ', 1, "SWAP A"},
254 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
255 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
256 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
257 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
258 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
259 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
260 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
261 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
262 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
263 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
264 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
265 { 0xd0, 0xff, ' ', 2, "POP %a"},
266 { 0xd1, 0xff, 'a', 3, "ACALL %A"},
267 { 0xd2, 0xff, ' ', 2, "SETB %b"},
268 { 0xd3, 0xff, ' ', 1, "SETB C"},
269 { 0xd4, 0xff, ' ', 1, "DA A"},
270 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
271 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
272 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
273 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
274 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
275 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
276 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
277 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
278 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
279 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
280 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
281 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
282 { 0xe1, 0xff, 'A', 3, "AJMP %A"},
283 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
284 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
285 { 0xe4, 0xff, ' ', 1, "CLR A"},
286 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
287 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
288 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
289 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
290 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
291 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
292 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
293 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
294 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
295 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
296 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
297 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
298 { 0xf1, 0xff, 'a', 3, "ACALL %A"},
299 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
300 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
301 { 0xf4, 0xff, ' ', 1, "CPL A"},
302 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
303 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
304 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
305 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
306 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
307 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
308 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
309 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
310 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
311 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
312 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
317 * Making an 390 CPU object
320 t_uc390::t_uc390 (int Itype, int Itech, class cl_sim *asim):
321 t_uc52 (Itype, Itech, asim)
323 if (Itype == CPU_DS390F)
325 printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n> ");
331 * Setting up SFR area to reset value
335 t_uc390::clear_sfr(void)
339 for (i = 0; i < SFR_SIZE; i++)
342 sfr->set(0x80, 0xff); /* P4 */
343 sfr->set(0x81, 0x07); /* SP */
344 sfr->set(0x86, 0x04); /* DPS */
345 sfr->set(0x90, 0xff); /* P1 */
346 sfr->set(0x92, 0xbf); /* P4CNT */
347 sfr->set(0x9b, 0xfc); /* ESP */
349 sfr->set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
351 sfr->set(ACON, 0xf8); /* ACON */
352 sfr->set(0xa0, 0xff); /* P2 */
353 sfr->set(0xa1, 0xff); /* P5 */
354 sfr->set(0xa3, 0x09); /* COC */
355 sfr->set(0xb0, 0xff); /* P3 */
356 sfr->set(0xb8, 0x80); /* IP */
357 sfr->set(0xc5, 0x10); /* STATUS */
358 sfr->set(0xc6, 0x10); /* MCON */
359 sfr->set(0xc7, 0xff); /* TA */
360 sfr->set(0xc9, 0xe4); /* T2MOD */
361 sfr->set(0xd2, 0x2f); /* MCNT1 */
362 sfr->set(0xe3, 0x09); /* C1C */
364 prev_p1 = port_pins[1] & sfr->get(P1);
365 prev_p3 = port_pins[3] & sfr->get(P3);
369 t_uc390::get_mem_size (enum mem_class type)
374 return 128*1024; // 4*1024*1024; 4 Meg possible
376 return 128*1024; // 4*1024*1024; 4 Meg possible
382 return 4*1024; // internal XRAM
391 t_uc390::read_mem(enum mem_class type, t_mem addr)
394 if (type == MEM_XRAM &&
396 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
401 return t_uc51::read_mem (type, addr); /* 24 bit */
405 t_uc390::get_mem (enum mem_class type, t_addr addr)
407 if (type == MEM_XRAM &&
409 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
414 return t_uc51::get_mem (type, addr);
418 t_uc390::write_mem (enum mem_class type, t_addr addr, t_mem val)
420 if (type == MEM_XRAM &&
422 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
427 t_uc51::write_mem (type, addr, val);
431 t_uc390::set_mem (enum mem_class type, t_addr addr, t_mem val)
433 if (type == MEM_XRAM &&
435 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
440 t_uc51::set_mem (type, addr, val);
444 *____________________________________________________________________________
448 t_uc390::push_byte (uchar uc)
453 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
457 if (get_mem (MEM_SFR, SP) == 0x00) /* overflow SP */
459 sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
460 get_mem (MEM_SFR, SP);
461 write_mem (MEM_IXRAM, sp10, uc);
468 sp = get_indirect (sfr->get (SP), &res);
477 t_uc390::pop_byte (int *Pres)
481 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
485 sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
486 get_mem (MEM_SFR, SP);
488 if (get_mem (MEM_SFR, SP) == 0xff) /* underflow SP */
490 uc = get_mem (MEM_IXRAM, sp10);
497 sp = get_indirect (get_mem (MEM_SFR, SP), Pres);
508 *____________________________________________________________________________
513 t_uc390::inst_inc_dptr (uchar code)
517 uchar pl, ph, px, dps;
519 dps = sfr->get (DPS);
533 dptr = sfr->get (ph) * 256 + sfr->get (pl);
534 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
535 dptr += sfr->get (px) *256*256;
536 if (dps & 0x80) /* decr set */
541 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
542 sfr->set (px, (dptr >> 16) & 0xff);
543 sfr->set (event_at.ws = ph, (dptr >> 8) & 0xff);
544 sfr->set (pl, dptr & 0xff);
546 if (dps & 0x20) /* auto-switch dptr */
547 sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
553 * 0x73 1 24 JMP @A+DPTR
554 *____________________________________________________________________________
559 t_uc390::inst_jmp_$a_dptr (uchar code)
561 uchar pl, ph, px, dps;
563 dps = sfr->get (DPS);
577 PC = (sfr->get (ph) * 256 + sfr->get (pl) +
578 read_mem (MEM_SFR, ACC)) &
580 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
581 PC += sfr->get (px) * 256*256;
588 * 0x90 3 24 MOV DPTR,#data
589 *____________________________________________________________________________
594 t_uc390::inst_mov_dptr_$data (uchar code)
596 uchar pl, ph, px, dps;
598 dps = sfr->get (DPS);
612 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
613 sfr->set (px, fetch ());
614 sfr->set (event_at.ws = ph, fetch ());
615 sfr->set (pl, fetch ());
617 if (dps & 0x20) /* auto-switch dptr */
618 sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
626 * 0x93 1 24 MOVC A,@A+DPTR
627 *____________________________________________________________________________
632 t_uc390::inst_movc_a_$a_dptr (uchar code)
634 uchar pl, ph, px, dps;
636 dps = sfr->get (DPS);
650 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
651 sfr->set (ACC, get_mem (MEM_ROM,
653 (sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl) +
654 sfr->get (ACC)) & (EROM_SIZE-1)));
656 sfr->set (ACC, get_mem (MEM_ROM, event_at.rc =
657 (sfr->get (ph) * 256 + sfr->get (pl) +
658 sfr->get (ACC)) & (EROM_SIZE-1)));
660 if (dps & 0x20) /* auto-switch dptr */
661 sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
668 * 0xc0 2 24 PUSH addr
669 *____________________________________________________________________________
674 t_uc390::inst_push (uchar code)
679 addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
680 res = push_byte (read (addr));
688 *____________________________________________________________________________
693 t_uc390::inst_pop (uchar code)
698 addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
699 *addr = pop_byte (&res);
707 * 0xe0 1 24 MOVX A,@DPTR
708 *____________________________________________________________________________
713 t_uc390::inst_movx_a_$dptr (uchar code)
715 uchar pl, ph, px, dps;
717 dps = sfr->get (DPS);
731 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
732 sfr->set (event_at.ws = ACC,
734 event_at.rx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl)));
736 sfr->set (event_at.ws = ACC,
738 event_at.rx = sfr->get (ph) * 256 + sfr->get (pl)));
740 if (dps & 0x20) /* auto-switch dptr */
741 sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
748 * 0xf0 1 24 MOVX @DPTR,A
749 *____________________________________________________________________________
754 t_uc390::inst_movx_$dptr_a (uchar code)
756 uchar pl, ph, px, dps;
758 dps = sfr->get (DPS);
772 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
774 event_at.wx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl),
775 sfr->get (event_at.rs = ACC));
778 event_at.wx = sfr->get (ph) * 256 + sfr->get (pl),
779 sfr->get (event_at.rs = ACC));
781 if (dps & 0x20) /* auto-switch dptr */
782 sfr->set (DPS, dps ^ 1); /* toggle dual-dptr switch */
789 * 0x[02468ace]1 2 24 AJMP addr
790 *____________________________________________________________________________
795 t_uc390::inst_ajmp_addr (uchar code)
799 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
801 x = (code >> 5) & 0x07;
804 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
808 h = (code >> 5) & 0x07;
810 PC = (PC & 0xf800) | (h * 256 + l);
817 * 0x02 3 24 LJMP addr
818 *____________________________________________________________________________
823 t_uc390::inst_ljmp (uchar code)
827 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
832 PC = x * 256*256 + h * 256 + l;
845 * 0x[13579bdf]1 2 24 ACALL addr
846 *____________________________________________________________________________
851 t_uc390::inst_acall_addr (uchar code)
853 uchar x, h, l, *sp, *aof_SP;
856 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
858 x = (code >> 5) & 0x07;
862 res = push_byte ( PC & 0xff); /* push low byte */
863 res = push_byte ((PC >> 8) & 0xff); /* push high byte */
864 res = push_byte ((PC >> 16) & 0xff); /* push x byte */
866 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
870 /* stock mcs51 mode */
871 h = (code >> 5) & 0x07;
873 aof_SP = &((sfr->umem8)[SP]);
875 //MEM(MEM_SFR)[SP]++;
877 proc_write_sp (*aof_SP);
878 sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
881 *sp = PC & 0xff; // push low byte
883 //MEM(MEM_SFR)[SP]++;
885 proc_write_sp (*aof_SP);
886 sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
889 *sp = (PC >> 8) & 0xff; // push high byte
891 PC = (PC & 0xf800) | (h * 256 + l);
899 * 0x12 3 24 LCALL addr
900 *____________________________________________________________________________
905 t_uc390::inst_lcall (uchar code, uint addr)
907 uchar x = 0, h = 0, l = 0;
911 { /* this is a normal lcall */
912 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
917 /* else, this is interrupt processing */
919 res = push_byte ( PC & 0xff); /* push low byte */
920 res = push_byte ((PC >> 8) & 0xff); /* push high byte */
922 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
924 res = push_byte ((PC >> 16) & 0xff); /* push x byte */
926 PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
928 PC = x * 256*256 + h * 256 + l;
942 *____________________________________________________________________________
947 t_uc390::inst_ret (uchar code)
952 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
959 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
962 PC = x * 256*256 + h * 256 + l;
972 *____________________________________________________________________________
977 t_uc390::inst_reti (uchar code)
982 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
988 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
991 PC = x * 256*256 + h * 256 + l;
997 class it_level *il = (class it_level *) (it_levels->top ());
1001 il = (class it_level *) (it_levels->pop ());
1009 * Processing write operation to IRAM
1011 * It starts serial transmition if address is in SFR and it is
1012 * SBUF. Effect on IE is also checked.
1016 t_uc390::proc_write(uchar *addr)
1018 if (addr == &((sfr->umem8)[SBUF]))
1020 s_out= sfr->get(SBUF);
1026 else if (addr == &((sfr->umem8)[IE]))
1028 else if (addr == &((sfr->umem8)[DPS]))
1033 else if (addr == &((sfr->umem8)[EXIF]))
1036 else if (addr == &((sfr->umem8)[P4CNT]))
1040 else if (addr == &((sfr->umem8)[ACON]))
1043 /* lockout: IDM1:IDM0 and SA can't be set at the same time */
1044 if (((sfr->umem8)[MCON] & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */
1045 *addr &= ~0x04; /* lockout SA */
1047 else if (addr == &((sfr->umem8)[P5CNT]))
1051 else if (addr == &((sfr->umem8)[C0C]))
1055 else if (addr == &((sfr->umem8)[PMR]))
1058 // todo: check previous state
1059 if ((*addr & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */
1061 ctm_ticks = ticks->ticks;
1062 (sfr->umem8)[EXIF] &= ~0x08; /* clear CKRDY */
1067 else if (addr == &((sfr->umem8)[MCON]))
1070 /* lockout: IDM1:IDM0 and SA can't be set at the same time */
1071 if (((sfr->umem8)[ACON] & 0x04) == 0x04) /* SA set? */
1072 *addr &= ~0xc0; /* lockout IDM1:IDM0 */
1074 else if (addr == &((sfr->umem8)[TA]))
1078 timed_access_ticks = ticks->ticks;
1079 timed_access_state = 1;
1081 else if (*addr == 0xaa &&
1082 timed_access_state == 1 &&
1083 timed_access_ticks == ticks->ticks + 1)
1085 timed_access_ticks = ticks->ticks;
1086 timed_access_state = 2;
1089 timed_access_state = 0;
1091 else if (addr == &((sfr->umem8)[T2MOD]))
1093 else if (addr == &((sfr->umem8)[COR]))
1097 else if (addr == &((sfr->umem8)[WDCON]))
1101 else if (addr == &((sfr->umem8)[C1C]))
1105 else if (addr == &((sfr->umem8)[MCNT1]))
1111 * Reading IRAM or SFR, but if address points to a port, it reads
1112 * port pins instead of port latches
1116 t_uc390::read(uchar *addr)
1118 //if (addr == &(MEM(MEM_SFR)[P1]))
1119 if (addr == &(sfr->umem8[P1]))
1120 return get_mem (MEM_SFR, P1) & port_pins[1];
1121 //if (addr == &(MEM(MEM_SFR)[P2]))
1122 else if (addr == &(sfr->umem8[P2]))
1123 return get_mem (MEM_SFR, P2) & port_pins[2];
1124 //if (addr == &(MEM(MEM_SFR)[P3]))
1125 else if (addr == &(sfr->umem8[P3]))
1126 return get_mem (MEM_SFR, P3) & port_pins[3];
1127 //if (addr == &(MEM(MEM_SFR)[P4]))
1128 else if (addr == &(sfr->umem8[P4]))
1129 return get_mem (MEM_SFR, P4) & port_pins[4];
1130 //if (addr == &(MEM(MEM_SFR)[P5]))
1131 else if (addr == &(sfr->umem8[P5]))
1132 return get_mem (MEM_SFR, P5) & port_pins[5];
1133 else if (addr == &(sfr->umem8[EXIF]))
1135 ticks->ticks >= ctm_ticks + 65535)
1137 *addr |= 0x08; /* set CKRDY */
1145 * Disassembling an instruction
1149 t_uc390::dis_tbl (void)
1151 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1155 //t_uc51::dis_tbl ();
1160 t_uc390::disass (t_addr addr, char *sep)
1162 char work[256], temp[20], c[2];
1163 char *buf, *p, *b, *t;
1166 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1167 return t_uc51::disass (addr, sep);
1168 code = get_mem (MEM_ROM, addr);
1171 b = dis_tbl ()[code].mnemonic;
1179 case 'A': // absolute address
1181 // sprintf (temp, "%04lx",
1183 // (((code >> 5) & 0x07) * 256 +
1184 // get_mem (MEM_ROM, addr + 1)));
1186 sprintf (temp, "%06lx",
1188 (((code >> 5) & 0x07) * (256 * 256) +
1189 (get_mem (MEM_ROM, addr + 1) * 256) +
1190 get_mem (MEM_ROM, addr + 2)));
1192 case 'l': // long address
1193 sprintf (temp, "%06lx",
1194 get_mem (MEM_ROM, addr + 1) * (256*256) +
1195 get_mem (MEM_ROM, addr + 2) * 256 +
1196 get_mem (MEM_ROM, addr + 3));
1197 // get_mem (MEM_ROM, addr + 1) * 256 + get_mem (MEM_ROM, addr + 2));
1199 case 'a': // addr8 (direct address) at 2nd byte
1200 if (!get_name (get_mem (MEM_ROM, addr + 1), sfr_tbl (), temp))
1201 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1203 case '8': // addr8 (direct address) at 3rd byte
1204 if (!get_name (get_mem (MEM_ROM, addr + 2), sfr_tbl (), temp))
1205 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1206 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
1208 case 'b': // bitaddr at 2nd byte
1209 if (get_name (get_mem (MEM_ROM, addr + 1), bit_tbl (), temp))
1211 if (get_name (get_bitidx (get_mem (MEM_ROM, addr + 1)),
1215 sprintf (c, "%1ld", get_mem (MEM_ROM, addr + 1) & 0x07);
1219 sprintf (temp, "%02x.%ld",
1220 get_bitidx (get_mem (MEM_ROM, addr + 1)),
1221 get_mem (MEM_ROM, addr + 1) & 0x07);
1223 case 'r': // rel8 address at 2nd byte
1224 sprintf (temp, "%04lx",
1225 addr + 2 + (signed char) (get_mem (MEM_ROM, addr + 1)));
1227 case 'R': // rel8 address at 3rd byte
1228 sprintf (temp, "%04lx",
1229 addr + 3 + (signed char) (get_mem (MEM_ROM, addr + 2)));
1231 case 'd': // data8 at 2nd byte
1232 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1234 case 'D': // data8 at 3rd byte
1235 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
1250 p = strchr (work, ' ');
1253 buf = strdup (work);
1257 buf = (char *) malloc (6 + strlen (p) + 1);
1259 buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
1260 for (p = work, b = buf; *p != ' '; p++, b++)
1265 while (strlen (buf) < 6)
1274 t_uc390::print_regs (class cl_console *con)
1279 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1281 t_uc51::print_regs (con);
1284 start = sfr->get (PSW) & 0x18;
1285 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
1286 iram->dump (start, start + 7, 8, con);
1287 start = sfr->get (PSW) & 0x18;
1288 data = iram->get (iram->get (start));
1289 con->dd_printf("%06x %02x %c",
1290 iram->get (start), data, isprint (data) ? data : '.');
1291 con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x",
1292 sfr->get (ACC), sfr->get (ACC),
1293 isprint (sfr->get (ACC)) ?
1294 (sfr->get (ACC)) : '.', sfr->get (B));
1296 data = get_mem (MEM_XRAM,
1297 sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
1298 con->dd_printf (" DPTR= 0x%02x%02x%02x @DPTR= 0x%02x %3d %c\n",
1299 sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
1300 data, data, isprint (data) ? data : '.');
1301 data = iram->get (iram->get (start + 1));
1302 con->dd_printf ("%06x %02x %c", iram->get (start + 1), data,
1303 isprint (data) ? data : '.');
1304 data= sfr->get (PSW);
1305 con->dd_printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
1307 (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
1308 (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0'
1310 /* show stack pointer */
1311 if (sfr->get (ACON) & 0x04)
1312 /* SA: 10 bit stack */
1313 con->dd_printf ("SP10 0x%03x %3d\n",
1314 (sfr->get (ESP) & 3) * 256 + sfr->get (SP),
1315 get_mem (MEM_IXRAM, (sfr->get (ESP) & 3) * 256 + sfr->get (SP))
1318 con->dd_printf ("SP 0x%02x %3d\n",
1320 iram->get (sfr->get (SP))
1322 print_disass (PC, con);
1324 /* End of s51.src/uc390.cc */