2 * Simulator of microcontrollers (uc390.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
8 * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
11 /* This file is part of microcontroller simulator: ucsim.
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
30 // Bernhard's ToDo list:
32 // - add sfr-descriptions to s51.src/glob.cc
33 // - implement math accelerator
34 // - consider ACON bits
35 // - proc_write_sp (*aof_SP); insert this at the appropriate places
36 // - buy some memory to run s51 with 2*4 Meg ROM/XRAM
50 * Names of instructions
53 struct dis_entry disass_390f[] = {
54 { 0x00, 0xff, ' ', 1, "NOP"},
55 { 0x01, 0xff, 'A', 3, "AJMP %A"},
56 { 0x02, 0xff, 'L', 4, "LJMP %l"},
57 { 0x03, 0xff, ' ', 1, "RR A"},
58 { 0x04, 0xff, ' ', 1, "INC A"},
59 { 0x05, 0xff, ' ', 2, "INC %a"},
60 { 0x06, 0xff, ' ', 1, "INC @R0"},
61 { 0x07, 0xff, ' ', 1, "INC @R1"},
62 { 0x08, 0xff, ' ', 1, "INC R0"},
63 { 0x09, 0xff, ' ', 1, "INC R1"},
64 { 0x0a, 0xff, ' ', 1, "INC R2"},
65 { 0x0b, 0xff, ' ', 1, "INC R3"},
66 { 0x0c, 0xff, ' ', 1, "INC R4"},
67 { 0x0d, 0xff, ' ', 1, "INC R5"},
68 { 0x0e, 0xff, ' ', 1, "INC R6"},
69 { 0x0f, 0xff, ' ', 1, "INC R7"},
70 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
71 { 0x11, 0xff, 'a', 3, "ACALL %A"},
72 { 0x12, 0xff, 'l', 4, "LCALL %l"},
73 { 0x13, 0xff, ' ', 1, "RRC A"},
74 { 0x14, 0xff, ' ', 1, "DEC A"},
75 { 0x15, 0xff, ' ', 2, "DEC %a"},
76 { 0x16, 0xff, ' ', 1, "DEC @R0"},
77 { 0x17, 0xff, ' ', 1, "DEC @R1"},
78 { 0x18, 0xff, ' ', 1, "DEC R0"},
79 { 0x19, 0xff, ' ', 1, "DEC R1"},
80 { 0x1a, 0xff, ' ', 1, "DEC R2"},
81 { 0x1b, 0xff, ' ', 1, "DEC R3"},
82 { 0x1c, 0xff, ' ', 1, "DEC R4"},
83 { 0x1d, 0xff, ' ', 1, "DEC R5"},
84 { 0x1e, 0xff, ' ', 1, "DEC R6"},
85 { 0x1f, 0xff, ' ', 1, "DEC R7"},
86 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
87 { 0x21, 0xff, 'A', 3, "AJMP %A"},
88 { 0x22, 0xff, '_', 1, "RET"},
89 { 0x23, 0xff, ' ', 1, "RL A"},
90 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
91 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
92 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
93 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
94 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
95 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
96 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
97 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
98 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
99 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
100 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
101 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
102 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
103 { 0x31, 0xff, 'a', 3, "ACALL %A"},
104 { 0x32, 0xff, '_', 1, "RETI"},
105 { 0x33, 0xff, ' ', 1, "RLC A"},
106 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
107 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
108 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
109 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
110 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
111 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
112 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
113 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
114 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
115 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
116 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
117 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
118 { 0x40, 0xff, 'r', 2, "JC %r"},
119 { 0x41, 0xff, 'A', 3, "AJMP %A"},
120 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
121 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
122 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
123 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
124 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
125 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
126 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
127 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
128 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
129 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
130 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
131 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
132 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
133 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
134 { 0x50, 0xff, 'r', 2, "JNC %r"},
135 { 0x51, 0xff, 'a', 3, "ACALL %A"},
136 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
137 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
138 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
139 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
140 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
141 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
142 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
143 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
144 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
145 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
146 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
147 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
148 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
149 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
150 { 0x60, 0xff, 'r', 2, "JZ %r"},
151 { 0x61, 0xff, 'A', 3, "AJMP %A"},
152 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
153 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
154 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
155 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
156 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
157 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
158 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
159 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
160 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
161 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
162 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
163 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
164 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
165 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
166 { 0x70, 0xff, 'r', 2, "JNZ %r"},
167 { 0x71, 0xff, 'a', 3, "ACALL %A"},
168 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
169 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
170 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
171 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
172 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
173 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
174 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
175 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
176 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
177 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
178 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
179 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
180 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
181 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
182 { 0x80, 0xff, 's', 2, "SJMP %r"},
183 { 0x81, 0xff, 'A', 3, "AJMP %A"},
184 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
185 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
186 { 0x84, 0xff, ' ', 1, "DIV AB"},
187 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
188 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
189 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
190 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
191 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
192 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
193 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
194 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
195 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
196 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
197 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
198 { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
199 { 0x91, 0xff, 'a', 3, "ACALL %A"},
200 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
201 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
202 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
203 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
204 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
205 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
206 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
207 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
208 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
209 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
210 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
211 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
212 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
213 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
214 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
215 { 0xa1, 0xff, 'A', 3, "AJMP %A"},
216 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
217 { 0xa3, 0xff, ' ', 1, "INC DPTR"},
218 { 0xa4, 0xff, ' ', 1, "MUL AB"},
219 { 0xa5, 0xff, '_', 1, "-"},
220 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
221 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
222 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
223 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
224 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
225 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
226 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
227 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
228 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
229 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
230 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
231 { 0xb1, 0xff, 'a', 3, "ACALL %A"},
232 { 0xb2, 0xff, ' ', 2, "CPL %b"},
233 { 0xb3, 0xff, ' ', 1, "CPL C"},
234 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
235 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
236 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
237 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
238 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
239 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
240 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
241 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
242 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
243 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
244 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
245 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
246 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
247 { 0xc1, 0xff, 'A', 3, "AJMP %A"},
248 { 0xc2, 0xff, ' ', 2, "CLR %b"},
249 { 0xc3, 0xff, ' ', 1, "CLR C"},
250 { 0xc4, 0xff, ' ', 1, "SWAP A"},
251 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
252 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
253 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
254 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
255 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
256 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
257 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
258 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
259 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
260 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
261 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
262 { 0xd0, 0xff, ' ', 2, "POP %a"},
263 { 0xd1, 0xff, 'a', 3, "ACALL %A"},
264 { 0xd2, 0xff, ' ', 2, "SETB %b"},
265 { 0xd3, 0xff, ' ', 1, "SETB C"},
266 { 0xd4, 0xff, ' ', 1, "DA A"},
267 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
268 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
269 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
270 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
271 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
272 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
273 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
274 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
275 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
276 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
277 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
278 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
279 { 0xe1, 0xff, 'A', 3, "AJMP %A"},
280 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
281 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
282 { 0xe4, 0xff, ' ', 1, "CLR A"},
283 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
284 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
285 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
286 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
287 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
288 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
289 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
290 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
291 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
292 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
293 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
294 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
295 { 0xf1, 0xff, 'a', 3, "ACALL %A"},
296 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
297 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
298 { 0xf4, 0xff, ' ', 1, "CPL A"},
299 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
300 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
301 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
302 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
303 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
304 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
305 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
306 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
307 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
308 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
309 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
314 * Making an 390 CPU object
317 t_uc390::t_uc390 (int Itype, int Itech, class cl_sim *asim):
318 t_uc52 (Itype, Itech, asim)
320 if (Itype == CPU_DS390F)
322 printf ("FLAT24 MODE SET, warning: experimental code\n");
327 // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
328 // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
331 t_uc390::get_mem_size (enum mem_class type)
333 //if ((sfr->get (ACON) & 0x3) == 2)
335 return t_uc52::get_mem_size (type);
339 return 128*1024; // 4*1024*1024; 4 Meg possible
341 return 128*1024; // 4*1024*1024; 4 Meg possible
347 return 4*1024; // internal XRAM
356 t_uc390::read_mem(enum mem_class type, t_mem addr)
358 //if ((sfr->get (ACON) & 0x3) == 2)
360 if (type == MEM_XRAM &&
367 return t_uc51::read_mem (type, addr);
371 t_uc390::get_mem (enum mem_class type, t_addr addr)
373 if (type == MEM_XRAM &&
380 return t_uc51::get_mem (type, addr);
384 t_uc390::write_mem (enum mem_class type, t_addr addr, t_mem val)
386 if (type == MEM_XRAM &&
393 t_uc51::write_mem (type, addr, val);
397 t_uc390::set_mem (enum mem_class type, t_addr addr, t_mem val)
399 if (type == MEM_XRAM &&
406 t_uc51::set_mem (type, addr, val);
410 *____________________________________________________________________________
414 t_uc390::push_byte (uchar uc)
419 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
423 if (get_mem (MEM_SFR, SP) == 0x00) /* overflow SP */
425 sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
426 get_mem (MEM_SFR, SP);
427 write_mem (MEM_IXRAM, sp10, uc);
434 sp = get_indirect (sfr->get (SP), &res);
443 t_uc390::pop_byte (int *Pres)
447 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
451 sp10 = (get_mem (MEM_SFR, ESP) & 0x3) * 256 +
452 get_mem (MEM_SFR, SP);
454 if (get_mem (MEM_SFR, SP) == 0xff) /* underflow SP */
456 uc = get_mem (MEM_IXRAM, sp10);
463 sp = get_indirect (get_mem (MEM_SFR, SP), Pres);
474 *____________________________________________________________________________
478 t_uc390::inst_inc_addr (uchar code)
482 addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
484 /* mask off the 2Hex bit adjacent to the 1H bit which selects
485 which DPTR we use. This is a feature of 80C390.
486 You can do INC DPS and it only effects bit 1. */
488 (*addr) ^= 1; /* just toggle */
498 *____________________________________________________________________________
503 t_uc390::inst_inc_dptr (uchar code)
507 uchar pl, ph, px, dps;
509 dps = sfr->get (DPS);
523 dptr = sfr->get (ph) * 256 + sfr->get (pl);
524 //if ((sfr->get (ACON) & 0x3) == 2)
526 dptr += sfr->get (px) *256*256;
527 if (dps & 0x80) /* decr set */
532 //if ((sfr->get (ACON) & 0x3) == 2)
534 sfr->set (px, (dptr >> 16) & 0xff);
535 sfr->set (event_at.ws = ph, (dptr >> 8) & 0xff);
536 sfr->set (pl, dptr & 0xff);
538 if (dps & 0x20) /* auto-switch dptr */
539 sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */
545 * 0x73 1 24 JMP @A+DPTR
546 *____________________________________________________________________________
551 t_uc390::inst_jmp_$a_dptr (uchar code)
553 uchar pl, ph, px, dps;
555 dps = sfr->get (DPS);
569 PC = (sfr->get (ph) * 256 + sfr->get (pl) +
570 read_mem (MEM_SFR, ACC)) &
572 //if ((sfr->get (ACON) & 0x3) == 2)
574 PC += sfr->get (px) * 256*256;
581 * 0x90 3 24 MOV DPTR,#data
582 *____________________________________________________________________________
587 t_uc390::inst_mov_dptr_$data (uchar code)
589 uchar pl, ph, px, dps;
591 dps = sfr->get (DPS);
605 //if ((sfr->get (ACON) & 0x3) == 2)
607 sfr->set (px, fetch ());
608 sfr->set (event_at.ws = ph, fetch ());
609 sfr->set (pl, fetch ());
611 if (dps & 0x20) /* auto-switch dptr */
612 sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */
620 * 0x93 1 24 MOVC A,@A+DPTR
621 *____________________________________________________________________________
626 t_uc390::inst_movc_a_$a_dptr (uchar code)
628 uchar pl, ph, px, dps;
630 dps = sfr->get (DPS);
644 //if ((sfr->get (ACON) & 0x3) == 2)
646 sfr->set (ACC, get_mem (MEM_ROM,
648 (sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl) +
649 sfr->get (ACC)) & (EROM_SIZE-1)));
651 sfr->set (ACC, get_mem (MEM_ROM, event_at.rc =
652 (sfr->get (ph) * 256 + sfr->get (pl) +
653 sfr->get (ACC)) & (EROM_SIZE-1)));
655 if (dps & 0x20) /* auto-switch dptr */
656 sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */
663 * 0xc0 2 24 PUSH addr
664 *____________________________________________________________________________
669 t_uc390::inst_push (uchar code)
674 addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
675 res = push_byte (read (addr));
683 *____________________________________________________________________________
688 t_uc390::inst_pop (uchar code)
693 addr = get_direct (fetch (), &event_at.wi, &event_at.ws);
694 *addr = pop_byte (&res);
702 * 0xe0 1 24 MOVX A,@DPTR
703 *____________________________________________________________________________
708 t_uc390::inst_movx_a_$dptr (uchar code)
710 uchar pl, ph, px, dps;
712 dps = sfr->get (DPS);
726 //if ((sfr->get (ACON) & 0x3) == 2)
728 sfr->set (event_at.ws = ACC,
730 event_at.rx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl)));
732 sfr->set (event_at.ws = ACC,
734 event_at.rx = sfr->get (ph) * 256 + sfr->get (pl)));
736 if (dps & 0x20) /* auto-switch dptr */
737 sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */
744 * 0xf0 1 24 MOVX @DPTR,A
745 *____________________________________________________________________________
750 t_uc390::inst_movx_$dptr_a (uchar code)
752 uchar pl, ph, px, dps;
754 dps = sfr->get (DPS);
768 //if ((sfr->get (ACON) & 0x3) == 2)
771 event_at.wx = sfr->get (px) * 256*256 + sfr->get (ph) * 256 + sfr->get (pl),
772 sfr->get (event_at.rs = ACC));
775 event_at.wx = sfr->get (ph) * 256 + sfr->get (pl),
776 sfr->get (event_at.rs = ACC));
778 if (dps & 0x20) /* auto-switch dptr */
779 sfr->set (DPS, (dps ^ 1)); /* toggle dual-dptr switch */
786 * 0x[02468ace]1 2 24 AJMP addr
787 *____________________________________________________________________________
792 t_uc390::inst_ajmp_addr (uchar code)
796 //if ((sfr->get (ACON) & 0x3) == 2)
799 x = (code >> 5) & 0x07;
802 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
806 h = (code >> 5) & 0x07;
808 PC = (PC & 0xf800) | (h * 256 + l);
815 * 0x02 3 24 LJMP addr
816 *____________________________________________________________________________
821 t_uc390::inst_ljmp (uchar code)
825 //if ((sfr->get (ACON) & 0x3) == 2)
831 PC = x * 256*256 + h * 256 + l;
844 * 0x[13579bdf]1 2 24 ACALL addr
845 *____________________________________________________________________________
850 t_uc390::inst_acall_addr (uchar code)
852 uchar x, h, l, *sp, *aof_SP;
855 //if ((sfr->get (ACON) & 0x3) == 2)
858 x = (code >> 5) & 0x07;
862 res = push_byte ( PC & 0xff); /* push low byte */
863 res = push_byte ((PC >> 8) & 0xff); /* push high byte */
864 res = push_byte ((PC >> 16) & 0xff); /* push x byte */
866 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
870 /* stock mcs51 mode */
871 h = (code >> 5) & 0x07;
873 aof_SP = &((sfr->umem8)[SP]);
875 //MEM(MEM_SFR)[SP]++;
877 proc_write_sp (*aof_SP);
878 sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
881 *sp = PC & 0xff; // push low byte
883 //MEM(MEM_SFR)[SP]++;
885 proc_write_sp (*aof_SP);
886 sp = get_indirect (*aof_SP/*sfr->get (SP)*/, &res);
889 *sp = (PC >> 8) & 0xff; // push high byte
891 PC = (PC & 0xf800) | (h * 256 + l);
899 * 0x12 3 24 LCALL addr
900 *____________________________________________________________________________
905 t_uc390::inst_lcall (uchar code, uint addr)
907 uchar x = 0, h = 0, l = 0;
911 { /* this is a normal lcall */
912 //if ((sfr->get (ACON) & 0x3) == 2)
918 /* else, this is interrupt processing */
920 res = push_byte ( PC & 0xff); /* push low byte */
921 res = push_byte ((PC >> 8) & 0xff); /* push high byte */
923 //if ((sfr->get (ACON) & 0x3) == 2)
926 res = push_byte ((PC >> 16) & 0xff); /* push x byte */
928 PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
930 PC = x * 256*256 + h * 256 + l;
944 *____________________________________________________________________________
949 t_uc390::inst_ret (uchar code)
954 //if ((sfr->get (ACON) & 0x3) == 2)
962 //if ((sfr->get (ACON) & 0x3) == 2)
966 PC = x * 256*256 + h * 256 + l;
976 *____________________________________________________________________________
981 t_uc390::inst_reti (uchar code)
986 //if ((sfr->get (ACON) & 0x3) == 2)
994 //if ((sfr->get (ACON) & 0x3) == 2)
998 PC = x * 256*256 + h * 256 + l;
1004 class it_level *il = (class it_level *) (it_levels->top ());
1008 il = (class it_level *) (it_levels->pop ());
1016 * Disassembling an instruction
1020 t_uc390::dis_tbl (void)
1022 //if ((sfr->get (ACON) & 0x3) == 2)
1025 //t_uc51::dis_tbl ();
1031 t_uc390::disass (t_addr addr, char *sep)
1033 char work[256], temp[20], c[2];
1034 char *buf, *p, *b, *t;
1037 //if ((sfr->get (ACON) & 0x3) == 2)
1039 return t_uc51::disass (addr, sep);
1040 code = get_mem (MEM_ROM, addr);
1043 b = dis_tbl ()[code].mnemonic;
1051 case 'A': // absolute address
1053 // sprintf (temp, "%04lx",
1055 // (((code >> 5) & 0x07) * 256 +
1056 // get_mem (MEM_ROM, addr + 1)));
1058 sprintf (temp, "%06lx",
1060 (((code >> 5) & 0x07) * (256 * 256) +
1061 (get_mem (MEM_ROM, addr + 1) * 256) +
1062 get_mem (MEM_ROM, addr + 2)));
1064 case 'l': // long address
1065 sprintf (temp, "%06lx",
1066 get_mem (MEM_ROM, addr + 1) * (256*256) +
1067 get_mem (MEM_ROM, addr + 2) * 256 +
1068 get_mem (MEM_ROM, addr + 3));
1069 // get_mem (MEM_ROM, addr + 1) * 256 + get_mem (MEM_ROM, addr + 2));
1071 case 'a': // addr8 (direct address) at 2nd byte
1072 if (!get_name (get_mem (MEM_ROM, addr + 1), sfr_tbl (), temp))
1073 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1075 case '8': // addr8 (direct address) at 3rd byte
1076 if (!get_name (get_mem (MEM_ROM, addr + 2), sfr_tbl (), temp))
1077 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1078 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
1080 case 'b': // bitaddr at 2nd byte
1081 if (get_name (get_mem (MEM_ROM, addr + 1), bit_tbl (), temp))
1083 if (get_name (get_bitidx (get_mem (MEM_ROM, addr + 1)),
1087 sprintf (c, "%1ld", get_mem (MEM_ROM, addr + 1) & 0x07);
1091 sprintf (temp, "%02x.%ld",
1092 get_bitidx (get_mem (MEM_ROM, addr + 1)),
1093 get_mem (MEM_ROM, addr + 1) & 0x07);
1095 case 'r': // rel8 address at 2nd byte
1096 sprintf (temp, "%04lx",
1097 addr + 2 + (signed char) (get_mem (MEM_ROM, addr + 1)));
1099 case 'R': // rel8 address at 3rd byte
1100 sprintf (temp, "%04lx",
1101 addr + 3 + (signed char) (get_mem (MEM_ROM, addr + 2)));
1103 case 'd': // data8 at 2nd byte
1104 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 1));
1106 case 'D': // data8 at 3rd byte
1107 sprintf (temp, "%02lx", get_mem (MEM_ROM, addr + 2));
1122 p = strchr (work, ' ');
1125 buf = strdup (work);
1129 buf = (char *) malloc (6 + strlen (p) + 1);
1131 buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
1132 for (p = work, b = buf; *p != ' '; p++, b++)
1137 while (strlen (buf) < 6)
1146 t_uc390::print_regs(class cl_console *con)
1151 //if ((sfr->get (ACON) & 0x3) == 2)
1154 t_uc51::print_regs (con);
1157 start = sfr->get (PSW) & 0x18;
1158 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
1159 iram->dump (start, start + 7, 8, con);
1160 start = sfr->get (PSW) & 0x18;
1161 data = iram->get (iram->get (start));
1162 con->printf ("%06x %02x %c",
1163 iram->get (start), data, isprint (data) ? data : '.');
1164 con->printf (" ACC= 0x%02x %3d %c B= 0x%02x",
1165 sfr->get (ACC), sfr->get (ACC),
1166 isprint (sfr->get (ACC)) ? (sfr->get (ACC)) : '.', sfr->get (B));
1168 data = get_mem (MEM_XRAM,
1169 sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
1170 con->printf (" DPTR= 0x%02x%02x%02x @DPTR= 0x%02x %3d %c\n",
1171 sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
1172 data, data, isprint (data) ? data : '.');
1173 data = iram->get (iram->get (start + 1));
1174 con->printf ("%06x %02x %c", iram->get (start + 1), data,
1175 isprint (data) ? data : '.');
1176 data= sfr->get (PSW);
1177 con->printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
1179 (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
1180 (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0'
1182 /* show stack pointer */
1183 if (sfr->get (ACON) & 0x04)
1184 /* SA: 10 bit stack */
1185 con->printf ("SP10 0x%03x %3d\n",
1186 (sfr->get (ESP) & 3) * 256 + sfr->get (SP),
1187 get_mem (MEM_IXRAM, (sfr->get (ESP) & 3) * 256 + sfr->get (SP))
1190 con->printf ("SP 0x%02x %3d\n",
1192 iram->get (sfr->get (SP))
1194 print_disass (PC, con);
1196 /* End of s51.src/uc390.cc */