2 * Simulator of microcontrollers (uc390.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
8 * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
11 /* This file is part of microcontroller simulator: ucsim.
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
40 * Names of instructions
43 struct dis_entry disass_390f[]= {
44 { 0x00, 0xff, ' ', 1, "NOP"},
45 { 0x01, 0xff, 'A', 3, "AJMP %A"},
46 { 0x02, 0xff, 'L', 4, "LJMP %l"},
47 { 0x03, 0xff, ' ', 1, "RR A"},
48 { 0x04, 0xff, ' ', 1, "INC A"},
49 { 0x05, 0xff, ' ', 2, "INC %a"},
50 { 0x06, 0xff, ' ', 1, "INC @R0"},
51 { 0x07, 0xff, ' ', 1, "INC @R1"},
52 { 0x08, 0xff, ' ', 1, "INC R0"},
53 { 0x09, 0xff, ' ', 1, "INC R1"},
54 { 0x0a, 0xff, ' ', 1, "INC R2"},
55 { 0x0b, 0xff, ' ', 1, "INC R3"},
56 { 0x0c, 0xff, ' ', 1, "INC R4"},
57 { 0x0d, 0xff, ' ', 1, "INC R5"},
58 { 0x0e, 0xff, ' ', 1, "INC R6"},
59 { 0x0f, 0xff, ' ', 1, "INC R7"},
60 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
61 { 0x11, 0xff, 'a', 3, "ACALL %A"},
62 { 0x12, 0xff, 'l', 4, "LCALL %l"},
63 { 0x13, 0xff, ' ', 1, "RRC A"},
64 { 0x14, 0xff, ' ', 1, "DEC A"},
65 { 0x15, 0xff, ' ', 2, "DEC %a"},
66 { 0x16, 0xff, ' ', 1, "DEC @R0"},
67 { 0x17, 0xff, ' ', 1, "DEC @R1"},
68 { 0x18, 0xff, ' ', 1, "DEC R0"},
69 { 0x19, 0xff, ' ', 1, "DEC R1"},
70 { 0x1a, 0xff, ' ', 1, "DEC R2"},
71 { 0x1b, 0xff, ' ', 1, "DEC R3"},
72 { 0x1c, 0xff, ' ', 1, "DEC R4"},
73 { 0x1d, 0xff, ' ', 1, "DEC R5"},
74 { 0x1e, 0xff, ' ', 1, "DEC R6"},
75 { 0x1f, 0xff, ' ', 1, "DEC R7"},
76 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
77 { 0x21, 0xff, 'A', 3, "AJMP %A"},
78 { 0x22, 0xff, '_', 1, "RET"},
79 { 0x23, 0xff, ' ', 1, "RL A"},
80 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
81 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
82 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
83 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
84 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
85 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
86 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
87 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
88 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
89 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
90 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
91 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
92 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
93 { 0x31, 0xff, 'a', 3, "ACALL %A"},
94 { 0x32, 0xff, '_', 1, "RETI"},
95 { 0x33, 0xff, ' ', 1, "RLC A"},
96 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
97 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
98 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
99 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
100 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
101 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
102 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
103 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
104 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
105 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
106 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
107 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
108 { 0x40, 0xff, 'r', 2, "JC %r"},
109 { 0x41, 0xff, 'A', 3, "AJMP %A"},
110 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
111 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
112 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
113 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
114 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
115 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
116 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
117 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
118 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
119 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
120 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
121 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
122 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
123 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
124 { 0x50, 0xff, 'r', 2, "JNC %r"},
125 { 0x51, 0xff, 'a', 3, "ACALL %A"},
126 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
127 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
128 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
129 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
130 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
131 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
132 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
133 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
134 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
135 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
136 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
137 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
138 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
139 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
140 { 0x60, 0xff, 'r', 2, "JZ %r"},
141 { 0x61, 0xff, 'A', 3, "AJMP %A"},
142 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
143 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
144 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
145 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
146 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
147 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
148 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
149 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
150 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
151 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
152 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
153 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
154 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
155 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
156 { 0x70, 0xff, 'r', 2, "JNZ %r"},
157 { 0x71, 0xff, 'a', 3, "ACALL %A"},
158 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
159 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
160 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
161 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
162 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
163 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
164 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
165 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
166 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
167 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
168 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
169 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
170 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
171 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
172 { 0x80, 0xff, 's', 2, "SJMP %r"},
173 { 0x81, 0xff, 'A', 3, "AJMP %A"},
174 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
175 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
176 { 0x84, 0xff, ' ', 1, "DIV AB"},
177 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
178 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
179 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
180 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
181 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
182 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
183 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
184 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
185 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
186 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
187 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
188 { 0x90, 0xff, ' ', 4, "MOV DPTR,#%6"},
189 { 0x91, 0xff, 'a', 3, "ACALL %A"},
190 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
191 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
192 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
193 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
194 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
195 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
196 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
197 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
198 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
199 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
200 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
201 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
202 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
203 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
204 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
205 { 0xa1, 0xff, 'A', 3, "AJMP %A"},
206 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
207 { 0xa3, 0xff, ' ', 1, "INC DPTR"},
208 { 0xa4, 0xff, ' ', 1, "MUL AB"},
209 { 0xa5, 0xff, '_', 1, "-"},
210 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
211 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
212 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
213 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
214 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
215 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
216 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
217 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
218 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
219 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
220 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
221 { 0xb1, 0xff, 'a', 3, "ACALL %A"},
222 { 0xb2, 0xff, ' ', 2, "CPL %b"},
223 { 0xb3, 0xff, ' ', 1, "CPL C"},
224 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
225 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
226 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
227 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
228 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
229 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
230 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
231 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
232 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
233 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
234 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
235 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
236 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
237 { 0xc1, 0xff, 'A', 3, "AJMP %A"},
238 { 0xc2, 0xff, ' ', 2, "CLR %b"},
239 { 0xc3, 0xff, ' ', 1, "CLR C"},
240 { 0xc4, 0xff, ' ', 1, "SWAP A"},
241 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
242 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
243 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
244 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
245 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
246 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
247 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
248 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
249 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
250 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
251 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
252 { 0xd0, 0xff, ' ', 2, "POP %a"},
253 { 0xd1, 0xff, 'a', 3, "ACALL %A"},
254 { 0xd2, 0xff, ' ', 2, "SETB %b"},
255 { 0xd3, 0xff, ' ', 1, "SETB C"},
256 { 0xd4, 0xff, ' ', 1, "DA A"},
257 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
258 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
259 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
260 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
261 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
262 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
263 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
264 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
265 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
266 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
267 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
268 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
269 { 0xe1, 0xff, 'A', 3, "AJMP %A"},
270 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
271 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
272 { 0xe4, 0xff, ' ', 1, "CLR A"},
273 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
274 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
275 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
276 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
277 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
278 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
279 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
280 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
281 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
282 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
283 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
284 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
285 { 0xf1, 0xff, 'a', 3, "ACALL %A"},
286 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
287 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
288 { 0xf4, 0xff, ' ', 1, "CPL A"},
289 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
290 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
291 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
292 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
293 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
294 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
295 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
296 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
297 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
298 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
299 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
304 * Making an 390 CPU object
307 t_uc390::t_uc390(int Itype, int Itech, class cl_sim *asim):
308 t_uc52(Itype, Itech, asim)
310 if (Itype == CPU_DS390F) {
311 printf("FLAT24 MODE SET, warning: experimental code\n");
319 *____________________________________________________________________________
323 t_uc390::inst_inc_addr(uchar code)
327 addr= get_direct(fetch(), &event_at.wi, &event_at.ws);
329 /* mask off the 2Hex bit adjacent to the 1H bit which selects
330 which DPTR we use. This is a feature of 80C390.
331 You can do INC DPS and it only effects bit 1. */
333 (*addr) ^= 1; /* just toggle */
344 *____________________________________________________________________________
349 t_uc390::inst_inc_dptr(uchar code)
353 unsigned char pl,ph,dps;
364 if (dps & 1) { /* alternate DPTR */
365 if (dps & 0x80) /* decr set */
366 dptr= sfr->get(ph)*256 + sfr->get(pl) - 1;
368 dptr= sfr->get(ph)*256 + sfr->get(pl) + 1;
370 if (dps & 0x40) /* decr set */
371 dptr= sfr->get(ph)*256 + sfr->get(pl) - 1;
373 dptr= sfr->get(ph)*256 + sfr->get(pl) + 1;
376 sfr->set(event_at.ws= ph, (dptr >> 8) & 0xff);
377 sfr->set(pl, dptr & 0xff);
379 if (dps & 0x20) { /* auto-switch dptr */
380 sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */
387 * 0x73 1 24 JMP @A+DPTR
388 *____________________________________________________________________________
393 t_uc390::inst_jmp_$a_dptr(uchar code)
395 unsigned char pl,ph,dps;
406 PC= (sfr->get(ph)*256 + sfr->get(pl) +
407 read_mem(MEM_SFR, ACC)) &
415 * 0x90 3 24 MOV DPTR,#data
416 *____________________________________________________________________________
421 t_uc390::inst_mov_dptr_$data(uchar code)
423 unsigned char pl,ph,dps;
434 //if ((sfr->get(ACON) & 0x3) == 2)
436 fetch(); /* throw away msb of address for now */
439 sfr->set(event_at.ws= ph, fetch());
440 sfr->set(pl, fetch());
442 if (dps & 0x20) { /* auto-switch dptr */
443 sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */
452 * 0x93 1 24 MOVC A,@A+DPTR
453 *____________________________________________________________________________
458 t_uc390::inst_movc_a_$a_dptr(uchar code)
460 unsigned char pl,ph,dps;
471 sfr->set(ACC, get_mem(MEM_ROM, event_at.rc=
472 (sfr->get(ph)*256+sfr->get(pl) +
473 sfr->get(ACC)) & (EROM_SIZE-1)));
475 if (dps & 0x20) { /* auto-switch dptr */
476 sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */
484 * 0xe0 1 24 MOVX A,@DPTR
485 *____________________________________________________________________________
490 t_uc390::inst_movx_a_$dptr(uchar code)
492 unsigned char pl,ph,dps;
503 sfr->set(event_at.ws= ACC,
504 get_mem(MEM_XRAM, event_at.rx=sfr->get(ph)*256+sfr->get(pl)));
506 if (dps & 0x20) { /* auto-switch dptr */
507 sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */
514 * 0xf0 1 24 MOVX @DPTR,A
515 *____________________________________________________________________________
520 t_uc390::inst_movx_$dptr_a(uchar code)
522 unsigned char pl,ph,dps;
533 set_mem(MEM_XRAM, event_at.wx= sfr->get(ph)*256+sfr->get(pl),
534 sfr->get(event_at.rs= ACC));
536 if (dps & 0x20) { /* auto-switch dptr */
537 sfr->set(DPS, (dps ^ 1)); /* toggle dual-dptr switch */
544 * 0x[02468ace]1 2 24 AJMP addr
545 *____________________________________________________________________________
550 t_uc390::inst_ajmp_addr(uchar code)
555 /* throw away high address byte for now... */
556 h= (code >> 5) & 0x07;
559 PC= (PC & 0xf800) | (h*256 + l);
562 h= (code >> 5) & 0x07;
564 PC= (PC & 0xf800) | (h*256 + l);
572 * 0x02 3 24 LJMP addr
573 *____________________________________________________________________________
578 t_uc390::inst_ljmp(uchar code)
581 fetch(); /* throw away msb of address for now */
583 PC= fetch()*256 + fetch();
585 PC= fetch()*256 + fetch();
592 * 0x[13579bdf]1 2 24 ACALL addr
593 *____________________________________________________________________________
598 t_uc390::inst_acall_addr(uchar code)
600 uchar h, l, *sp, *aof_SP;
604 /* throw away msb of address for now */
605 h= (code >> 5) & 0x07;
610 aof_SP= &((sfr->umem8)[SP]);
611 //MEM(MEM_SFR)[SP]++;
613 proc_write_sp(*aof_SP);
614 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
617 (*sp)= PC & 0xff; // push low byte
619 //MEM(MEM_SFR)[SP]++;
621 proc_write_sp(*aof_SP);
622 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
625 (*sp)= (PC >> 8) & 0xff; // push high byte
626 PC= (PC & 0xf800) | (h*256 + l);
628 // need to push msb, skip for now...
631 /* stock mcs51 mode */
632 h= (code >> 5) & 0x07;
634 aof_SP= &((sfr->umem8)[SP]);
635 //MEM(MEM_SFR)[SP]++;
637 proc_write_sp(*aof_SP);
638 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
641 (*sp)= PC & 0xff; // push low byte
643 //MEM(MEM_SFR)[SP]++;
645 proc_write_sp(*aof_SP);
646 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
649 (*sp)= (PC >> 8) & 0xff; // push high byte
650 PC= (PC & 0xf800) | (h*256 + l);
659 * 0x12 3 24 LCALL addr
660 *____________________________________________________________________________
665 t_uc390::inst_lcall(uchar code, uint addr)
667 uchar h= 0, l= 0, *sp, *aof_SP;
672 /* this is a normal lcall */
674 fetch(); /* drop for now */
682 /* else, this is interrupt processing */
684 aof_SP= &((sfr->umem8)[SP]);
685 //MEM(MEM_SFR)[SP]++;
687 proc_write_sp(*aof_SP);
688 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
691 (*sp)= PC & 0xff; // push low byte
695 //MEM(MEM_SFR)[SP]++;
697 proc_write_sp(*aof_SP);
698 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
701 (*sp)= (PC >> 8) & 0xff; // push high byte
713 *____________________________________________________________________________
718 t_uc390::inst_ret(uchar code)
720 uchar h, l, *sp, *aof_SP;
723 aof_SP= &((sfr->umem8)[SP]);
724 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
728 //MEM(MEM_SFR)[SP]--;
730 proc_write_sp(*aof_SP);
733 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
737 //MEM(MEM_SFR)[SP]--;
739 proc_write_sp(*aof_SP);
751 *____________________________________________________________________________
756 t_uc390::inst_reti(uchar code)
758 uchar h, l, *sp, *aof_SP;
761 aof_SP= &((sfr->umem8)[SP]);
762 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
766 //MEM(MEM_SFR)[SP]--;
768 proc_write_sp(*aof_SP);
771 sp= get_indirect(*aof_SP/*sfr->get(SP)*/, &res);
775 //MEM(MEM_SFR)[SP]--;
777 proc_write_sp(*aof_SP);
785 class it_level *il= (class it_level *)(it_levels->top());
789 il= (class it_level *)(it_levels->pop());
797 * Disassembling an instruction
801 t_uc390::dis_tbl(void)
812 t_uc390::disass(t_addr addr, char *sep)
814 char work[256], temp[20], c[2];
815 char *buf, *p, *b, *t;
819 t_uc51::disass(addr, sep);
822 code= get_mem(MEM_ROM, addr);
824 b= dis_tbl()[code].mnemonic;
832 case 'A': // absolute address
834 //sprintf(temp, "%04lx",
836 // (((code>>5)&0x07)*256 +
837 // get_mem(MEM_ROM, addr+1)));
839 sprintf(temp, "%06lx",
841 (((code>>5)&0x07)*(256*256) +
842 (get_mem(MEM_ROM, addr+1) * 256) +
843 get_mem(MEM_ROM, addr+2)));
845 case 'l': // long address
846 sprintf(temp, "%06lx",
847 get_mem(MEM_ROM, addr+1)*(256*256) + get_mem(MEM_ROM, addr+1)*256
848 + get_mem(MEM_ROM, addr+2));
849 //get_mem(MEM_ROM, addr+1)*256 + get_mem(MEM_ROM, addr+2));
851 case 'a': // addr8 (direct address) at 2nd byte
852 if (!get_name(get_mem(MEM_ROM, addr+1), sfr_tbl(), temp))
853 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
855 case '8': // addr8 (direct address) at 3rd byte
856 if (!get_name(get_mem(MEM_ROM, addr+2), sfr_tbl(), temp))
857 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
858 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2));
860 case 'b': // bitaddr at 2nd byte
861 if (get_name(get_mem(MEM_ROM, addr+1), bit_tbl(), temp))
863 if (get_name(get_bitidx(get_mem(MEM_ROM, addr+1)),
867 sprintf(c, "%1ld", get_mem(MEM_ROM, addr+1)&0x07);
871 sprintf(temp, "%02x.%ld",
872 get_bitidx(get_mem(MEM_ROM, addr+1)),
873 get_mem(MEM_ROM, addr+1)&0x07);
875 case 'r': // rel8 address at 2nd byte
876 sprintf(temp, "%04lx",
877 addr+2+(signed char)(get_mem(MEM_ROM, addr+1)));
879 case 'R': // rel8 address at 3rd byte
880 sprintf(temp, "%04lx",
881 addr+3+(signed char)(get_mem(MEM_ROM, addr+2)));
883 case 'd': // data8 at 2nd byte
884 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+1));
886 case 'D': // data8 at 3rd byte
887 sprintf(temp, "%02lx", get_mem(MEM_ROM, addr+2));
889 case '6': // data24 at 2nd(HH)-3rd(H)-4th(L) byte
890 sprintf(temp, "%06lx",
891 get_mem(MEM_ROM, addr+1)*256*256 + get_mem(MEM_ROM, addr+2)*256 +
892 get_mem(MEM_ROM, addr+3));
906 p= strchr(work, ' ');
913 buf= (char *)malloc(6+strlen(p)+1);
915 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
916 for (p= work, b= buf; *p != ' '; p++, b++)
922 while (strlen(buf) < 6)
931 /* End of s51.src/uc390.cc */