2 * Simulator of microcontrollers (uc390.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
8 * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
11 /* This file is part of microcontroller simulator: ucsim.
13 UCSIM is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 UCSIM is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with UCSIM; see the file COPYING. If not, write to the Free
25 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 // Bernhard's ToDo list:
31 // - implement math accelerator
32 // - consider ACON bits
33 // - buy some memory to run s51 with 2*4 Meg ROM/XRAM
35 // strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
36 // strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
48 #include "uc390hwcl.h"
56 * Names of instructions
59 struct dis_entry disass_390f[] = {
60 { 0x00, 0xff, ' ', 1, "NOP"},
61 { 0x01, 0xff, 'A', 3, "AJMP %A"},
62 { 0x02, 0xff, 'L', 4, "LJMP %l"},
63 { 0x03, 0xff, ' ', 1, "RR A"},
64 { 0x04, 0xff, ' ', 1, "INC A"},
65 { 0x05, 0xff, ' ', 2, "INC %a"},
66 { 0x06, 0xff, ' ', 1, "INC @R0"},
67 { 0x07, 0xff, ' ', 1, "INC @R1"},
68 { 0x08, 0xff, ' ', 1, "INC R0"},
69 { 0x09, 0xff, ' ', 1, "INC R1"},
70 { 0x0a, 0xff, ' ', 1, "INC R2"},
71 { 0x0b, 0xff, ' ', 1, "INC R3"},
72 { 0x0c, 0xff, ' ', 1, "INC R4"},
73 { 0x0d, 0xff, ' ', 1, "INC R5"},
74 { 0x0e, 0xff, ' ', 1, "INC R6"},
75 { 0x0f, 0xff, ' ', 1, "INC R7"},
76 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
77 { 0x11, 0xff, 'a', 3, "ACALL %A"},
78 { 0x12, 0xff, 'l', 4, "LCALL %l"},
79 { 0x13, 0xff, ' ', 1, "RRC A"},
80 { 0x14, 0xff, ' ', 1, "DEC A"},
81 { 0x15, 0xff, ' ', 2, "DEC %a"},
82 { 0x16, 0xff, ' ', 1, "DEC @R0"},
83 { 0x17, 0xff, ' ', 1, "DEC @R1"},
84 { 0x18, 0xff, ' ', 1, "DEC R0"},
85 { 0x19, 0xff, ' ', 1, "DEC R1"},
86 { 0x1a, 0xff, ' ', 1, "DEC R2"},
87 { 0x1b, 0xff, ' ', 1, "DEC R3"},
88 { 0x1c, 0xff, ' ', 1, "DEC R4"},
89 { 0x1d, 0xff, ' ', 1, "DEC R5"},
90 { 0x1e, 0xff, ' ', 1, "DEC R6"},
91 { 0x1f, 0xff, ' ', 1, "DEC R7"},
92 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
93 { 0x21, 0xff, 'A', 3, "AJMP %A"},
94 { 0x22, 0xff, '_', 1, "RET"},
95 { 0x23, 0xff, ' ', 1, "RL A"},
96 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
97 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
98 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
99 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
100 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
101 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
102 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
103 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
104 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
105 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
106 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
107 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
108 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
109 { 0x31, 0xff, 'a', 3, "ACALL %A"},
110 { 0x32, 0xff, '_', 1, "RETI"},
111 { 0x33, 0xff, ' ', 1, "RLC A"},
112 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
113 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
114 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
115 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
116 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
117 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
118 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
119 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
120 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
121 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
122 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
123 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
124 { 0x40, 0xff, 'r', 2, "JC %r"},
125 { 0x41, 0xff, 'A', 3, "AJMP %A"},
126 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
127 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
128 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
129 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
130 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
131 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
132 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
133 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
134 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
135 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
136 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
137 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
138 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
139 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
140 { 0x50, 0xff, 'r', 2, "JNC %r"},
141 { 0x51, 0xff, 'a', 3, "ACALL %A"},
142 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
143 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
144 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
145 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
146 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
147 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
148 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
149 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
150 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
151 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
152 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
153 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
154 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
155 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
156 { 0x60, 0xff, 'r', 2, "JZ %r"},
157 { 0x61, 0xff, 'A', 3, "AJMP %A"},
158 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
159 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
160 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
161 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
162 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
163 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
164 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
165 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
166 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
167 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
168 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
169 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
170 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
171 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
172 { 0x70, 0xff, 'r', 2, "JNZ %r"},
173 { 0x71, 0xff, 'a', 3, "ACALL %A"},
174 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
175 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
176 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
177 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
178 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
179 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
180 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
181 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
182 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
183 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
184 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
185 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
186 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
187 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
188 { 0x80, 0xff, 's', 2, "SJMP %r"},
189 { 0x81, 0xff, 'A', 3, "AJMP %A"},
190 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
191 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
192 { 0x84, 0xff, ' ', 1, "DIV AB"},
193 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
194 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
195 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
196 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
197 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
198 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
199 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
200 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
201 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
202 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
203 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
204 { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
205 { 0x91, 0xff, 'a', 3, "ACALL %A"},
206 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
207 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
208 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
209 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
210 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
211 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
212 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
213 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
214 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
215 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
216 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
217 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
218 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
219 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
220 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
221 { 0xa1, 0xff, 'A', 3, "AJMP %A"},
222 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
223 { 0xa3, 0xff, ' ', 1, "INC DPTR"},
224 { 0xa4, 0xff, ' ', 1, "MUL AB"},
225 { 0xa5, 0xff, '_', 1, "-"},
226 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
227 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
228 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
229 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
230 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
231 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
232 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
233 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
234 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
235 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
236 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
237 { 0xb1, 0xff, 'a', 3, "ACALL %A"},
238 { 0xb2, 0xff, ' ', 2, "CPL %b"},
239 { 0xb3, 0xff, ' ', 1, "CPL C"},
240 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
241 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
242 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
243 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
244 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
245 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
246 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
247 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
248 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
249 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
250 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
251 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
252 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
253 { 0xc1, 0xff, 'A', 3, "AJMP %A"},
254 { 0xc2, 0xff, ' ', 2, "CLR %b"},
255 { 0xc3, 0xff, ' ', 1, "CLR C"},
256 { 0xc4, 0xff, ' ', 1, "SWAP A"},
257 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
258 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
259 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
260 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
261 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
262 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
263 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
264 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
265 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
266 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
267 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
268 { 0xd0, 0xff, ' ', 2, "POP %a"},
269 { 0xd1, 0xff, 'a', 3, "ACALL %A"},
270 { 0xd2, 0xff, ' ', 2, "SETB %b"},
271 { 0xd3, 0xff, ' ', 1, "SETB C"},
272 { 0xd4, 0xff, ' ', 1, "DA A"},
273 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
274 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
275 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
276 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
277 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
278 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
279 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
280 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
281 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
282 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
283 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
284 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
285 { 0xe1, 0xff, 'A', 3, "AJMP %A"},
286 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
287 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
288 { 0xe4, 0xff, ' ', 1, "CLR A"},
289 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
290 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
291 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
292 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
293 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
294 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
295 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
296 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
297 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
298 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
299 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
300 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
301 { 0xf1, 0xff, 'a', 3, "ACALL %A"},
302 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
303 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
304 { 0xf4, 0xff, ' ', 1, "CPL A"},
305 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
306 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
307 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
308 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
309 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
310 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
311 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
312 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
313 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
314 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
315 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
320 * Making an 390 CPU object
323 cl_uc390::cl_uc390 (int Itype, int Itech, class cl_sim *asim):
324 cl_uc52 (Itype, Itech, asim)
326 if (Itype == CPU_DS390F)
328 printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n");
331 // todo: add interrupt sources
335 cl_uc390::mk_hw_elements (void)
339 cl_uc52::mk_hw_elements();
340 hws->add (h = new cl_uc390_hw (this));
345 cl_uc390::make_memories(void)
347 class cl_address_space *as;
349 rom= as= new cl_address_space(MEM_ROM_ID, 0, 0x20000, 8);
351 address_spaces->add(as);
352 iram= as= new cl_address_space(MEM_IRAM_ID, 0, 0x100, 8);
354 address_spaces->add(as);
355 sfr= as= new cl_address_space(MEM_SFR_ID, 0x80, 0x80, 8);
357 address_spaces->add(as);
358 xram= as= new cl_address_space(MEM_XRAM_ID, 0, 0x100000+128, 8);
360 address_spaces->add(as);
361 as= new cl_address_space(MEM_IXRAM_ID, 0, 0x1000, 8);
363 address_spaces->add(as);
365 class cl_address_decoder *ad;
366 class cl_memory_chip *chip;
368 chip= new cl_memory_chip("rom_chip", 0x20000, 8, 0xff);
371 ad= new cl_address_decoder(as= rom, chip, 0, 0x1ffff, 0);
373 as->decoders->add(ad);
376 chip= new cl_memory_chip("iram_chip", 0x100, 8, 0);
379 ad= new cl_address_decoder(as= iram, chip, 0, 0xff, 0);
381 as->decoders->add(ad);
384 chip= new cl_memory_chip("xram_chip", 0x100000+128, 8, 0);
387 ad= new cl_address_decoder(as= xram, chip, 0, 0x10007f, 0);
389 as->decoders->add(ad);
392 chip= new cl_memory_chip("ixram_chip", 0x1000, 8);
395 ad= new cl_address_decoder(as= address_space(MEM_IXRAM_ID),
398 as->decoders->add(ad);
401 chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
404 ad= new cl_address_decoder(as= sfr, chip, 0x80, 0xff, 0);
406 as->decoders->add(ad);
409 acc= sfr->get_cell(ACC);
410 psw= sfr->get_cell(PSW);
415 * Setting up SFR area to reset value
419 cl_uc390::clear_sfr(void)
421 cl_uc52::clear_sfr();
423 sfr->write(0x80, 0xff); /* P4 */
424 sfr->write(0x81, 0x07); /* SP */
425 sfr->write(0x86, 0x04); /* DPS */
426 sfr->write(0x90, 0xff); /* P1 */
427 sfr->write(0x92, 0xbf); /* P4CNT */
428 sfr->write(0x9b, 0xfc); /* ESP */
430 sfr->/*write*/set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
432 sfr->/*write*/set(ACON, 0xf8); /* ACON */
433 sfr->write(0xa0, 0xff); /* P2 */
434 sfr->write(0xa1, 0xff); /* P5 */
435 sfr->write(0xa3, 0x09); /* COC */
436 sfr->write(0xb0, 0xff); /* P3 */
437 sfr->write(0xb8, 0x80); /* IP */
438 sfr->write(0xc5, 0x10); /* STATUS */
439 sfr->write(0xc6, 0x10); /* MCON */
440 sfr->write(0xc7, 0xff); /* TA */
441 sfr->write(0xc9, 0xe4); /* T2MOD */
442 sfr->write(0xd2, 0x2f); /* MCNT1 */
443 sfr->write(0xe3, 0x09); /* C1C */
448 cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
451 if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
453 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
456 id/*type*/ = MEM_IXRAM_ID;
458 return cl_51core::read_mem(id/*type*/, addr); /* 24 bit */
462 cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
464 if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
466 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
469 /*type*/id = MEM_IXRAM_ID;
471 return cl_51core::get_mem (/*type*/id, addr);
475 cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
477 if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
479 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
482 /*type*/id = MEM_IXRAM_ID;
484 cl_51core::write_mem (/*type*/id, addr, val);
488 cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
490 if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
492 (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
495 /*type*/id = MEM_IXRAM_ID;
497 cl_51core::set_mem (id/*type*/, addr, val);
501 *____________________________________________________________________________
505 cl_uc390::push_byte (t_mem uc)
509 sp = sfr->wadd (SP, 1);
510 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
512 if (sp == 0) /* overflow SP */
514 sp += (sfr->read (ESP) & 0x3) * 256;
515 write_mem (MEM_IXRAM_ID, sp, uc); // fixme
519 class cl_memory_cell *stck;
521 stck = iram->get_cell (sp);
527 cl_uc390::pop_byte (void)
532 if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
535 sp += (sfr->read (ESP) & 0x3) * 256;
536 temp = read_mem (MEM_IXRAM_ID, sp); // fixme
537 sp = sfr->wadd (SP, -1);
538 if (sp == 0xff) /* underflow SP */
544 class cl_memory_cell *stck;
546 stck = iram->get_cell (sfr->get (SP));
548 sp = sfr->wadd (SP, -1);
555 *____________________________________________________________________________
560 cl_uc390::inst_inc_dptr (uchar code)
564 uchar pl, ph, px, dps;
566 dps = sfr->get (DPS);
580 dptr = sfr->read (ph) * 256 + sfr->read (pl);
581 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
582 dptr += sfr->read (px) *256*256;
583 if (dps & 0x80) /* decr set */
588 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
589 sfr->write (px, (dptr >> 16) & 0xff);
590 sfr->write (ph, (dptr >> 8) & 0xff);
591 sfr->write (pl, dptr & 0xff);
593 if (dps & 0x20) /* auto-switch dptr */
594 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
600 * 0x73 1 24 JMP @A+DPTR
601 *____________________________________________________________________________
606 cl_uc390::inst_jmp_Sa_dptr (uchar code)
608 uchar pl, ph, px, dps;
610 dps = sfr->get (DPS);
624 PC = rom->validate_address(sfr->read (ph) * 256 + sfr->read (pl) +
626 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
627 PC += sfr->read (px) * 256*256;
634 * 0x90 3 24 MOV DPTR,#data
635 *____________________________________________________________________________
640 cl_uc390::inst_mov_dptr_Sdata (uchar code)
642 uchar pl, ph, px, dps;
644 dps = sfr->get (DPS);
658 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
659 sfr->write (px, fetch ());
660 sfr->write (ph, fetch ());
661 sfr->write (pl, fetch ());
663 if (dps & 0x20) /* auto-switch dptr */
664 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
672 * 0x93 1 24 MOVC A,@A+DPTR
673 *____________________________________________________________________________
678 cl_uc390::inst_movc_a_Sa_dptr (uchar code)
680 uchar pl, ph, px, dps;
682 dps = sfr->get (DPS);
696 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
697 acc->write (rom->read ((sfr->read (px) * 256*256 +
698 sfr->read (ph) * 256 + sfr->read (pl) +
701 acc->write (rom->read ((sfr->read (ph) * 256 + sfr->read (pl) +
704 if (dps & 0x20) /* auto-switch dptr */
705 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
712 * 0xc0 2 24 PUSH addr
713 *____________________________________________________________________________
718 cl_uc390::inst_push (uchar code)
720 class cl_memory_cell *cell;
722 cell = get_direct(fetch());
723 t_addr sp_before= sfr->get(SP);
725 push_byte (data= cell->read());
726 class cl_stack_op *so=
727 new cl_stack_push(instPC, data, sp_before, sfr->get(SP));
737 *____________________________________________________________________________
742 cl_uc390::inst_pop (uchar code)
744 class cl_memory_cell *cell;
746 t_addr sp_before= sfr->get(SP);
748 cell = get_direct (fetch());
749 cell->write (data= pop_byte());
750 class cl_stack_op *so=
751 new cl_stack_pop(instPC, data, sp_before, sfr->get(SP));
760 * 0xe0 1 24 MOVX A,@DPTR
761 *____________________________________________________________________________
766 cl_uc390::inst_movx_a_Sdptr (uchar code)
768 uchar pl, ph, px, dps;
770 dps = sfr->get (DPS);
784 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
785 acc->write (read_mem (MEM_XRAM_ID,
786 sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl)));
788 acc->write (read_mem (MEM_XRAM_ID,
789 sfr->read (ph) * 256 + sfr->read (pl)));
791 if (dps & 0x20) /* auto-switch dptr */
792 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
799 * 0xf0 1 24 MOVX @DPTR,A
800 *____________________________________________________________________________
805 cl_uc390::inst_movx_Sdptr_a (uchar code)
807 uchar pl, ph, px, dps;
809 dps = sfr->get (DPS);
823 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
824 write_mem (MEM_XRAM_ID,
825 sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl),
828 write_mem (MEM_XRAM_ID,
829 sfr->read (ph) * 256 + sfr->read (pl),
832 if (dps & 0x20) /* auto-switch dptr */
833 sfr->write (DPS, dps ^ 1); /* toggle dual-dptr switch */
840 * 0x[02468ace]1 2 24 AJMP addr
841 *____________________________________________________________________________
846 cl_uc390::inst_ajmp_addr (uchar code)
850 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
852 x = (code >> 5) & 0x07;
855 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
859 h = (code >> 5) & 0x07;
861 PC = (PC & 0xf800) | (h * 256 + l);
868 * 0x02 3 24 LJMP addr
869 *____________________________________________________________________________
874 cl_uc390::inst_ljmp (uchar code)
878 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
883 PC = x * 256*256 + h * 256 + l;
896 * 0x[13579bdf]1 2 24 ACALL addr
897 *____________________________________________________________________________
902 cl_uc390::inst_acall_addr (uchar code)
906 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
908 x = (code >> 5) & 0x07;
912 push_byte ( PC & 0xff); /* push low byte */
913 push_byte ((PC >> 8) & 0xff); /* push high byte */
914 push_byte ((PC >> 16) & 0xff); /* push x byte */
916 PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
920 /* stock mcs51 mode */
921 class cl_memory_cell *stck;
924 h = (code >> 5) & 0x07;
926 sp = sfr->wadd (SP, 1);
927 stck = iram->get_cell (sp);
928 stck->write (PC & 0xff); // push low byte
930 sp = sfr->wadd (SP, 1);
931 stck = iram->get_cell (sp);
932 stck->write ((PC >> 8) & 0xff); // push high byte
933 PC = (PC & 0xf800) | (h*256 + l);
942 *____________________________________________________________________________
947 cl_uc390::inst_lcall (uchar code, uint addr, bool intr)
949 uchar x = 0, h = 0, l = 0;
952 { /* this is a normal lcall */
953 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
958 /* else, this is interrupt processing */
960 t_addr sp_before= sfr->get(SP);
961 push_byte ( PC & 0xff); /* push low byte */
962 push_byte ((PC >> 8) & 0xff); /* push high byte */
965 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
967 push_byte ((PC >> 16) & 0xff); /* push x byte */
969 PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
971 PC = x * 256*256 + h * 256 + l;
975 class cl_stack_op *so;
979 so= new cl_stack_intr(instPC, PC, pushed, sp_before, sfr->get(SP));
984 so= new cl_stack_call(instPC, PC, pushed, sp_before, sfr->get(SP));
994 *____________________________________________________________________________
999 cl_uc390::inst_ret (uchar code)
1003 t_addr sp_before= sfr->get(SP);
1004 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1011 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1014 PC = x * 256*256 + h * 256 + l;
1019 class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sfr->get(SP));
1027 *____________________________________________________________________________
1032 cl_uc390::inst_reti (uchar code)
1036 t_addr sp_before= sfr->get(SP);
1037 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1043 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1046 PC = x * 256*256 + h * 256 + l;
1051 interrupt->was_reti = DD_TRUE;
1052 class it_level *il = (class it_level *) (it_levels->top ());
1056 il = (class it_level *) (it_levels->pop ());
1060 class cl_stack_op *so=
1061 new cl_stack_iret(instPC, PC, sp_before, sfr->get(SP));
1069 * Disassembling an instruction
1073 cl_uc390::dis_tbl (void)
1075 if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
1079 //t_uc51::dis_tbl ();
1084 cl_uc390::disass (t_addr addr, char *sep)
1086 char work[256], temp[20], c[2];
1087 char *buf, *p, *b, *t;
1090 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1091 return cl_51core::disass (addr, sep);
1092 code = rom->get(addr);
1095 b = dis_tbl()[code].mnemonic;
1103 case 'A': // absolute address
1105 // sprintf (temp, "%04lx",
1107 // (((code >> 5) & 0x07) * 256 +
1108 // rom->get (addr + 1)));
1110 sprintf (temp, "%06lx",
1111 (addr & 0xf80000L) |
1112 (((code >> 5) & 0x07) * (256 * 256) +
1113 (rom->get (addr + 1) * 256) +
1114 rom->get (addr + 2)));
1116 case 'l': // long address
1117 sprintf (temp, "%06lx",
1118 rom->get (addr + 1) * (256*256L) +
1119 rom->get (addr + 2) * 256 +
1120 rom->get (addr + 3));
1121 // rom->get (addr + 1) * 256 + rom->get (addr + 2));
1123 case 'a': // addr8 (direct address) at 2nd byte
1124 if (!get_name (rom->get (addr + 1), sfr_tbl (), temp))
1125 sprintf (temp, "%02"_M_"x", rom->get (addr + 1));
1127 case '8': // addr8 (direct address) at 3rd byte
1128 if (!get_name (rom->get (addr + 2), sfr_tbl (), temp))
1129 sprintf (temp, "%02"_M_"x", rom->get (addr + 2));
1131 case 'b': // bitaddr at 2nd byte
1133 t_addr ba = rom->get (addr+1);
1134 if (get_name (ba, bit_tbl(), temp))
1136 if (get_name ((ba<128) ? ((ba/8)+32) : (ba&0xf8), sfr_tbl(), temp))
1139 sprintf (c, "%1"_M_"d", ba & 0x07);
1143 sprintf (temp, "%02x.%"_M_"d", (ba<128) ? ((ba/8)+32) : (ba&0xf8),
1147 case 'r': // rel8 address at 2nd byte
1148 sprintf (temp, "%04"_A_"x",
1149 t_addr (addr + 2 + (signed char) (rom->get (addr + 1))));
1151 case 'R': // rel8 address at 3rd byte
1152 sprintf (temp, "%04"_A_"x",
1153 t_addr (addr + 3 + (signed char) (rom->get (addr + 2))));
1155 case 'd': // data8 at 2nd byte
1156 sprintf (temp, "%02"_M_"x", rom->get (addr + 1));
1158 case 'D': // data8 at 3rd byte
1159 sprintf (temp, "%02"_M_"x", rom->get (addr + 2));
1174 p = strchr (work, ' ');
1177 buf = strdup (work);
1181 buf = (char *) malloc (6 + strlen (p) + 1);
1183 buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
1184 for (p = work, b = buf; *p != ' '; p++, b++)
1189 while (strlen (buf) < 6)
1198 cl_uc390::print_regs (class cl_console *con)
1203 if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
1205 cl_51core::print_regs (con);
1208 start = sfr->get (PSW) & 0x18;
1209 //dump_memory(iram, &start, start+7, 8, /*sim->cmd_out()*/con, sim);
1210 iram->dump (start, start + 7, 8, con);
1211 start = sfr->get (PSW) & 0x18;
1212 data = iram->get (iram->get (start));
1213 con->dd_printf("%06x %02x %c",
1214 iram->get (start), data, isprint (data) ? data : '.');
1215 con->dd_printf(" ACC= 0x%02x %3d %c B= 0x%02x",
1216 sfr->get (ACC), sfr->get (ACC),
1217 isprint (sfr->get (ACC)) ?
1218 (sfr->get (ACC)) : '.', sfr->get (B));
1220 data = get_mem (MEM_XRAM_ID,
1221 sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
1222 con->dd_printf (" DPTR= 0x%02x%02x%02x @DPTR= 0x%02x %3d %c\n",
1223 sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
1224 data, data, isprint (data) ? data : '.');
1225 data = iram->get (iram->get (start + 1));
1226 con->dd_printf ("%06x %02x %c", iram->get (start + 1), data,
1227 isprint (data) ? data : '.');
1228 data= sfr->get (PSW);
1229 con->dd_printf (" PSW= 0x%02x CY=%c AC=%c OV=%c P=%c ",
1231 (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
1232 (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0'
1234 /* show stack pointer */
1235 if (sfr->get (ACON) & 0x04)
1236 /* SA: 10 bit stack */
1237 con->dd_printf ("SP10 0x%03x %3d\n",
1238 (sfr->get (ESP) & 3) * 256 + sfr->get (SP),
1239 get_mem (MEM_IXRAM_ID, (sfr->get (ESP) & 3) * 256 + sfr->get (SP))
1242 con->dd_printf ("SP 0x%02x %3d\n",
1244 iram->get (sfr->get (SP))
1246 print_disass (PC, con);
1250 /* End of s51.src/uc390.cc */