2 * Simulator of microcontrollers (regs51.h)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
32 /* Address of SFR registers */
34 #define ACC 0xe0 /* Accumulator */
35 #define B 0xf0 /* B register (scondary accumulator) */
36 #define PSW 0xd0 /* Program Status Word */
37 #define SP 0x81 /* Stack Pointer */
38 #define DPL 0x82 /* Data Pointer Low byte */
39 #define DPH 0x83 /* Data Pointer High byte */
40 #define P0 0x80 /* Port #0 */
41 #define P1 0x90 /* Port #1 */
42 #define P2 0xa0 /* Port #2 */
43 #define P3 0xb0 /* Port #3 */
44 #define IP 0xb8 /* Intrrupt Priority */
45 #define IE 0xa8 /* Interrupt Enable */
46 #define TMOD 0x89 /* Timer MODe */
47 #define TCON 0x88 /* Timer CONtrol */
48 #define T2CON 0xc8 /* Timer #2 CONtrol */
49 #define TH0 0x8c /* Timer #0 High byte */
50 #define TL0 0x8a /* Timer #0 Low byte */
51 #define TH1 0x8d /* Timer #1 High byte */
52 #define TL1 0x8b /* Timer #1 Low byte */
53 #define SCON 0x98 /* Serial line CONtrol */
54 #define TH2 0xcd /* Timer #2 High byte */
55 #define TL2 0xcc /* Timer #2 Low byte */
56 #define RCAP2H 0xcb /* Capture Register of Timer #2 High byte */
57 #define RCAP2L 0xca /* Capture Register of Timer #2 Low byte */
58 #define SBUF 0x99 /* Serial line BUFfer */
59 #define PCON 0x87 /* Power CONtrol */
61 #define AUXR 0x8e /* Auxiliary Register */
62 #define AUXR1 0xa2 /* Secondary Aux Register */
64 #define DPXL 0x84 /* */
65 #define DPL1 0x84 /* 2nd Data Pointer Low byte */
66 #define DPH1 0x85 /* 2nd Data Pointer High byte */
67 #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */
68 #define DPX 0x93 /* Data Pointer HHigh byte */
69 #define DPX1 0x95 /* Data Pointer HHigh byte */
70 #define ESP 0x9B /* Extended Stack Pointer */
71 #define ACON 0x9D /* */
72 #define WDTRST 0xa6 /* */
73 #define IE0 0xa8 /* */
74 #define SADDR 0xa9 /* */
75 #define IPH0 0xb7 /* */
77 #define IPL0 0xb8 /* */
78 #define SADEN 0xb9 /* */
79 #define SPH 0xbd /* */
80 #define T2MOD 0xc9 /* */
81 #define PSW1 0xd1 /* */
84 #define MA 0xd3 /* MA register from math accelerator */
85 #define MB 0xd4 /* MB register from math accelerator */
86 #define MC 0xd5 /* MC register from math accelerator */
87 #define CCON 0xd8 /* */
88 #define CMOD 0xd9 /* */
89 #define CCAPM0 0xda /* */
90 #define CCAPM1 0xdb /* */
91 #define CCAPM2 0xdc /* */
92 #define CCAPM3 0xdd /* */
93 #define CCAPM4 0xde /* */
95 #define CCAP0L 0xea /* */
96 #define CCAP1L 0xeb /* */
97 #define CCAP2L 0xec /* */
98 #define CCAP3L 0xed /* */
99 #define CCAP4L 0xee /* */
100 #define CH 0xf9 /* */
101 #define CCAP0H 0xfa /* */
102 #define CCAP1H 0xfb /* */
103 #define CCAP2H 0xfc /* */
104 #define CCAP3H 0xfd /* */
105 #define CCAP4H 0xfe /* */
107 /* Bit masks of flag bits in PSW (0xd0)*/
109 #define bmCY 0x80 /* carry */
110 #define bmAC 0x40 /* acarry */
111 #define bmF0 0x20 /* flag 0 */
112 #define bmRS1 0x10 /* register select 1 */
113 #define bmRS0 0x08 /* register select 0 */
114 #define bmOV 0x04 /* arithmetic overflow */
115 #define bmP 0x01 /* parity, set by hardware */
117 /* Bit masks in PCON (0x87) */
128 /* Bit masks in IE (0xa8) */
139 /* Bit masks in IP (0xb8) */
149 /* Bit masks in IPL0 (0xb8) */
151 #define bmIPL0_6 0x40
152 #define bmIPL0_5 0x20
153 #define bmIPL0_4 0x10
154 #define bmIPL0_3 0x08
155 #define bmIPL0_2 0x04
156 #define bmIPL0_1 0x02
157 #define bmIPL0_0 0x01
159 /* Bit masks in IPH0 (0xb7) */
161 #define bmIPH0_6 0x40
162 #define bmIPH0_5 0x20
163 #define bmIPH0_4 0x10
164 #define bmIPH0_3 0x08
165 #define bmIPH0_2 0x04
166 #define bmIPH0_1 0x02
167 #define bmIPH0_0 0x01
169 /* Bit masks in P1 (0x90) */
180 /* Bit masks in P3 (0xb0) */
191 /* Bit masks in TMOD (0x89) */
202 /* Bit masks in TCON (0x88) */
213 /* Bit masks in AUXR (0x8e) */
215 #define bmEXTRAM 0x02
216 #define bmDISABLE 0x01
218 /* Bit masks in AUXR1 (0xa2) */
220 #define bmENBOOT 0x20
224 /* Bit masks in T2CON (0xc8) */
233 #define bmCP_RL2 0x01
235 /* Bit masks in SCON (0x98) */
237 #define bmFE_SM0 0x80
248 /* Bit masks in T2MOD (0xc9) */
253 /* Bit masks in CMOD (0xd9) */
261 /* Bit masks in CCON (0xd8) */
271 /* Bit masks in CCAPM0 (0xda) */
281 /* Bit masks in CCAPM1 (0xdb) */
291 /* Bit masks in CCAPM2 (0xdc) */
301 /* Bit masks in CCAPM3 (0xdd) */
311 /* Bit masks in CCAPM4 (0xde) */
332 /* End of s51.src/regs51.h */