2 * Simulator of microcontrollers (regs51.h)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
32 /* Address of SFR registers */
34 #define ACC 0xe0 /* Accumulator */
35 #define B 0xf0 /* B register (scondary accumulator) */
36 #define PSW 0xd0 /* Program Status Word */
37 #define SP 0x81 /* Stack Pointer */
38 #define DPL 0x82 /* Data Pointer Low byte */
39 #define DPH 0x83 /* Data Pointer High byte */
40 #define DPL1 0x84 /* 2nd Data Pointer Low byte */
41 #define DPH1 0x85 /* 2nd Data Pointer High byte */
42 #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1, 2H=AUTO DPTR INCR */
43 #define P0 0x80 /* Port #0 */
44 #define P1 0x90 /* Port #1 */
45 #define P2 0xa0 /* Port #2 */
46 #define P3 0xb0 /* Port #3 */
47 #define IP 0xb8 /* Intrrupt Priority */
48 #define IE 0xa8 /* Interrupt Enable */
49 #define TMOD 0x89 /* Timer MODe */
50 #define TCON 0x88 /* Timer CONtrol */
51 #define T2CON 0xc8 /* Timer #2 CONtrol */
52 #define TH0 0x8c /* Timer #0 High byte */
53 #define TL0 0x8a /* Timer #0 Low byte */
54 #define TH1 0x8d /* Timer #1 High byte */
55 #define TL1 0x8b /* Timer #1 Low byte */
56 #define SCON 0x98 /* Serial line CONtrol */
57 #define TH2 0xcd /* Timer #2 High byte */
58 #define TL2 0xcc /* Timer #2 Low byte */
59 #define RCAP2H 0xcb /* Capture Register of Timer #2 High byte */
60 #define RCAP2L 0xca /* Capture Register of Timer #2 Low byte */
61 #define SBUF 0x99 /* Serial line BUFfer */
62 #define PCON 0x87 /* Power CONtrol */
64 #define AUXR 0x8e /* Auxiliary Register */
65 #define AUXR1 0xa2 /* Secondary Aux Register */
68 #define DPXL 0x84 /* */
69 #define DPL1 0x84 /* 2nd Data Pointer Low byte */
70 #define DPH1 0x85 /* 2nd Data Pointer High byte */
71 #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */
72 #define EXIF 0x91 /* */
73 #define P4CNT 0x92 /* */
74 #define DPX 0x93 /* Data Pointer HHigh byte */
75 #define DPX1 0x95 /* Data Pointer HHigh byte */
76 #define ESP 0x9b /* Extended Stack Pointer */
77 #define ACON 0x9d /* */
79 #define P5CNT 0xa2 /* */
80 #define C0C 0xa3 /* */
81 #define WDTRST 0xa6 /* */
82 #define IE0 0xa8 /* */
83 #define SADDR 0xa9 /* */
84 #define IPH0 0xb7 /* */
86 #define IPL0 0xb8 /* */
87 #define SADEN 0xb9 /* */
88 #define SPH 0xbd /* */
89 #define PMR 0xc4 /* */
90 #define MCON 0xc6 /* */
92 #define T2MOD 0xc9 /* */
93 #define COR 0xce /* */
94 #define PSW1 0xd1 /* */
97 #define MA 0xd3 /* MA register from math accelerator */
98 #define MB 0xd4 /* MB register from math accelerator */
99 #define MC 0xd5 /* MC register from math accelerator */
100 #define CCON 0xd8 /* */
101 #define CMOD 0xd9 /* */
102 #define WDCON 0xd8 /* */
103 #define CCAPM0 0xda /* */
104 #define CCAPM1 0xdb /* */
105 #define CCAPM2 0xdc /* */
106 #define CCAPM3 0xdd /* */
107 #define CCAPM4 0xde /* */
108 #define C1C 0xe3 /* */
109 #define CL 0xe9 /* */
110 #define CCAP0L 0xea /* */
111 #define CCAP1L 0xeb /* */
112 #define CCAP2L 0xec /* */
113 #define CCAP3L 0xed /* */
114 #define CCAP4L 0xee /* */
115 #define CH 0xf9 /* */
116 #define CCAP0H 0xfa /* */
117 #define CCAP1H 0xfb /* */
118 #define CCAP2H 0xfc /* */
119 #define CCAP3H 0xfd /* */
120 #define CCAP4H 0xfe /* */
122 /* Bit masks of flag bits in PSW (0xd0)*/
124 #define bmCY 0x80 /* carry */
125 #define bmAC 0x40 /* acarry */
126 #define bmF0 0x20 /* flag 0 */
127 #define bmRS1 0x10 /* register select 1 */
128 #define bmRS0 0x08 /* register select 0 */
129 #define bmOV 0x04 /* arithmetic overflow */
130 #define bmP 0x01 /* parity, set by hardware */
132 /* Bit masks in PCON (0x87) */
143 /* Bit masks in IE (0xa8) */
154 /* Bit masks in IP (0xb8) */
164 /* Bit masks in IPL0 (0xb8) */
166 #define bmIPL0_6 0x40
167 #define bmIPL0_5 0x20
168 #define bmIPL0_4 0x10
169 #define bmIPL0_3 0x08
170 #define bmIPL0_2 0x04
171 #define bmIPL0_1 0x02
172 #define bmIPL0_0 0x01
174 /* Bit masks in IPH0 (0xb7) */
176 #define bmIPH0_6 0x40
177 #define bmIPH0_5 0x20
178 #define bmIPH0_4 0x10
179 #define bmIPH0_3 0x08
180 #define bmIPH0_2 0x04
181 #define bmIPH0_1 0x02
182 #define bmIPH0_0 0x01
184 /* Bit masks in P1 (0x90) */
195 /* Bit masks in P3 (0xb0) */
206 /* Bit masks in TMOD (0x89) */
217 /* Bit masks in TCON (0x88) */
228 /* Bit masks in AUXR (0x8e) */
230 #define bmEXTRAM 0x02
231 #define bmDISABLE 0x01
233 /* Bit masks in AUXR1 (0xa2) */
235 #define bmENBOOT 0x20
239 /* Bit masks in T2CON (0xc8) */
248 #define bmCP_RL2 0x01
250 /* Bit masks in SCON (0x98) */
252 #define bmFE_SM0 0x80
263 /* Bit masks in T2MOD (0xc9) */
268 /* Bit masks in CMOD (0xd9) */
276 /* Bit masks in CCON (0xd8) */
286 /* Bit masks in CCAPM0 (0xda) */
296 /* Bit masks in CCAPM1 (0xdb) */
306 /* Bit masks in CCAPM2 (0xdc) */
316 /* Bit masks in CCAPM3 (0xdd) */
326 /* Bit masks in CCAPM4 (0xde) */
347 /* End of s51.src/regs51.h */