2 * Simulator of microcontrollers (logic.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 * 0x42 2 12 ORL addr,A
40 *____________________________________________________________________________
45 cl_51core::inst_orl_addr_a(uchar code)
47 class cl_memory_cell *cell;
49 cell= get_direct(fetch());
50 cell->write(cell->read(HW_PORT) | acc->read());
56 * 0x43 3 24 ORL addr,#data
57 *____________________________________________________________________________
62 cl_51core::inst_orl_addr_Sdata(uchar code)
64 class cl_memory_cell *cell;
67 cell= get_direct(fetch());
69 cell->write(cell->read(HW_PORT) | d);
76 * 0x44 2 12 ORL A,#data
77 *____________________________________________________________________________
82 cl_51core::inst_orl_a_Sdata(uchar code)
87 acc->write(d|= fetch());
93 * 0x45 2 12 ORL A,addr
94 *____________________________________________________________________________
99 cl_51core::inst_orl_a_addr(uchar code)
102 class cl_memory_cell *cell;
104 cell= get_direct(fetch());
106 acc->write(d|= cell->read());
112 * 0x46-0x47 1 12 ORL A,@Ri
113 *____________________________________________________________________________
118 cl_51core::inst_orl_a_Sri(uchar code)
121 class cl_memory_cell *cell;
123 cell= iram->get_cell(get_reg(code & 0x01)->read());
125 acc->write(d|= cell->read());
131 * 0x48-0x4f 1 12 ORL A,Rn
132 *____________________________________________________________________________
137 cl_51core::inst_orl_a_rn(uchar code)
142 acc->write(d|= get_reg(code & 0x07)->read());
148 * 0x52 2 12 ANL addr,A
149 *____________________________________________________________________________
154 cl_51core::inst_anl_addr_a(uchar code)
156 class cl_memory_cell *cell;
158 cell= get_direct(fetch());
159 cell->write(cell->read(HW_PORT) & acc->read());
165 * 0x53 3 24 ANL addr,#data
166 *____________________________________________________________________________
171 cl_51core::inst_anl_addr_Sdata(uchar code)
173 class cl_memory_cell *cell;
176 cell= get_direct(fetch());
178 cell->write(cell->read(HW_PORT) & d);
185 * 0x54 2 12 ANL A,#data
186 *____________________________________________________________________________
191 cl_51core::inst_anl_a_Sdata(uchar code)
196 acc->write(d & fetch());
202 * 0x55 2 12 ANL A,addr
203 *____________________________________________________________________________
208 cl_51core::inst_anl_a_addr(uchar code)
211 class cl_memory_cell *cell;
213 cell= get_direct(fetch());
215 acc->write(d & cell->read());
221 * 0x56-0x57 1 12 ANL A,@Ri
222 *____________________________________________________________________________
227 cl_51core::inst_anl_a_Sri(uchar code)
230 class cl_memory_cell *cell;
232 cell= iram->get_cell(get_reg(code & 0x01)->read());
234 acc->write(d & cell->read());
240 * 0x58-0x5f 1 12 ANL A,Rn
241 *____________________________________________________________________________
246 cl_51core::inst_anl_a_rn(uchar code)
251 acc->write(d & get_reg(code & 0x07)->read());
257 * 0x62 2 12 XRL addr,A
258 *____________________________________________________________________________
263 cl_51core::inst_xrl_addr_a(uchar code)
265 class cl_memory_cell *cell;
267 cell= get_direct(fetch());
268 cell->write(cell->read(HW_PORT) ^ acc->read());
274 * 0x63 3 24 XRL addr,#data
275 *____________________________________________________________________________
280 cl_51core::inst_xrl_addr_Sdata(uchar code)
282 class cl_memory_cell *cell;
284 cell= get_direct(fetch());
285 cell->write(cell->read(HW_PORT) ^ fetch());
292 * 0x64 2 12 XRL A,#data
293 *____________________________________________________________________________
298 cl_51core::inst_xrl_a_Sdata(uchar code)
303 acc->write(d ^ fetch());
309 * 0x65 2 12 XRL A,addr
310 *____________________________________________________________________________
315 cl_51core::inst_xrl_a_addr(uchar code)
318 class cl_memory_cell *cell;
320 cell= get_direct(fetch());
322 acc->write(d ^ cell->read());
328 * 0x66-0x67 1 12 XRL A,@Ri
329 *____________________________________________________________________________
334 cl_51core::inst_xrl_a_Sri(uchar code)
337 class cl_memory_cell *cell;
339 cell= iram->get_cell(get_reg(code & 0x01)->read());
341 acc->write(d ^ cell->read());
347 * 0x68-0x6f 1 12 XRL A,Rn
348 *____________________________________________________________________________
353 cl_51core::inst_xrl_a_rn(uchar code)
358 acc->write(d ^ get_reg(code & 0x07)->read());
365 *____________________________________________________________________________
370 cl_51core::inst_cpl_a(uchar code)
372 acc->write(~(acc->read()));
377 /* End of s51.src/logic.cc */