2 * Simulator of microcontrollers (jmp.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 /* Bugs fixed by Sandeep Dutta:
29 * relative<->absolute jump in "jmp @a+dptr"
41 #include "interruptcl.h"
45 * 0x[02468ace]1 2 24 AJMP addr
46 *____________________________________________________________________________
51 cl_51core::inst_ajmp_addr(uchar code)
55 h= (code >> 5) & 0x07;
58 PC= (PC & 0xf800) | (h*256 + l);
64 * 0x10 3 12 JBC bit,addr
65 *____________________________________________________________________________
70 cl_51core::inst_jbc_bit_addr(uchar code)
78 class cl_address_space *mem;
79 if ((mem= bit2mem(bitaddr, &a, &m)) == 0)
81 t_mem d= mem->read(a, HW_PORT);
82 mem->write(a, d & ~m);
84 PC= rom->validate_address(PC + (signed char)jaddr);
92 *____________________________________________________________________________
97 cl_51core::inst_ljmp(uchar code)
99 PC= fetch()*256 + fetch();
106 * 0x[13579bdf]1 2 24 ACALL addr
107 *____________________________________________________________________________
112 cl_51core::inst_acall_addr(uchar code)
115 class cl_memory_cell *stck;
116 t_mem sp, sp_before/*, sp_after*/;
118 h= (code >> 5) & 0x07;
120 sp_before= sfr->get(SP);
121 sp= sfr->wadd(SP, 1);
123 stck= iram->get_cell(sp);
124 stck->write(PC & 0xff); // push low byte
127 sp= /*sp_after*= */sfr->wadd(SP, 1);
129 stck= iram->get_cell(sp);
130 stck->write((PC >> 8) & 0xff); // push high byte
132 PC= (PC & 0xf800) | (h*256 + l);
133 class cl_stack_op *so= new cl_stack_call(instPC, PC, pushed, sp_before, sp);
141 * 0x12 3 24 LCALL addr
142 *____________________________________________________________________________
147 cl_51core::inst_lcall(uchar code, uint addr, bool intr)
150 t_mem sp, sp_before/*, sp_after*/;
151 class cl_memory_cell *stck;
158 sp_before= sfr->get(SP);
159 sp= sfr->wadd(SP, 1);
161 stck= iram->get_cell(sp);
162 stck->write(PC & 0xff); // push low byte
166 sp= sfr->wadd(SP, 1);
168 stck= iram->get_cell(sp);
169 stck->write((PC >> 8) & 0xff); // push high byte
175 class cl_stack_op *so;
177 so= new cl_stack_intr(instPC, PC, pushed, sp_before, sp/*_after*/);
179 so= new cl_stack_call(instPC, PC, pushed, sp_before, sp/*_after*/);
187 * 0x20 3 24 JB bit,addr
188 *____________________________________________________________________________
193 cl_51core::inst_jb_bit_addr(uchar code)
195 uchar bitaddr, jaddr;
199 class cl_address_space *mem;
200 if ((mem= bit2mem(bitaddr= fetch(), &a, &m)) == 0)
204 if (mem->read(a) & m)
205 PC= rom->validate_address(PC + (signed char)jaddr);
212 *____________________________________________________________________________
217 cl_51core::inst_ret(uchar code)
220 t_mem sp, sp_before/*, sp_after*/;
221 class cl_memory_cell *stck;
223 sp= sp_before= sfr->read(SP);
224 stck= iram->get_cell(sp);
226 sp= sfr->wadd(SP, -1);
229 stck= iram->get_cell(sp);
231 sp= sfr->wadd(SP, -1);
233 class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sp/*_after*/);
241 * 0x30 3 24 JNB bit,addr
242 *____________________________________________________________________________
247 cl_51core::inst_jnb_bit_addr(uchar code)
249 uchar bitaddr, jaddr;
252 class cl_address_space *mem;
254 if ((mem= bit2mem(bitaddr= fetch(), &a, &m)) == 0)
258 if (!(mem->read(a) & m))
259 PC= rom->validate_address(PC + (signed char)jaddr);
266 *____________________________________________________________________________
271 cl_51core::inst_reti(uchar code)
274 t_mem sp, sp_before, sp_after;
275 class cl_memory_cell *stck;
277 sp= sp_before= sfr->read(SP);
278 stck= iram->get_cell(sp);
280 sp= sfr->wadd(SP, -1);
283 stck= iram->get_cell(sp);
285 sp= sp_after= sfr->wadd(SP, -1);
288 interrupt->was_reti= DD_TRUE;
289 class it_level *il= (class it_level *)(it_levels->top());
293 il= (class it_level *)(it_levels->pop());
296 class cl_stack_op *so=
297 new cl_stack_iret(instPC, PC, sp_before, sp_after);
306 *____________________________________________________________________________
311 cl_51core::inst_jc_addr(uchar code)
318 PC= rom->validate_address(PC + (signed char)jaddr);
325 *____________________________________________________________________________
330 cl_51core::inst_jnc_addr(uchar code)
337 PC= rom->validate_address(PC + (signed char)jaddr);
344 *____________________________________________________________________________
349 cl_51core::inst_jz_addr(uchar code)
356 PC= rom->validate_address(PC + (signed char)jaddr);
363 *____________________________________________________________________________
368 cl_51core::inst_jnz_addr(uchar code)
375 PC= rom->validate_address(PC + (signed char)jaddr);
381 * 0x73 1 24 JMP @A+DPTR
382 *____________________________________________________________________________
387 cl_51core::inst_jmp_Sa_dptr(uchar code)
389 PC= rom->validate_address(sfr->read(DPH)*256 + sfr->read(DPL) + acc->read());
396 * 0x80 2 24 SJMP addr
397 *____________________________________________________________________________
402 cl_51core::inst_sjmp(uchar code)
404 signed char target= fetch();
406 PC= rom->validate_address(PC + target);
413 * 0xb4 3 24 CJNE A,#data,addr
414 *____________________________________________________________________________
419 cl_51core::inst_cjne_a_Sdata_addr(uchar code)
421 uchar data, jaddr, ac;
426 SFR_SET_C((ac= acc->read()) < data);
428 PC= rom->validate_address(PC + (signed char)jaddr);
434 * 0xb5 3 24 CJNE A,addr,addr
435 *____________________________________________________________________________
440 cl_51core::inst_cjne_a_addr_addr(uchar code)
444 class cl_memory_cell *cell;
446 cell= get_direct(a= fetch());
450 SFR_SET_C(acc->get() < data);
451 if (acc->read() != data)
452 PC= rom->validate_address(PC + (signed char)jaddr);
458 * 0xb6-0xb7 3 24 CJNE @Ri,#data,addr
459 *____________________________________________________________________________
464 cl_51core::inst_cjne_Sri_Sdata_addr(uchar code)
467 class cl_memory_cell *cell;
469 cell= iram->get_cell(get_reg(code & 0x01)->read());
474 SFR_SET_C((d= cell->read()) < data);
476 PC= rom->validate_address(PC + (signed char)jaddr);
482 * 0xb8-0xbf 3 24 CJNE Rn,#data,addr
483 *____________________________________________________________________________
488 cl_51core::inst_cjne_rn_Sdata_addr(uchar code)
491 class cl_memory_cell *reg;
493 reg = get_reg(code & 0x07);
498 SFR_SET_C((r= reg->read()) < data);
500 PC= rom->validate_address(PC + (signed char)jaddr);
506 * 0xd5 3 24 DJNZ addr,addr
507 *____________________________________________________________________________
512 cl_51core::inst_djnz_addr_addr(uchar code)
515 class cl_memory_cell *cell;
517 cell = get_direct(fetch());
520 t_mem d= cell->read(HW_PORT);//cell->wadd(-1);
523 PC= rom->validate_address(PC + (signed char)jaddr);
529 * 0xd8-0xdf 2 24 DJNZ Rn,addr
530 *____________________________________________________________________________
535 cl_51core::inst_djnz_rn_addr(uchar code)
538 class cl_memory_cell *reg;
540 reg = get_reg(code & 0x07);
543 t_mem r= reg->wadd(-1);
545 PC= rom->validate_address(PC + (signed char)jaddr);
550 /* End of s51.src/jmp.cc */