2 * Simulator of microcontrollers (interrupt.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
35 #include "interruptcl.h"
41 cl_interrupt::cl_interrupt(class cl_uc *auc):
42 cl_hw(auc, HW_INTERRUPT, 0, "irq")
48 cl_interrupt::init(void)
50 sfr= uc->address_space(MEM_SFR_ID);
53 //sfr->register_hw(IE, this, 0);
54 register_cell(sfr, IE, 0, wtd_restore);
55 register_cell(sfr, TCON, &cell_tcon, wtd_restore_write);
56 bit_INT0= sfr->read(P3) & bm_INT0;
57 bit_INT1= sfr->read(P3) & bm_INT1;
63 cl_interrupt::added_to_uc(void)
65 uc->it_sources->add(new cl_it_src(bmEX0, TCON, bmIE0, 0x0003, true,
67 uc->it_sources->add(new cl_it_src(bmEX1, TCON, bmIE1, 0x0013, true,
72 cl_interrupt::write(class cl_memory_cell *cell, t_mem *val)
74 if (cell == cell_tcon)
76 bit_IT0= *val & bmIT0;
77 bit_IT1= *val & bmIT1;
85 cl_interrupt::mem_cell_changed(class cl_m *mem, t_addr addr)
90 cl_interrupt::tick(int cycles)
92 if (!bit_IT0 && !bit_INT0)
93 cell_tcon->set_bit1(bmIE0);
94 if (!bit_IT1 && !bit_INT1)
95 cell_tcon->set_bit1(bmIE1);
100 cl_interrupt::reset(void)
106 cl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params)
108 struct ev_port_changed *ep= (struct ev_port_changed *)params;
110 if (where->cathegory == HW_PORT &&
111 he == EV_PORT_CHANGED &&
114 t_mem p3n= ep->new_pins & ep->new_value;
115 t_mem p3o= ep->pins & ep->prev_value;
119 cell_tcon->set_bit1(bmIE0);
123 cell_tcon->set_bit1(bmIE1);
124 bit_INT0= p3n & bm_INT0;
125 bit_INT1= p3n & bm_INT1;
131 cl_interrupt::print_info(class cl_console_base *con)
133 int ie= sfr->get(IE);
136 con->dd_printf("Interrupts are %s. Interrupt sources:\n",
137 (ie&bmEA)?"enabled":"disabled");
138 con->dd_printf(" Handler En Pr Req Act Name\n");
139 for (i= 0; i < uc->it_sources->count; i++)
141 class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i));
142 con->dd_printf(" 0x%06x", is->addr);
143 con->dd_printf(" %-3s", (ie&(is->ie_mask))?"en":"dis");
144 con->dd_printf(" %2d", uc->it_priority(is->ie_mask));
145 con->dd_printf(" %-3s",
146 (sfr->get(is->src_reg)&(is->src_mask))?
148 con->dd_printf(" %-3s", (is->active)?"act":"no");
149 con->dd_printf(" %s", object_name(is));
150 con->dd_printf("\n");
152 con->dd_printf("Active interrupt service(s):\n");
153 con->dd_printf(" Pr Handler PC Source\n");
154 for (i= 0; i < uc->it_levels->count; i++)
156 class it_level *il= (class it_level *)(uc->it_levels->at(i));
159 con->dd_printf(" %2d", il->level);
160 con->dd_printf(" 0x%06x", il->addr);
161 con->dd_printf(" 0x%06x", il->PC);
162 con->dd_printf(" %s", (il->source)?(object_name(il->source)):
164 con->dd_printf("\n");
170 /* End of s51.src/interrupt.cc */