2 * Simulator of microcontrollers (glob.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
35 * Names of instructions
38 struct dis_entry disass_51[]= {
39 { 0x00, 0xff, ' ', 1, "NOP"},
40 { 0x01, 0xff, 'A', 2, "AJMP %A"},
41 { 0x02, 0xff, 'L', 3, "LJMP %l"},
42 { 0x03, 0xff, ' ', 1, "RR A"},
43 { 0x04, 0xff, ' ', 1, "INC A"},
44 { 0x05, 0xff, ' ', 2, "INC %a"},
45 { 0x06, 0xff, ' ', 1, "INC @R0"},
46 { 0x07, 0xff, ' ', 1, "INC @R1"},
47 { 0x08, 0xff, ' ', 1, "INC R0"},
48 { 0x09, 0xff, ' ', 1, "INC R1"},
49 { 0x0a, 0xff, ' ', 1, "INC R2"},
50 { 0x0b, 0xff, ' ', 1, "INC R3"},
51 { 0x0c, 0xff, ' ', 1, "INC R4"},
52 { 0x0d, 0xff, ' ', 1, "INC R5"},
53 { 0x0e, 0xff, ' ', 1, "INC R6"},
54 { 0x0f, 0xff, ' ', 1, "INC R7"},
55 { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
56 { 0x11, 0xff, 'a', 2, "ACALL %A"},
57 { 0x12, 0xff, 'l', 3, "LCALL %l"},
58 { 0x13, 0xff, ' ', 1, "RRC A"},
59 { 0x14, 0xff, ' ', 1, "DEC A"},
60 { 0x15, 0xff, ' ', 2, "DEC %a"},
61 { 0x16, 0xff, ' ', 1, "DEC @R0"},
62 { 0x17, 0xff, ' ', 1, "DEC @R1"},
63 { 0x18, 0xff, ' ', 1, "DEC R0"},
64 { 0x19, 0xff, ' ', 1, "DEC R1"},
65 { 0x1a, 0xff, ' ', 1, "DEC R2"},
66 { 0x1b, 0xff, ' ', 1, "DEC R3"},
67 { 0x1c, 0xff, ' ', 1, "DEC R4"},
68 { 0x1d, 0xff, ' ', 1, "DEC R5"},
69 { 0x1e, 0xff, ' ', 1, "DEC R6"},
70 { 0x1f, 0xff, ' ', 1, "DEC R7"},
71 { 0x20, 0xff, 'R', 3, "JB %b,%R"},
72 { 0x21, 0xff, 'A', 2, "AJMP %A"},
73 { 0x22, 0xff, '_', 1, "RET"},
74 { 0x23, 0xff, ' ', 1, "RL A"},
75 { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
76 { 0x25, 0xff, ' ', 2, "ADD A,%a"},
77 { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
78 { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
79 { 0x28, 0xff, ' ', 1, "ADD A,R0"},
80 { 0x29, 0xff, ' ', 1, "ADD A,R1"},
81 { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
82 { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
83 { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
84 { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
85 { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
86 { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
87 { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
88 { 0x31, 0xff, 'a', 2, "ACALL %A"},
89 { 0x32, 0xff, '_', 1, "RETI"},
90 { 0x33, 0xff, ' ', 1, "RLC A"},
91 { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
92 { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
93 { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
94 { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
95 { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
96 { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
97 { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
98 { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
99 { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
100 { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
101 { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
102 { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
103 { 0x40, 0xff, 'r', 2, "JC %r"},
104 { 0x41, 0xff, 'A', 2, "AJMP %A"},
105 { 0x42, 0xff, ' ', 2, "ORL %a,A"},
106 { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
107 { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
108 { 0x45, 0xff, ' ', 2, "ORL A,%a"},
109 { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
110 { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
111 { 0x48, 0xff, ' ', 1, "ORL A,R0"},
112 { 0x49, 0xff, ' ', 1, "ORL A,R1"},
113 { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
114 { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
115 { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
116 { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
117 { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
118 { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
119 { 0x50, 0xff, 'r', 2, "JNC %r"},
120 { 0x51, 0xff, 'a', 2, "ACALL %A"},
121 { 0x52, 0xff, ' ', 2, "ANL %a,A"},
122 { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
123 { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
124 { 0x55, 0xff, ' ', 2, "ANL A,%a"},
125 { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
126 { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
127 { 0x58, 0xff, ' ', 1, "ANL A,R0"},
128 { 0x59, 0xff, ' ', 1, "ANL A,R1"},
129 { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
130 { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
131 { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
132 { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
133 { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
134 { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
135 { 0x60, 0xff, 'r', 2, "JZ %r"},
136 { 0x61, 0xff, 'A', 2, "AJMP %A"},
137 { 0x62, 0xff, ' ', 2, "XRL %a,A"},
138 { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
139 { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
140 { 0x65, 0xff, ' ', 2, "XRL A,%a"},
141 { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
142 { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
143 { 0x68, 0xff, ' ', 1, "XRL A,R0"},
144 { 0x69, 0xff, ' ', 1, "XRL A,R1"},
145 { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
146 { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
147 { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
148 { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
149 { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
150 { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
151 { 0x70, 0xff, 'r', 2, "JNZ %r"},
152 { 0x71, 0xff, 'a', 2, "ACALL %A"},
153 { 0x72, 0xff, ' ', 2, "ORL C,%b"},
154 { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
155 { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
156 { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
157 { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
158 { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
159 { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
160 { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
161 { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
162 { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
163 { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
164 { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
165 { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
166 { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
167 { 0x80, 0xff, 's', 2, "SJMP %r"},
168 { 0x81, 0xff, 'A', 2, "AJMP %A"},
169 { 0x82, 0xff, ' ', 2, "ANL C,%b"},
170 { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
171 { 0x84, 0xff, ' ', 1, "DIV AB"},
172 { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
173 { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
174 { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
175 { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
176 { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
177 { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
178 { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
179 { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
180 { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
181 { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
182 { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
183 { 0x90, 0xff, ' ', 3, "MOV DPTR,#%6"},
184 { 0x91, 0xff, 'a', 2, "ACALL %A"},
185 { 0x92, 0xff, ' ', 2, "MOV %b,C"},
186 { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
187 { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
188 { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
189 { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
190 { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
191 { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
192 { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
193 { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
194 { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
195 { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
196 { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
197 { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
198 { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
199 { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
200 { 0xa1, 0xff, 'A', 2, "AJMP %A"},
201 { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
202 { 0xa3, 0xff, ' ', 1, "INC DPTR"},
203 { 0xa4, 0xff, ' ', 1, "MUL AB"},
204 { 0xa5, 0xff, '_', 1, "-"},
205 { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
206 { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
207 { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
208 { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
209 { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
210 { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
211 { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
212 { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
213 { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
214 { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
215 { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
216 { 0xb1, 0xff, 'a', 2, "ACALL %A"},
217 { 0xb2, 0xff, ' ', 2, "CPL %b"},
218 { 0xb3, 0xff, ' ', 1, "CPL C"},
219 { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
220 { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
221 { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
222 { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
223 { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
224 { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
225 { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
226 { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
227 { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
228 { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
229 { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
230 { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
231 { 0xc0, 0xff, ' ', 2, "PUSH %a"},
232 { 0xc1, 0xff, 'A', 2, "AJMP %A"},
233 { 0xc2, 0xff, ' ', 2, "CLR %b"},
234 { 0xc3, 0xff, ' ', 1, "CLR C"},
235 { 0xc4, 0xff, ' ', 1, "SWAP A"},
236 { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
237 { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
238 { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
239 { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
240 { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
241 { 0xca, 0xff, ' ', 1, "XCH A,R2"},
242 { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
243 { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
244 { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
245 { 0xce, 0xff, ' ', 1, "XCH A,R6"},
246 { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
247 { 0xd0, 0xff, ' ', 2, "POP %a"},
248 { 0xd1, 0xff, 'a', 2, "ACALL %A"},
249 { 0xd2, 0xff, ' ', 2, "SETB %b"},
250 { 0xd3, 0xff, ' ', 1, "SETB C"},
251 { 0xd4, 0xff, ' ', 1, "DA A"},
252 { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
253 { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
254 { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
255 { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
256 { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
257 { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
258 { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
259 { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
260 { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
261 { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
262 { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
263 { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
264 { 0xe1, 0xff, 'A', 2, "AJMP %A"},
265 { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
266 { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
267 { 0xe4, 0xff, ' ', 1, "CLR A"},
268 { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
269 { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
270 { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
271 { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
272 { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
273 { 0xea, 0xff, ' ', 1, "MOV A,R2"},
274 { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
275 { 0xec, 0xff, ' ', 1, "MOV A,R4"},
276 { 0xed, 0xff, ' ', 1, "MOV A,R5"},
277 { 0xee, 0xff, ' ', 1, "MOV A,R6"},
278 { 0xef, 0xff, ' ', 1, "MOV A,R7"},
279 { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
280 { 0xf1, 0xff, 'a', 2, "ACALL %A"},
281 { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
282 { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
283 { 0xf4, 0xff, ' ', 1, "CPL A"},
284 { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
285 { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
286 { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
287 { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
288 { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
289 { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
290 { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
291 { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
292 { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
293 { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
294 { 0xff, 0xff, ' ', 1, "MOV R7,A"},
303 struct name_entry sfr_tab51[]=
305 {CPU_251, 0x84, "DPXL"},
306 {CPU_251|CPU_DS390|CPU_DS390F, 0x93, "DPX"},
307 {CPU_251, 0xa8, "IE0"},
308 {CPU_251, 0xb7, "IPH0"},
309 {CPU_251, 0xb8, "IPL0"},
310 {CPU_251, 0xbd, "SPH"},
311 {CPU_251, 0xd1, "PSW1"},
313 {CPU_DS390|CPU_DS390F, 0x80, "P4"},
314 {CPU_DS390|CPU_DS390F, 0x84, "DPL1"},
315 {CPU_DS390|CPU_DS390F, 0x85, "DPH1"},
316 {CPU_DS390|CPU_DS390F, 0x86, "DPS"},
317 {CPU_DS390|CPU_DS390F, 0x8e, "CKCON"},
318 {CPU_DS390|CPU_DS390F, 0x91, "EXIF"},
319 {CPU_DS390|CPU_DS390F, 0x92, "P4CNT"},
320 {CPU_DS390|CPU_DS390F, 0x95, "DPX1"},
321 {CPU_DS390|CPU_DS390F, 0x96, "C0RMS0"},
322 {CPU_DS390|CPU_DS390F, 0x97, "C0RMS1"},
323 {CPU_DS390|CPU_DS390F, 0x98, "SCON0"},
324 {CPU_DS390|CPU_DS390F, 0x99, "SBUF0"},
325 {CPU_DS390|CPU_DS390F, 0x9b, "ESP"},
326 {CPU_DS390|CPU_DS390F, 0x9c, "AP"},
327 {CPU_DS390|CPU_DS390F, 0x9d, "ACON"},
328 {CPU_DS390|CPU_DS390F, 0x9e, "C0TMA0"},
329 {CPU_DS390|CPU_DS390F, 0x9f, "C0TMA1"},
330 {CPU_DS390|CPU_DS390F, 0xa1, "P5"},
331 {CPU_DS390|CPU_DS390F, 0xa2, "P5CNT"},
332 {CPU_DS390|CPU_DS390F, 0xa3, "C0C"},
333 {CPU_DS390|CPU_DS390F, 0xa4, "C0S"},
334 {CPU_DS390|CPU_DS390F, 0xa5, "C0IR"},
335 {CPU_DS390|CPU_DS390F, 0xa6, "C0TE"},
336 {CPU_DS390|CPU_DS390F, 0xa7, "C0RE"},
337 {CPU_DS390|CPU_DS390F, 0xa9, "SADDR0"},
338 {CPU_DS390|CPU_DS390F, 0xaa, "SADDR1"},
339 {CPU_DS390|CPU_DS390F, 0xab, "C0M1C"},
340 {CPU_DS390|CPU_DS390F, 0xac, "C0M2C"},
341 {CPU_DS390|CPU_DS390F, 0xad, "C0M3C"},
342 {CPU_DS390|CPU_DS390F, 0xae, "C0M4C"},
343 {CPU_DS390|CPU_DS390F, 0xaf, "C0M5C"},
344 {CPU_DS390|CPU_DS390F, 0xb3, "C0M6C"},
345 {CPU_DS390|CPU_DS390F, 0xb4, "C0M7C"},
346 {CPU_DS390|CPU_DS390F, 0xb5, "C0M8C"},
347 {CPU_DS390|CPU_DS390F, 0xb6, "C0M9C"},
348 {CPU_DS390|CPU_DS390F, 0xb7, "C0M10C"},
349 {CPU_DS390|CPU_DS390F, 0xb9, "SADEN0"},
350 {CPU_DS390|CPU_DS390F, 0xba, "SADEN1"},
351 {CPU_DS390|CPU_DS390F, 0xbb, "C0M11C"},
352 {CPU_DS390|CPU_DS390F, 0xbc, "C0M12C"},
353 {CPU_DS390|CPU_DS390F, 0xbd, "C0M13C"},
354 {CPU_DS390|CPU_DS390F, 0xbe, "C0M14C"},
355 {CPU_DS390|CPU_DS390F, 0xbf, "C0M15C"},
356 {CPU_DS390|CPU_DS390F, 0xc0, "SCON1"},
357 {CPU_DS390|CPU_DS390F, 0xc1, "SBUF1"},
358 {CPU_DS390|CPU_DS390F, 0xc4, "PMR"},
359 {CPU_DS390|CPU_DS390F, 0xc5, "STATUS"},
360 {CPU_DS390|CPU_DS390F, 0xc6, "MCON"},
361 {CPU_DS390|CPU_DS390F, 0xc7, "TA"},
362 {CPU_DS390|CPU_DS390F, 0xce, "COR"},
363 {CPU_DS390|CPU_DS390F, 0xd1, "MCNT0"},
364 {CPU_DS390|CPU_DS390F, 0xd2, "MCNT1"},
365 {CPU_DS390|CPU_DS390F, 0xd3, "MA"},
366 {CPU_DS390|CPU_DS390F, 0xd4, "MB"},
367 {CPU_DS390|CPU_DS390F, 0xd5, "MC"},
368 {CPU_DS390|CPU_DS390F, 0xd6, "C1RMS0"},
369 {CPU_DS390|CPU_DS390F, 0xd7, "C1RMS1"},
370 {CPU_DS390|CPU_DS390F, 0xd8, "WDCON"},
371 {CPU_DS390|CPU_DS390F, 0xde, "C1TMA0"},
372 {CPU_DS390|CPU_DS390F, 0xdf, "C1TMA1"},
373 {CPU_DS390|CPU_DS390F, 0xe3, "C1C"},
374 {CPU_DS390|CPU_DS390F, 0xe4, "C1S"},
375 {CPU_DS390|CPU_DS390F, 0xe5, "C11R"},
376 {CPU_DS390|CPU_DS390F, 0xe6, "C1TE"},
377 {CPU_DS390|CPU_DS390F, 0xe7, "C1RE"},
378 {CPU_DS390|CPU_DS390F, 0xe8, "EIE"},
379 {CPU_DS390|CPU_DS390F, 0xea, "MXAX"},
380 {CPU_DS390|CPU_DS390F, 0xeb, "C1M1C"},
381 {CPU_DS390|CPU_DS390F, 0xec, "C1M2C"},
382 {CPU_DS390|CPU_DS390F, 0xed, "C1M3C"},
383 {CPU_DS390|CPU_DS390F, 0xee, "C1M4C"},
384 {CPU_DS390|CPU_DS390F, 0xef, "C1M5C"},
385 {CPU_DS390|CPU_DS390F, 0xf3, "C1M6C"},
386 {CPU_DS390|CPU_DS390F, 0xf4, "C1M7C"},
387 {CPU_DS390|CPU_DS390F, 0xf5, "C1M8C"},
388 {CPU_DS390|CPU_DS390F, 0xf6, "C1M9C"},
389 {CPU_DS390|CPU_DS390F, 0xf7, "C1M10C"},
390 {CPU_DS390|CPU_DS390F, 0xfb, "C1M11C"},
391 {CPU_DS390|CPU_DS390F, 0xfc, "C1M12C"},
392 {CPU_DS390|CPU_DS390F, 0xfd, "C1M13C"},
393 {CPU_DS390|CPU_DS390F, 0xfe, "C1M14C"},
394 {CPU_DS390|CPU_DS390F, 0xff, "C1M15C"},
396 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x80, "P0"},
397 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x81, "SP"},
398 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x82, "DPL"},
399 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x83, "DPH"},
400 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x87, "PCON"},
401 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "TCON"},
402 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "TMOD"},
403 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "TL0"},
404 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "TL1"},
405 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TH0"},
406 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TH1"},
407 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x90, "P1"},
408 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "SCON"},
409 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "SBUF"},
410 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa0, "P2"},
411 {CPU_ALL_51|CPU_ALL_52, 0xa8, "IE"},
412 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xb0, "P3"},
413 {CPU_ALL_51|CPU_ALL_52, 0xb8, "IP"},
414 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "PSW"},
415 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xe0, "ACC"},
416 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xf0, "B"},
418 {CPU_ALL_52|CPU_251, 0xc8, "T2CON"},
419 {CPU_ALL_52|CPU_251, 0xca, "RCAP2L"},
420 {CPU_ALL_52|CPU_251, 0xcb, "RCAP2H"},
421 {CPU_ALL_52|CPU_251, 0xcc, "TL2"},
422 {CPU_ALL_52|CPU_251, 0xcd, "TH2"},
424 {CPU_51R|CPU_89C51R, 0x8e, "AUXR"},
425 {CPU_51R|CPU_89C51R|CPU_251, 0xa6, "WDTRST"},
426 {CPU_51R|CPU_89C51R|CPU_251, 0xa9, "SADDR"},
427 {CPU_51R|CPU_89C51R, 0xb7, "IPH"},
428 {CPU_51R|CPU_89C51R|CPU_251, 0xb9, "SADEN"},
429 {CPU_51R|CPU_89C51R|CPU_251|\
430 CPU_DS390|CPU_DS390F, 0xc9, "T2MOD"}, /* fixme: isn't that CPU_ALL_52? */
432 {CPU_89C51R, 0xa2, "AUXR1"},
433 {CPU_89C51R|CPU_251, 0xd8, "CCON"},
434 {CPU_89C51R|CPU_251, 0xd9, "CMOD"},
435 {CPU_89C51R|CPU_251, 0xda, "CCAPM0"},
436 {CPU_89C51R|CPU_251, 0xdb, "CCAPM1"},
437 {CPU_89C51R|CPU_251, 0xdc, "CCAPM2"},
438 {CPU_89C51R|CPU_251, 0xdd, "CCAPM3"},
439 {CPU_89C51R|CPU_251, 0xde, "CCAPM4"},
440 {CPU_89C51R|CPU_251, 0xe9, "CL"},
441 {CPU_89C51R|CPU_251, 0xea, "CCAP0L"},
442 {CPU_89C51R|CPU_251, 0xeb, "CCAP1L"},
443 {CPU_89C51R|CPU_251, 0xec, "CCAP2L"},
444 {CPU_89C51R|CPU_251, 0xed, "CCAP3L"},
445 {CPU_89C51R|CPU_251, 0xee, "CCAP4L"},
446 {CPU_89C51R|CPU_251, 0xf9, "CH"},
447 {CPU_89C51R|CPU_251, 0xfa, "CCAP0H"},
448 {CPU_89C51R|CPU_251, 0xfb, "CCAP1H"},
449 {CPU_89C51R|CPU_251, 0xfc, "CCAP2H"},
450 {CPU_89C51R|CPU_251, 0xfd, "CCAP3H"},
451 {CPU_89C51R|CPU_251, 0xfe, "CCAP4H"},
461 struct name_entry bit_tab51[]=
464 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd7, "CY"},
465 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd6, "AC"},
466 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd5, "F0"},
467 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd4, "RS1"},
468 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd3, "RS0"},
469 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd2, "OV"},
470 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd1, "F1"},
471 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "P"},
473 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8f, "TF1"},
474 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8e, "TR1"},
475 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TF0"},
476 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TR0"},
477 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "IE1"},
478 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "IT1"},
479 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "IE0"},
480 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "IT0"},
482 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaf, "EA"},
483 {CPU_DS390|CPU_DS390F, 0xae, "ES1"},
484 {CPU_89C51R|CPU_251, 0xae, "EC"},
485 {CPU_ALL_52|CPU_251, 0xad, "ET2"},
486 {CPU_DS390|CPU_DS390F, 0xac, "ES0"},
487 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xac, "ES"},
488 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xab, "ET1"},
489 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaa, "EX1"},
490 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa9, "ET0"},
491 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa8, "EX0"},
493 {CPU_89C51R|CPU_251, 0xbe, "PPC"},
494 {CPU_DS390|CPU_DS390F, 0xbe, "PS1"},
495 {CPU_ALL_52, 0xbd, "PT2"},
496 {CPU_DS390|CPU_DS390F, 0xbc, "PS0"},
497 {CPU_ALL_51|CPU_ALL_52, 0xbc, "PS"},
498 {CPU_ALL_51|CPU_ALL_52, 0xbb, "PT1"},
499 {CPU_ALL_51|CPU_ALL_52, 0xba, "PX1"},
500 {CPU_ALL_51|CPU_ALL_52, 0xb9, "PT0"},
501 {CPU_ALL_51|CPU_ALL_52, 0xb8, "PX0"},
503 {CPU_251, 0xbe, "IPL0.6"},
504 {CPU_251, 0xbd, "IPL0.5"},
505 {CPU_251, 0xbc, "IPL0.4"},
506 {CPU_251, 0xbb, "IPL0.3"},
507 {CPU_251, 0xba, "IPL0.2"},
508 {CPU_251, 0xb9, "IPL0.1"},
509 {CPU_251, 0xb8, "IPL0.0"},
511 {CPU_DS390|CPU_DS390F, 0x9f, "SM0/FE_0"},
512 {CPU_DS390|CPU_DS390F, 0x9e, "SM1_0"},
513 {CPU_DS390|CPU_DS390F, 0x9d, "SM2_0"},
514 {CPU_DS390|CPU_DS390F, 0x9c, "REN_0"},
515 {CPU_DS390|CPU_DS390F, 0x9b, "TB8_0"},
516 {CPU_DS390|CPU_DS390F, 0x9a, "RB8_0"},
517 {CPU_DS390|CPU_DS390F, 0x99, "TI_0"},
518 {CPU_DS390|CPU_DS390F, 0x98, "RI_0"},
520 {CPU_51R|CPU_89C51R|CPU_251, 0x9f, "FE/SM0"},
521 {CPU_ALL_51|CPU_ALL_52, 0x9f, "SM0"},
522 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9e, "SM1"},
523 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9d, "SM2"},
524 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9c, "REN"},
525 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9b, "TB8"},
526 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9a, "RB8"},
527 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "TI"},
528 {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "RI"},
530 {CPU_DS390|CPU_DS390F, 0xc7, "SM0/FE_1"},
531 {CPU_DS390|CPU_DS390F, 0xc6, "SM1_1"},
532 {CPU_DS390|CPU_DS390F, 0xc5, "SM2_1"},
533 {CPU_DS390|CPU_DS390F, 0xc4, "REN_1"},
534 {CPU_DS390|CPU_DS390F, 0xc3, "TB8_1"},
535 {CPU_DS390|CPU_DS390F, 0xc2, "RB8_1"},
536 {CPU_DS390|CPU_DS390F, 0xc1, "TI_1"},
537 {CPU_DS390|CPU_DS390F, 0xc0, "RI_1"},
539 {CPU_ALL_52|CPU_251, 0xcf, "TF2"},
540 {CPU_ALL_52|CPU_251, 0xce, "EXF2"},
541 {CPU_ALL_52|CPU_251, 0xcd, "RCLK"},
542 {CPU_ALL_52|CPU_251, 0xcc, "TCLK"},
543 {CPU_ALL_52|CPU_251, 0xcb, "EXEN2"},
544 {CPU_ALL_52|CPU_251, 0xca, "TR2"},
545 {CPU_ALL_52|CPU_251, 0xc9, "C/T2"},
546 {CPU_ALL_52|CPU_251, 0xc8, "CP/RL2"},
548 {CPU_89C51R|CPU_251, 0xdf, "CF"},
549 {CPU_89C51R|CPU_251, 0xde, "CR"},
550 {CPU_89C51R|CPU_251, 0xdc, "CCF4"},
551 {CPU_89C51R|CPU_251, 0xdb, "CCF3"},
552 {CPU_89C51R|CPU_251, 0xda, "CCF2"},
553 {CPU_89C51R|CPU_251, 0xd9, "CCF1"},
554 {CPU_89C51R|CPU_251, 0xd8, "CCF0"},
556 {CPU_89C51R|CPU_251, 0x97, "CEX4"},
557 {CPU_89C51R|CPU_251, 0x96, "CEX3"},
558 {CPU_89C51R|CPU_251, 0x95, "CEX2"},
559 {CPU_89C51R|CPU_251, 0x94, "CEX1"},
560 {CPU_89C51R|CPU_251, 0x93, "CEX0"},
561 {CPU_89C51R|CPU_251, 0x92, "EXI"},
562 {CPU_89C51R|CPU_251, 0x91, "T2EX"},
563 {CPU_89C51R|CPU_251, 0x90, "T2"},
565 {CPU_DS390|CPU_DS390F, 0xdf, "SMOD_1"},
566 {CPU_DS390|CPU_DS390F, 0xde, "POR,"},
567 {CPU_DS390|CPU_DS390F, 0xdd, "EPF1"},
568 {CPU_DS390|CPU_DS390F, 0xdc, "PF1"},
569 {CPU_DS390|CPU_DS390F, 0xdb, "WDIF"},
570 {CPU_DS390|CPU_DS390F, 0xda, "WTRF"},
571 {CPU_DS390|CPU_DS390F, 0xd9, "EWT"},
572 {CPU_DS390|CPU_DS390F, 0xd8, "RWT"},
574 {CPU_DS390|CPU_DS390F, 0xef, "CANBIE"},
575 {CPU_DS390|CPU_DS390F, 0xee, "C0IE"},
576 {CPU_DS390|CPU_DS390F, 0xed, "C1IE"},
577 {CPU_DS390|CPU_DS390F, 0xec, "EWDI"},
578 {CPU_DS390|CPU_DS390F, 0xeb, "EX5"},
579 {CPU_DS390|CPU_DS390F, 0xea, "EX4"},
580 {CPU_DS390|CPU_DS390F, 0xe9, "EX3"},
581 {CPU_DS390|CPU_DS390F, 0xe8, "EX2"},
583 {CPU_DS390|CPU_DS390F, 0xef, "CANBIP"},
584 {CPU_DS390|CPU_DS390F, 0xee, "C0IP"},
585 {CPU_DS390|CPU_DS390F, 0xed, "C1IP"},
586 {CPU_DS390|CPU_DS390F, 0xec, "PWDI"},
587 {CPU_DS390|CPU_DS390F, 0xeb, "PX5"},
588 {CPU_DS390|CPU_DS390F, 0xea, "PX4"},
589 {CPU_DS390|CPU_DS390F, 0xe9, "PX3"},
590 {CPU_DS390|CPU_DS390F, 0xe8, "PX2"},
596 /* End of s51.src/glob.cc */