2 * Simulator of microcontrollers (move_inst.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
36 *____________________________________________________________________________
40 cl_avr::lpm(t_mem code)
45 addr= ram->get(ZH)*256 + ram->get(ZL);
46 data= rom->read(addr);
48 ram->/*write*/set(0, (data>>8)&0xff);
50 ram->/*write*/set(0, data&0xff);
57 cl_avr::elpm(t_mem code)
64 cl_avr::spm(t_mem code)
71 cl_avr::espm(t_mem code)
79 * LDI Rd,K 16<=d<=31 0<=K<=255
81 *____________________________________________________________________________
85 cl_avr::ldi_Rd_K(t_mem code)
91 K= ((code&0xf00)>>4)|(code&0xf);
98 cl_avr::movw_Rd_Rr(t_mem code)
105 * Load Indirect From SRAM to Register using Index Z
106 * LDD Rd,Z+q 0<=d<=31, 0<=q<=63
107 * 10q0 qq0d dddd 0qqq
108 *____________________________________________________________________________
112 cl_avr::ldd_Rd_Z_q(t_mem code)
118 q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
119 z= ram->get(ZH)*256 + ram->get(ZL);
120 t_mem data= ram->read(z+q);
121 ram->write(d, &data);
128 * Load Indirect From SRAM to Register using Index Y
129 * LDD Rd,Y+q 0<=d<=31, 0<=q<=63
130 * 10q0 qq0d dddd 1qqq
131 *____________________________________________________________________________
135 cl_avr::ldd_Rd_Y_q(t_mem code)
141 q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
142 y= ram->get(YH)*256 + ram->get(YL);
143 t_mem data= ram->read(y+q);
144 ram->write(d, &data);
151 * Store Indirect From Register to SRAM using Index Z
152 * ST Z+q,Rr 0<=r<=31, 0<=q<=63
153 * 10q0 qq1r rrrr 0qqq
154 *____________________________________________________________________________
158 cl_avr::std_Z_q_Rr(t_mem code)
164 q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
165 z= ram->get(ZH)*256 + ram->get(ZL);
166 t_mem data= ram->read(r);
167 ram->write(z+q, &data);
174 * Store Indirect From Register to SRAM using Index Y
175 * ST Y+q,Rr 0<=r<=31, 0<=q<=63
176 * 10q0 qq1r rrrr 1qqq
177 *____________________________________________________________________________
181 cl_avr::std_Y_q_Rr(t_mem code)
187 q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
188 y= ram->get(YH)*256 + ram->get(YL);
189 t_mem data= ram->read(r);
190 ram->write(y+q, &data);
197 * Load Direct from SRAM
198 * LDS Rd,k 0<=d<=31, 0<=k<=65535
199 * 1001 000d dddd 0000
200 * kkkk kkkk kkkk kkkk
201 *____________________________________________________________________________
205 cl_avr::lds_Rd_k(t_mem code)
211 t_mem data= ram->read(k);
212 ram->write(d, &data);
219 * Load Indirect From SRAM to register using Index Z
221 * 1001 000d dddd 0001
222 *____________________________________________________________________________
226 cl_avr::ld_Rd_Z$(t_mem code)
231 z= ram->get(ZH)*256 + ram->get(ZL);
232 t_mem data= ram->read(z);
233 ram->write(d, &data);
234 ram->set(ZL, data= (ram->get(ZL)+1)&0xff);
236 ram->set(ZH, (ram->get(ZH)+1)&0xff);
243 * Load Indirect From SRAM to register using Index Z
245 * 1001 000d dddd 0010
246 *____________________________________________________________________________
250 cl_avr::ld_Rd_$Z(t_mem code)
256 ram->set(ZL, z= (ram->get(ZL)-1)&0xff);
258 ram->set(ZH, (ram->get(ZH)-1)&0xff);
259 z= ram->get(ZH)*256 + z;
261 ram->write(d, &data);
268 cl_avr::lpm_Rd_Z(t_mem code)
275 cl_avr::lpm_Rd_Z$(t_mem code)
282 cl_avr::elpm_Rd_Z(t_mem code)
289 cl_avr::elpm_Rd_Z$(t_mem code)
296 * Load Indirect From SRAM to register using Index Y
298 * 1001 000d dddd 1001
299 *____________________________________________________________________________
303 cl_avr::ld_Rd_Y$(t_mem code)
308 y= ram->get(YH)*256 + ram->get(YL);
309 t_mem data= ram->read(y);
310 ram->write(d, &data);
311 ram->set(YL, data= (ram->get(YL)+1)&0xff);
313 ram->set(YH, (ram->get(YH)+1)&0xff);
320 * Load Indirect From SRAM to register using Index Y
322 * 1001 000d dddd 1010
323 *____________________________________________________________________________
327 cl_avr::ld_Rd_$Y(t_mem code)
333 ram->set(YL, y= (ram->get(YL)-1)&0xff);
335 ram->set(YH, (ram->get(YH)-1)&0xff);
336 y= ram->get(YH)*256 + y;
338 ram->write(d, &data);
345 * Load Indirect From SRAM to register using Index X
347 * 1001 000d dddd 1100
348 *____________________________________________________________________________
352 cl_avr::ld_Rd_X(t_mem code)
357 x= ram->get(XH)*256 + ram->get(XL);
358 t_mem data= ram->read(x);
359 ram->write(d, &data);
366 * Load Indirect From SRAM to register using Index X
368 * 1001 000d dddd 1101
369 *____________________________________________________________________________
373 cl_avr::ld_Rd_X$(t_mem code)
378 x= ram->get(XH)*256 + ram->get(XL);
379 t_mem data= ram->read(x);
380 ram->write(d, &data);
381 ram->set(XL, data= (ram->get(XL)+1)&0xff);
383 ram->set(XH, (ram->get(XH)+1)&0xff);
390 * Load Indirect From SRAM to register using Index X
392 * 1001 000d dddd 1110
393 *____________________________________________________________________________
397 cl_avr::ld_Rd_$X(t_mem code)
403 ram->set(XL, x= (ram->get(XL)-1)&0xff);
405 ram->set(XH, (ram->get(XH)-1)&0xff);
406 x= ram->get(XH)*256 + x;
408 ram->write(d, &data);
415 cl_avr::pop_Rd(t_mem code)
422 * Store Direct to SRAM
423 * STS k,Rr 0<=r<=31, 0<=k<=65535
424 * 1001 001r rrrr 0000
425 * kkkk kkkk kkkk kkkk
426 *____________________________________________________________________________
430 cl_avr::sts_k_Rr(t_mem code)
436 t_mem data= ram->read(r);
437 ram->write(k, &data);
444 * Store Indirect From Register to SRAM using Index Z
446 * 1001 001r rrrr 0001
447 *____________________________________________________________________________
451 cl_avr::st_Z$_Rr(t_mem code)
456 z= ram->get(ZH)*256 + ram->get(ZL);
457 t_mem data= ram->read(r);
458 ram->write(z, &data);
459 ram->set(ZL, data= (ram->get(ZL)+1)&0xff);
461 ram->set(ZH, (ram->get(ZH)+1)&0xff);
468 * Store Indirect From Register to SRAM using Index Z
470 * 1001 001r rrrr 0010
471 *____________________________________________________________________________
475 cl_avr::st_$Z_Rr(t_mem code)
481 ram->set(ZL, z= (ram->get(ZL)-1)&0xff);
483 ram->set(ZH, (ram->get(ZH)-1)&0xff);
484 z= ram->get(ZH)*256 + z;
486 ram->write(z, &data);
493 * Store Indirect From Register to SRAM using Index Y
495 * 1001 001r rrrr 1001
496 *____________________________________________________________________________
500 cl_avr::st_Y$_Rr(t_mem code)
505 y= ram->get(YH)*256 + ram->get(YL);
506 t_mem data= ram->read(r);
507 ram->write(y, &data);
508 ram->set(YL, data= (ram->get(YL)+1)&0xff);
510 ram->set(YH, (ram->get(YH)+1)&0xff);
517 * Store Indirect From Register to SRAM using Index Y
519 * 1001 001r rrrr 1010
520 *____________________________________________________________________________
524 cl_avr::st_$Y_Rr(t_mem code)
530 ram->set(YL, y= (ram->get(YL)-1)&0xff);
532 ram->set(YH, (ram->get(YH)-1)&0xff);
533 y= ram->get(YH)*256 + y;
535 ram->write(y, &data);
542 * Store Indirect From Register to SRAM using Index X
544 * 1001 001r rrrr 1100
545 *____________________________________________________________________________
549 cl_avr::st_X_Rr(t_mem code)
555 x= ram->get(XH)*256 + ram->get(XL);
556 t_mem data= ram->read(r);
557 ram->write(x, &data);
564 * Store Indirect From Register to SRAM using Index X
566 * 1001 001r rrrr 1101
567 *____________________________________________________________________________
571 cl_avr::st_X$_Rr(t_mem code)
576 x= ram->get(XH)*256 + ram->get(XL);
577 t_mem data= ram->read(r);
578 ram->write(x, &data);
579 ram->set(XL, data= (ram->get(XL)+1)&0xff);
581 ram->set(XH, (ram->get(XH)+1)&0xff);
588 * Store Indirect From Register to SRAM using Index X
590 * 1001 001r rrrr 1110
591 *____________________________________________________________________________
595 cl_avr::st_$X_Rr(t_mem code)
601 ram->set(XL, x= (ram->get(XL)-1)&0xff);
603 ram->set(XH, (ram->get(XH)-1)&0xff);
604 x= ram->get(XH)*256 + x;
606 ram->write(x, &data);
613 cl_avr::push_Rr(t_mem code)
622 * 1001 010d dddd 0010
623 *____________________________________________________________________________
627 cl_avr::swap_Rd(t_mem code)
635 data= (data<<4)|temp;
636 ram->write(d, &data);
642 * Load an I/O Port to Register
643 * IN Rd,P 0<=d<=31 0<=P<=63
644 * 1011 0PPd dddd PPPP
645 *____________________________________________________________________________
649 cl_avr::in_Rd_A(t_mem code)
654 P= ((code&0x600)>>5)|(code&0xf);
656 data= ram->read(P+0x20);
657 ram->write(d, &data);
663 * Store Register to I/O Port
664 * OUT P,Rr 0<=r<=31 0<=P<=63
665 * 1011 1PPr rrrr PPPP
666 *____________________________________________________________________________
670 cl_avr::out_A_Rr(t_mem code)
675 P= ((code&0x600)>>5)|(code&0xf);
678 ram->write(P+0x20, &data);
685 * MOV Rd,Rr 0<=d<=31 0<=r<=31
686 * 0010 11rd dddd rrrr
687 *____________________________________________________________________________
691 cl_avr::mov_Rd_Rr(t_mem code)
696 r= ((code&0x200)>>5)|(code&0xf);
697 t_mem data= ram->read(r);
698 ram->write(d, &data);
703 /* End of avr.src/move_inst.cc */